Figure 3-1. (a) A transistor inverter. (b) A NAND gate. (c) A NOR gate.
Gates and Boolean Algebra (2)
Figure 3-2. The symbols and functional behavior for the five basic gates.
Boolean Algebra
(b)
Figure 3-3. (a) The truth table for the majority function of three variables. (b) A circuit for (a).
Implementation of Boolean Functions • • • • •
Write truth table for function Provide inverters to generate complement of each input Draw AND gate for each term with 1 in result column Wire AND gates to appropriate inputs Feed output of all AND gates into an OR gate
Circuit Equivalence (1)
Figure 3-4. Construction of (a) NOT, (b) AND, and (c) OR gates using only NAND gates or only NOR gates.
Circuit Equivalence (2)
Figure 3-5. Two equivalent functions. (a) AB + AC
Circuit Equivalence (3)
Figure 3-5. Two equivalent functions. (b) A(B + C).
Circuit Equivalence (4)
Figure 3-6. Some identities of Boolean algebra.
Circuit Equivalence (5)
Figure 3-7. Alternative symbols for some gates: (a) NAND (b) NOR (c) AND (d) OR
Circuit Equivalence (6)
Figure 3-8. (a) The truth table for the XOR function. (b)–(d) Three circuits for computing it.
Circuit Equivalence (7)
Figure 3-9. (a) Electrical characteristics of a device. (b) Positive logic. (c) Negative logic.
Integrated Circuits
Figure 3-10. Common types of integrated-circuit packages, including a dual-inline package (a), pin grid array (b), and land grid array (c).
Multiplexers (1)
Figure 3-11. An eight-input multiplexer circuit.
Multiplexers (2)
Figure 3-12. (a) An eight-input multiplexer. (b) The same multiplexer wired to compute the majority function.
Decoders
Figure 3-13. A 3-to-8 decoder circuit.
Comparators
Figure 3-14. A simple 4-bit comparator.
Arithmetic Circuits (1)
Figure 3-15. A 1-bit left/right shifter.
Arithmetic Circuits (2)
Figure 3-16. (a) Truth table for 1-bit addition. (b) A circuit for a half adder.
Arithmetic Circuits (3)
Figure 3-17. (a) Truth table for full adder. (b) Circuit for a full adder.
Arithmetic Logic Units (1)
Figure 3-18. A 1-bit ALU.
Arithmetic Logic Units (2)
Figure 3-19. Eight 1-bit ALU slices connected to make an 8-bit ALU. The enables and invert signals are not shown for simplicity.
Clocks
Figure 3-20. (a) A clock. (b) The timing diagram for the clock. (c) Generation of an asymmetric clock.
Latches
Figure 3-21. (a) NOR latch in state 0. (b) NOR latch in state 1. (c) Truth table for NOR.
Clocked SR Latches
Figure 3-22. A clocked SR latch.
Clocked D Latches
Figure 3-23. A clocked D latch.
Flip-Flops (1)
Figure 3-24. (a) A pulse generator. (b) Timing at four points in the circuit.
Flip-Flops (2)
Figure 3-25. A D flip-flop.
Flip-Flops (3)
Figure 3-26. D latches and flip-flops.
Memory Organization (1)
Figure 3-27. An 8-bit register constructed from single-bit flip-flops.
Memory Organization (2a)
Figure 3-28. Logic diagram for a 4 x 3 memory. Each row is one of the four 3-bit words. A read or write operation always reads or writes a complete word.
Memory Organization (2b)
Figure 3-28. Logic diagram for a 4 x 3 memory. Each row is one of the four 3-bit words. A read or write operation always reads or writes a complete word.
Memory Organization (3)
Figure 3-29. (a) A noninverting buffer. (b) Effect of (a) when control is high. (c) Effect of (a) when control is low. (d) An inverting buffer.
Memory Chips (1)
Figure 3-30. Two ways of organizing a 4-Mbit memory chip.
Memory Chips (2)
Figure 3-31. Two ways of organizing a 512-Mbit memory chip.
Nonvolatile Memory Chips(2)
Figure 3-32. A comparison of various memory types.
Field-Programmable Gate Arrays
Figure 3-33. (a) A field-programmable logic array lookup table (LUT). (b) The LUT configuration to create a 3-bit clearable counter.
CPU Chip Control Pins • • • • • •
Bus control Interrupts Bus arbitration Coprocessor signaling Status Miscellaneous
CPU Chips
Figure 3-34. The logical pinout of a generic CPU. The arrows indicate input signals and output signals. The short diagonal lines indicate that multiple pins are used. For a specific CPU, a number will be given to tell how many.
Computer Buses (1)
Figure 3-35. A computer system with multiple buses.
Computer Buses (2)
Figure 3-36. Examples of bus masters and slaves.
Bus Width
Figure 3-37. Growth of an address bus over time.
Synchronous Buses (1)
Figure 3-38. (a) Read timing on a synchronous bus.
Synchronous Buses (2)
Figure 3-38. (b) Specification of some critical times.
Asynchronous Buses
Figure 3-39. Operation of an asynchronous bus.
Four Events of Full-Handshake
Bus Arbitration (1)
Figure 3-40. (a) A centralized one-level bus arbiter using daisy chaining. (b) The same arbiter, but with two levels.
Bus Arbitration (2)
Figure 3-41. Decentralized bus arbitration
Bus Operations (1)
Figure 3-42. A block transfer.
Bus Operations (2)
Figure 3-43. Use of the 8259A interrupt controller
The Intel Core i7
Figure 3-44. The Core i7 physical pinout.
The Core i7’s Logical Pinout
Figure 3-45. Logical pinout of the Core i7.
Pipelining on Core i7’s DDR3 Memory Bus Three steps of memory requests •
Activate phase – opens DRAM memory row, ready for access
•
Read or Write phase – multiple accesses can be made to individual words
•
Precharge phase – closes DRAM memory row, prepare for next activate
Pipelining
Figure 3-46. Pipelining memory requests on the Core i7’s DDR3 interface.
Texas Instruments OMAP4430 System-on-a-Chip (1)
Figure 3-47. The internal organization of the OMAP4430 system-on-a-chip.
Texas Instruments OMAP4430 System-on-a-Chip (2)
Figure 3-48. The OMAP4430 system-on-a-chip pinout.
Atmel ATmega168 Microcontroller (1)
Figure 3-49. Physical pinout of the ATmega168.
Atmel ATmega168 Microcontroller (2a)
Figure 3-50. The internal architecture and logical pinout of the ATmega168 are shown in Internal architecture and logical pinout of the ATmega168.
Atmel ATmega168 Microcontroller (2b)
Figure 3-50. The internal architecture and logical pinout of the ATmega168 are shown in Internal architecture and logical pinout of the ATmega168.
The PCI Bus (1)
Figure 3-51. Architecture of an early Pentium system. The thicker buses have more bandwidth than the thinner ones but the figure is not to scale.
The PCI Bus (2a)
Figure 3-52. The bus structure of a modern Core i7 system.
The PCI Bus (2b)
Figure 3-52. The bus structure of a modern Core i7 system.
PCI Bus Arbitration
Figure 3-53. The PCI bus uses a centralized bus arbiter.
PCI Bus Signals (1)
Figure 3-54. (a) Mandatory PCI bus signals.
PCI Bus Signals (2)
Figure 3-54. (b) Optional PCI bus signals.
PCI Bus Transactions
Figure 3-55. Examples of 32-bit PCI bus transactions. The first three cycles are used for a read operation, then an idle cycle, and then three cycles for a write operation.
The PCI Express Architecture
Figure 3-56. A typical PCI Express system.
The PCI Express Protocol Stack (1)
Figure 3-57. (a) The PCI Express protocol stack. (b) The format of a packet.
The PCI Express Protocol Stack (2) Each transaction uses 1 of 4 address spaces: • Memory space for ordinary reads and writes) • I/O space (for addressing device registers) • Configuration space for system initialization, etc.) • Message space for signaling, interrupts, etc.)
The Universal Serial Bus (1) Goals of USB developers: • Users must not have to set switches or jumpers • Users must not have to open the case to install new devices • There should be only one kind of cable • I/O devices should get power from the cable • Up to 127 devices should be attachable to a single computer • The system should support real-time devices (e.g., sound) • Devices should be installable while the computer is running • No reboot should be needed after installing a new device • The bus and devices should be inexpensive to manufacture
The Universal Serial Bus (2)
Figure 3-58. The USB root hub sends out frames every 1.00 msec.
I/O Interfaces
Figure 3-59. A 24-bit PIO Interface.
Address Decoding
Figure 3-60. Location of the EPROM, RAM, and PIO in our 64-KB address space
