## ECE380 Digital Logic

ECE380 Digital Logic Combinatorial Circuit Building Blocks: Multiplexers Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-1 Multiplex...
Author: Ralf Hawkins
ECE380 Digital Logic Combinatorial Circuit Building Blocks: Multiplexers

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 21-1

Multiplexers • A multiplexer (MUX) circuit has – A number of data inputs – One (or more) select inputs – One output

• It passes the signal value on one of its data inputs to its output based on the value(s) of the select signal(s) s

x1

0 f=x1s’+x2s

x2

1

Electrical & Computer Engineering

s f(s,x1,x2) 0 x1 1 x2

Dr. D. J. Jackson Lecture 21-2

1

Multiplexer implementations

x s y

f The preferred implementation

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 21-3

4-input multiplexer • A 4-input multiplexer ‘selects’ one of four data inputs to be output based on the values of 2 select lines s0 s1 w0

00

w1

01

w2

10

w3

11

f

s1 0 0 1 1

s0 0 1 0 1

f w0 w1 w2 w3

f=s1’s0’w0+s1’s0w1+s1s0’w2+s1s0w3

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 21-4

2

Building a 4-input MUX • A 4-input multiplexer can be constructed using 2input multiplexers s0 w0

0

w1

1

s1 0 f 1

w2

0

w3

1

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 21-5

MUX application (a 2x2 crossbar) • A circuit with n inputs and k outputs whose function is to provide a capability to connect any input to any output is called a nxk crossbar switch – With 2 inputs and 2 outputs, it is called a 2x2 crossbar – Useful in applications where it is necessary to connect one set of wires to another set of wires, where the connection pattern changes from time to time – Telephone switching networks are an example Electrical & Computer Engineering

s x1 x2 x1

y1 y2 0 1

y1

s x2

0

y2

1 Dr. D. J. Jackson Lecture 21-6

3

MUX application (prog. switch) • In programmable devices (PLDs, CPLDs and FPGAs) programmable switches connect wires inside the device – These can be implemented with multiplexers 0/1

i1

storage cell

0/1

i1 f

f

i2 An FPGA logic block with programmable inputs

i2 0/1

0/1

MUX implementation

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 21-7

Logic functions using MUXs • MUXs can be used to synthesize logic functions – The LUT implementations use MUXs to select a (constant) value from a look-up table

• Consider the XOR function a

a 0 0 1 1

b 0 1 0 1

f 0 1 1 0

Electrical & Computer Engineering

b 0

00

1

01

1

10

0

11

f

Dr. D. J. Jackson Lecture 21-8

4

Logic functions using MUXs • The previous XOR solution is not particularly efficient a 0 0 1 1

b 0 1 0 1

f 0 1 1 0

a 0 1

when a=0, f=b when a=1, f=b’

f b b’

a b

0

f

1

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 21-9

Logic functions using MUXs • Implement the following with a 2-input MUX and any additional logic gates a 0 0 1 1

b 0 1 0 1

f 1 1 0 1

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 21-10

5

Logic functions using MUXs • A 3-input XOR can be implemented with two 2-input MUXs x

y

z

f

0

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

0

0

1

1

0

1

0

1

1

0

0

1

1

1

1

Electrical & Computer Engineering

y

y⊕z

x z

0 0

1

f

1

(y⊕z)’

Dr. D. J. Jackson Lecture 21-11

Logic functions using MUXs • Implement the following with 2-input MUXs and any additional logic gates x

y

z

f

0

0

0

1

0

0

1

1

0

1

0

0

0

1

1

1

1

0

0

1

1

0

1

0

1

1

0

0

1

1

1

1

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 21-12

6

Shannon’s expansion theorem • Any Boolean function f(w1,…,wn) can be written in the form f(w1,…,wn)=(w1)’ ⋅ f(0,w2,…,wn)+(w1) ⋅ f(1,w2,…,wn)

• The expansion can be done using any of the n variables • If f(w1,w2,w3)= w1w2+w1w3+w2w3 – Expanding this in terms of w1 gives f(w1,w2,w3)= w1(w2+w3)+(w1)’(w2w3)

f when w1=1

f when w1=0

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 21-13

Shannon’s expansion example w w w 1 2 3

f

0

0 0

0

0

0 1

0

0

1 0

0

0

1 1

1

1

0 0

0

1

0 1

1

1

1 0

1

1

1 1

1

Electrical & Computer Engineering

w 1

f

0 1

w w 2 3 w +w 2 3 w w2 3

w 1 f

Dr. D. J. Jackson Lecture 21-14

7

Shannon’s expansion example x

y

z

f

0

0

0

1

0

0

1

1

0

1

0

0

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

0

1

1

1

0

f=x’y’z’+x’y’z+x’yz+xy’z’+xy’z choose x as the expansion variable f=x’(y’z’+y’z+yz)+x(y’z’+y’z) f=x’(y’+z)+x(y’) z y

Electrical & Computer Engineering

x f

Dr. D. J. Jackson Lecture 21-15

Shannon’s expansion example x

y

z

f

0

0

0

1

0

0

1

1

0

1

0

0

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

0

1

1

1

0

Electrical & Computer Engineering

f=x’y’z’+x’y’z+x’yz+xy’z’+xy’z choose z as the expansion variable

Dr. D. J. Jackson Lecture 21-16

8

ECE380 Digital Logic Combinatorial Circuit Building Blocks: Decoders, Demultiplexers, Encoders and Code Converters Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 22-1

Decoders • Decoder circuits: decode encoded information • A binary decoder has n data inputs and 2n outputs • Only one output is asserted at any time (one-hot encoded) and each output corresponds to one valuation of the inputs • An enable input (En) is used to disable the outputs – If En=0, none of the decoder outputs is asserted – If En=1, one of the outputs is asserted according to the valuation of the inputs n inputs Enable Electrical & Computer Engineering

w0 wn-1 En

y0

2n outputs

y2n-1 Dr. D. J. Jackson Lecture 22-2

1

2-to-4 decoder circuit y0 y1 y2 y3

w0 w1 En

Enable

w 0 w 1

y 0 y 1

En w1 w0 y0 y1 y2 y3 1

0

0

1

0

0

0

1

0

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

0

0

1

0

X

X

0

0

0

0

y 2 y 3

En

Truth table Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 22-3

3-to-8 decoder w0 w1 w2

En

w0 w1 En

w0 w1 En

Electrical & Computer Engineering

y0 y1 y2 y3

y0 y1 y2 y3

y0 y1 y2 y3

y4 y5 y6 y7

Dr. D. J. Jackson Lecture 22-4

2

74138 3-to-8 decoder

Note the ‘active low’ outputs Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 22-5

Decoder application

a0 a1

. . .

am-1

m-to-2m decoder

• A common decoder application is the decoding of address lines for memory chips Sel0 Sel1

. . . . Sel2m-1

0/1 0/1

…..

0/1

0/1 0/1

…..

0/1

. . . 0/1 0/1

…..

0/1

Dr. D. J. Jackson Lecture 22-6

3

Demultiplexers • A multiplexer multiplexed n data inputs to a single output • A circuit that performs the opposite, placing the value of a single input onto one for multiple outputs is called a demultiplexer • An n-to-2n decoder implements a 1-to-n demultiplexer Act as the select inputs Acts as the data input Electrical & Computer Engineering

w0 w1 Enable

En

y0 y1 y2 y3

Dr. D. J. Jackson Lecture 22-7

Encoders • An encoder performs the opposite function of a decoder • A binary encoder encodes information (data) from 2n inputs into an n-bit code (output) – Exactly one of the inputs should have a value of one – The outputs represent the binary number that identifies which input is equal to 1

• Encoders reduce the number of bits needed to represent given information • Practical use: transmitting information in a digital system

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 22-8

4

Encoders w0

2n inputs

w2n-1

y0 yn-1

n outputs

A 2n-to-n binary encoder w 3 w 2 w 1 w 0 y1 y0 0

0

0

1

0

0

0

0

1

0

0

1

0

1

0

0

1

0

1

0

0

0

1

1

w 0 w 1 w 2 w 3

Electrical & Computer Engineering

y 0 y 1 Dr. D. J. Jackson Lecture 22-9

Priority encoders • Another useful class of encoders is based on the priority of the input signals • In a priority encoder, each input has a priority level associated with it • The encoder outputs indicate the active input that has the highest priority – When an input with a high priority is asserted, the other lower priority inputs are ignored

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 22-10

5

Priority encoders • Assume that w0 has the lowest priority and w3 has the highest • The output z indicates when none of the inputs are 1 • Letting – – – –

i0=w3’w2’w1’w0 i1=w3’w2’w1 i2=w3’w2 i3=w3

y0 =i1+i3, y1=i2+i3 z = i1+i2 +i3+i4 Electrical & Computer Engineering

w 3 w 2 w 1 w 0 y1 y0 z 0

0

0

0

D

D

0

0

0

0

1

0

0

1

0

0

1

X 0

1

1

0

1

X

X 1

0

1

1

X

X

X 1

1

1

4-to-2 priority encoder truth table

Dr. D. J. Jackson Lecture 22-11

Code converters • The purpose of code converter circuits is to convert from one type of input encoding to another type of output encoding • For example: – A 3-to-8 decoder converts from a binary number to a one-hot encoding at the output – A 8-to-3 encoder performs the opposite

• Many different types of code converter circuits can be constructed – One common example a a BCD-to7-segment decoder Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 22-12

6

BCD-to-7-segment decoder • Converts one binary-coded decimal (BCD) digit into information suitable for driving a digit-oriented display – A vending machine display is an example

• The circuit converts a BCD digit into 7 signals that are used to drive (activate) the segments in the display – Each segment is a small light-emitting diode (LED), which glows when driven by an electrical signal

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 22-13

BCD-to-7-segment decoder a b c d e f g

w w0 w1 w2 3

a f e

b g

c

d Electrical & Computer Engineering

w3 w2 w1 w0 a b c d e f

g

0

0

0

0

1 1 1 1 1 1 0

0

0

0

1

0 1 1 0 0 0 0

0

0

1

0

1 1 0 1 1 0 1

0

0

1

1

1 1 1 1 0 0 1

0

1

0

0

0 1 1 0 0 1 1

0

1

0

1

1 0 1 1 0 1 1

0

1

1

0

1 0 1 1 1 1 1

0

1

1

1

1 1 1 0 0 0 0

1

0

0

0

1 1 1 1 1 1 1

1

0

0

1

1 1 1 1 0 1 1 Dr. D. J. Jackson Lecture 22-14

7

BCD-to-7-segment decoder a f e

g

a b

f

c

e

g

d

e

g

b

f

c

e

g

d

a f

a

f

c

e

d Electrical & Computer Engineering

b

f

c

e

g d

f

c

e

g d

b

f

c

e

d

a b

a

g

d a

b

a

f

c

e

g

c

d a

b

b

g d

a b

f

c

e

b g

c

d Dr. D. J. Jackson Lecture 22-15

8

ECE380 Digital Logic Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 23-1

Assignment statements • VHDL provides several types of statements that can be used to assign logic values to signals – Simple assignment statements • Used previously, for logic or arithmetic expressions

– – – – –

Selected signal assignments Conditional signal assignments Generate statements If-then-else statements Case statements

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 23-2

1

Selected signal assignment • A selected signal assignment allows a signal to be assigned one of several values, based on a selection criterion – Keyword WITH specifies that s is used for the selection criterion – Two WHEN clauses state that f=w0 when s=0 and f=w1 otherwise – The keyword OTHERS must be used ARCHITECTURE Behavior OF mux2to1 IS BEGIN WITH s SELECT f