ELCT201: Digital Logic Design Lecture 5 Dr. Eng. Rania.Swief e-mail: [email protected]

Dr. Eng. Haitham Omran e-mail: [email protected]

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Outlines • • • •

Decoders Encoders Multiplexers Tri-state Buffers

Dr. Eng. Ahmed H. Madian

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Decoders • Need to activate only one product: – 1: activated (product released) – 0: not activated • Only one slot can be activated at a time. It could be modeled as follows

Input

Machine

pad

Dr. Eng. Ahmed H. Madian

Output select line

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Decoders • It is required to design a combinational circuit with 2 inputs (a, b) and 4 outputs (do,d1,d2,d3). • • • •

d0 =1 when a=0 and b=0 d1 = 1 when a=0 and b=1 d2 = 1 when a=1 and b=0 d3 = 1 when a=1 and b=1

Dr. Eng. Ahmed H. Madian

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2–to-4 decoder 1. From the specifications of the circuit, determine the required number of inputs and outputs and assign a letter (symbol) to each.

a b

decoder

Dr. Eng. Ahmed H. Madian

d0 d1 d2 d3

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2-to-4 Decoder 2. Derive the Truth Table that defines the required relationship between inputs and outputs. 3-Get the simplified logic function of the outputs using k-map d0 = a’b’ d1 = a’b d2 = ab’ d3 = ab 4- Draw the logic circuit 6/23 Dr. Eng. Ahmed H. Madian

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• Design a 3 inputs 8 output decoder

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3-to-8 Decoder

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3-to-8 Decoder (cont.) • Three inputs, X, Y, Z, are decoded into eight outputs, D0 through D7 • Di = 1 when the binary number XYZ = i • Shorthand: Di = mi • The output variables are mutually exclusive; exactly one output has the value 1 at any time, and the other seven are 0.

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Implementing functions using decoders • Any combinational circuit can be constructed using decoders and OR gates! Why? • Here is an example: Implement a full adder circuit with a decoder and two OR gates. • Recall full adder equations, and let X, Y, and Z be inputs: – S(X,Y,Z) = m(1,2,4,7) – C (X,Y,Z) = m(3, 5, 6, 7).

the

• Since there are 3 inputs, we need a 3-to-8 decoder.

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0 1 2 3 4 5 6 7

X 0 0 0 0 1 1 1 1

Y 0 0 1 1 0 0 1 1

Z 0 1 0 1 0 1 0 1

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C 0 0 0 1 0 1 1 1

S 0 1 1 0 1 0 0 1 11

S(X,Y,Z) = Σm(1,2,4,7) C(X,Y,Z) = Σm(3,5,6,7) x’y’z’ x’y’z x’yz’ x’yz xy’z’ xy’z xyz’

xyz

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2-to-4 Decoder With Enable signal

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Decoder Expansions  Larger decoders can be constructed using a number of smaller ones. HIERARCHICAL design!  Example: design a 3-to-8 decoder using 2-to-4 decoders.

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3-to-8 decoder using two 2-to-4 decoders

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Encoders • An encoder is a digital circuit that performs the inverse operation of a decoder. • An encoder has 2n input lines and n output lines. • The output lines generate the binary equivalent of the input line whose value is 1. 17/23 Dr. Eng. Ahmed H. Madian

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Encoder Example • Example: 8-to-3 binary encoder (octalto-binary)

A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7 18/23 Dr. Eng. Ahmed H. Madian

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Encoder Example (cont.)

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Simple Encoder Design Issues •

There are two Problems associated with the design of a simple encoder: 1. Only one input can be active at any given time. If two inputs are active simultaneously, the output produces an undefined combination (for example, if D3 and D6 are 1 simultaneously, the output of the encoder will be 111. A0 = D1 + D3 + D5 + D7 =1 A1 = D2 + D3 + D6 + D7 =1 A2 = D4 + D5 + D6 + D7 =1 2. An output with all 0's can be generated when all the inputs are 0's,or when D0 is equal to 1. How to solve this design issues? 20/23 Dr. Eng. Ahmed H. Madian

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Priority Encoders • It is a combinational circuit that implements the priority function. • The operation of the priority Encoder is such that, if two or more inputs are equal to “1” at the same time, the input having the highest priority will take precedence. • The input D3 in the following Truth Table has the highest priority, regardless of the values of the other inputs. • Thus, if D3 is “1” , the output will indicate that A1A0 = 11, i.e. the code A1A0 = 11 means that any data appears on line D3 will have the highest priority and pass through the system irrespective of the other inputs. • If D2 = “1” and D3 = “0” the code A1A0 = 10 and this means that D2 has the highest priority in this case.

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Inputs

Outputs

D3

D2

D1

D0

A1

A0

V

0 0 0 0 1

0 0 0 1 X

0 0 1 X X

0 1 X X X

0 0 0 1 1

0 0 1 0 1

0 1 1 1 1

D1D0 D3D2

D1D0 D3D2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

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4-to-2 Priority Encoder A 0  D3  D1 D 2 A1  D 2  D3 V  D 0  D1  D 2  D3

What about V? A valid output indicator, designated by V, is set to 1 only when one or more inputs are equal to 1.

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Making Connections • Direct point-to-point connections between gates – Wires we've seen so far • Route one of many inputs to a single output --- multiplexer • Route a single input to one of many outputs --- demultiplexer control

control

Multiplexer

Demultiplexer

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Multiplexers • Multiplexers: general concept – 2n data inputs, n control inputs (called "selects"), 1 output – Used to connect 2n points to a single point – Control signal pattern forms binary index of input connected to output Z = A' I0 + A I1

A 0 1

Z I0 I1

I0 I1

2:1 mux

Z

A

functional form

I1 0 0 0 0 1 1 1 1

I0 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

Z 0 0 1 0 0 1 1 1

logical form

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Multiplexers (cont.)

I0 I1

2:1 mux A

Z

I0 I1 I2 I3

4:1 mux

Z

A B

I0 I1 I2 I3 I4 I5 I6 I7

8:1 mux

Z

A B C

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Multiplexers (cont.)

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Multiplexers (cont.)

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Multiplexers as General-purpose Logic • 2n-1:1 mux can implement any function of n variables – With n-1 variables used as control inputs and – Data inputs tied to the last variable or its complement • Example: – F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1) A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 1 0 1 0 0 0 1 1

C'

C' C' 0 1

C'

0

0 1 4:1 MUX 2 3 S1 S0 A

1

Dr. Eng. Ahmed H. Madian

F

B

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Multiplexers as General-purpose Logic • 2n:1 multiplexer implements any function of n variables – With the variables used as control inputs and – Data inputs tied to 0 or 1 – This technique used in some programmable logic devices

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• Design an AND. Or, and Xor gates using only Muxs 0

0 1

4:1 mux

Z 1

Z

A B

A B

And

4:1 mux

Or

0 1 0

4:1 mux

Z

A B

Xor 31/46 Dr. Eng. Ahmed H. Madian

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Three-State Buffers (Tri-State Buffer)

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Three-State Buffers (Tri-State Buffer)

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Assignment 3 due date is next Sunday

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