## DIGITAL LOGIC CIRCUITS

University of Ottawa - School of Information Technology - SITE Sensing and Modelling Research Laboratory SMRLab - Prof.. Emil M. Petriu DIGITAL LOGI...
University of Ottawa - School of Information Technology - SITE

Sensing and Modelling Research Laboratory SMRLab - Prof.. Emil M. Petriu

DIGITAL LOGIC CIRCUITS Digital logic circuits

electronic circuits that handle information encoded in binary form (deal with signals that have only two values, 0 and 1)

Digital …. computers, watches, controllers, telephones, cameras, ... BINARY NUMBER SYSTEM Number ….in whatever base

Decimal value of the given number

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Decimal:

1,998

= 1x103 +9x102 +9x101 +8x100 =1,000+900+90+8 =1,998

Binary: 11111001110 = 1x210 +1x29 +1x28 +1x27 +1x26 +1x23 +1x22 +1x21 = 1,024+512+258+128+64+8+4+2 = 1,998 © Emil M. Petriu

Powers of 2

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2N

N

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0 1 2 3 4 5 6 7 8 9 10 11

1 2 4 8 16 32 64 128 256 512 1,024 2,048

“Kilo”as 210 is the closest power of 2 to 1,000 (decimal)

……………………………………………………….....

15

32,768

215 Hz often used as clock crystal frequency in digital watches

…………………………………………………….....

20

1,048,576

“Mega” as 220 is the closest power of 2 to 1,000,000 (decimal)

…………………………………………………...

30

1,073,741,824

“Giga” as 230 is the closest power of 2 to 1,000,000,000(decimal)

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Negative Powers of 2 _____________________________________________________________

N B

F2 = Σ (4,8,9,12,13,14)

A it is like that there is a “transparent” path from the D input to the Q output)

D Latch S

D

Enable D S R

Q

Q R

Enable

Q Q

0

0

1 1

Q Q

0

1

1 1

Q Q

1 0 1 1

1 0 0 1

0 1 1 0

1

Enable

0 1

D

0 1

S

0 1

R

0 1

Hold

Q

0

“Hold”state

“Transparent” state

Latch 1

D

D Enab.

CLK

EN1

D

Din*

Synchronous D Flip-Flop

Latch 2

Q Q

D1

D Enab.

Q Q

Q Q

Positive-Edge -Triggered D Flip-Flop

D CLK

Latch 1 is Transparent

D1 EN2

1 Input data D may change

0 1 0 1

Latch 1 is Holding

D1 = Din* Latch 2 is Holding

Q

Latch 1 is Transparent

Changed input data D enter Latch 1 Latch 2 is Transparent

Latch 2 is Holding

Q = D1 = Din* The state of the flip-flop’s output Q copies input D when the positive edge of the clock CLK occurs

Q

EN2

CLK EN1

Q

0 1 0 1 0 1 0

Positive-Edge-Triggered D Flip-Flop

Synchronous D Flip-Flop

Vcc CLR2 14

13

D2

CLK2 PR2 Q2 12

11

10

Q2 9

8

Connection diagram of the 7474 Dual Positive-Edge-Triggered D Flip-Flops with Preset and Clear. 1 CLR1

2 D1

3

4

CLK1 PR1

5

6

Q1

Q1

7 GND

COUNTERS 4-Bit Synchronous Counter using D Flip-Flops Q3

Q2

Q1

Q0

0

1

2

3

4

5

CL

4-Bit BINARY COUNTER

CK

15

6

14

7

CL

13

3

Q = Σ Qi 2i .

12

11

10

9

8

i=0

1

CK

0 1

CL

Q

0

0 1

2 3 4 5 6

7 8

9 10 11 12 13 14 15 0 1

2 3 4 5

DECIMAL STATE Q 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0

BINARY STATE OF THE COUNTER

FLIP FLOP INPUTS (for the next state)

Q3 Q2 Q1 Q0

D3 D2

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0

D3

Q3 Q2

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0

D1 D0

0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0

0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

D2

Q3 Q2

00 01 11 10

Q1 Q0

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0

Using D flip-flops has the distinct advantage of a straightforward definition of the flip-flop inputs: the current state of these inputs is the next state of the counter. The logic equations for all four flip-flop inputs D3, D2, D1, and D0 are derived from this truth table as Q3 Q2 functions of the 00 01 11 10 Q1 Q0 current states of the counter’s flip-flops: 0 4 12 8 00 Q3, Q2, Q1, and Q0. 1 5 13 9 01 Karnaugh maps can 11 3 7 15 11 be used to simplify these equations. 2 6 14 10 10

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

D1

Q3 Q2

00 01 11 10

Q1 Q0

Synchronous 4-bit Counter

00 01 11 10

Q1 Q0

D0

Q3 Q2

00 01 11 10

Q1 Q0

00

0

0

1

1

00

0

1

1

0

00

0

0

0

0

00

1

1

1

1

01

0

0

1

1

01

0

1

1

0

01

1

1

1

1

01

0

0

0

0

11

0

1

0

1

11

1

0

0

1

11

0

0

0

0

11

0

0

0

0

10

0

0

1

1

10

0

1

1

0

10

1

1

1

1

10

1

1

1

1

Synchronous 4-bit Counter

D3

Q3 Q2

00 01 11 10

Q1 Q0

D2

Q3 Q2

00 01 11 10

Q1 Q0

00

0

0

1

1

00

0

1

1

0

01

0

0

1

1

01

0

1

1

0

11

0

1

0

1

11

1

0

0

1

10

0

0

1

1

10

0

1

1

0

D3 = Q3. Q2 + Q3. Q1 + Q3.Q0 + Q3.Q2.Q1.Q0

D1

Q3 Q2

D2 = Q2. Q0 + Q2. Q1 + Q2. Q1. Q0

Q1 Q0

00 01 11 10

Q1 Q0 0

0

D0

Q3 Q2

00 01 11 10 00

0

0

01

1

1

1

1

11

0

0

0

0

10

1

1

1

1

D1 = Q1. Q0 + Q1. Q0 00

1

1

1

1

01

0

0

0

0

11

0

0

0

0

10

1

1

1

1

D0 = Q0

Synchronous 4-bit Counter

CL

CK Q0 D

Q

CLK R

Q

Q0

D0 = Q0

Q1 D

D1 = Q1. Q0 + Q1. Q0

Q

CLK D2 =

Q2. Q0

+

Q2.

Q1 +

Q2. Q1. Q0

R

Q

Q1

D3 = Q3. Q2 + Q3. Q1 + Q3.Q0

Q2 + Q3.Q2.Q1.Q0

D

Q

CLK R

Q

Q2

Q3 D

Q

CLK R