SEQUENTIAL LOGIC

Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Sequential Logic FF’s

φ

LOGIC

Out

tp,comb

In

2 storage mechanisms • positive feedback • charge-based Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Positive Feedback: Bi-Stability Vo1 =Vi2 Vi1

Vo1

Vi2 = Vo1

Vo2

Vi2 = Vo1

Vi1

Vo2

A C B Vi1 = Vo2

Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Vi2 = Vo1

Vi2 = Vo1

Meta-Stability B

C

δ

δ

Vi1 = V o2

Vi1 = Vo2

Gain should be larger than 1 in the transition region Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

SR-Flip Flop S

Q

R

Q

S

Q

S

Q

R

Q

S

Digital Integrated Circuits

R

Q

Q

0 1 0 1

0 0 1 1

Q 1 0 0

Q 0 1 0

S

R

Q

Q

1 0 1 0

1 1 0 0

Q 1 0 1

Q 0 1 1

Q

R R

S

Q

Q

Sequential Logic

© Prentice Hall 1995

JK- Flip Flop J

S

Q

R

(a)

Q

Kn

Qn+1

0 0 1 1

0 1

Qn 0 1 Qn

Q

φ K

Jn

Q

0 1 (c)

J φ

Q

K

Q (b)

Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Other Flip-Flops T

J

φ

φ K

Q

D

J φ

Q

φ

Q

Q

K

T

Q

D

Q

φ

Q

φ

Q

Delay Flip-Flop

Toggle Flip-Flop

Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Race Problem tloop t φ

1

D

Q

φ

Q

t

Signal can race around during φ= 1

Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Master-Slave Flip-Flop SLAVE

MASTER

J

S

Q

K

R

Q

SI

RI

S

Q

Q

R

Q

Q

φ

PRESET

J φ K

Q Q

CLEAR

Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Propagation Delay Based Edge-Triggered φ

In

N1 X

In φ

N2 X

tpLH

Out Out

= Mono-Stable Multi-Vibrator Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Edge Triggered Flip-Flop J S

Q

Q

R

Q

Q

φ

K

J

Q

>φ K Digital Integrated Circuits

Q

Sequential Logic

© Prentice Hall 1995

Flip-Flop: Timing Definitions φ

t

tsetup

thold

In DATA STABLE

Out

t

tpFF

DATA STABLE

Digital Integrated Circuits

Sequential Logic

t

© Prentice Hall 1995

Maximum Clock Frequency

FF’s

φ

LOGIC tp,comb

Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

CMOS Clocked SR- FlipFlop VDD

M2

M4 Q

Q

Digital Integrated Circuits

φ

M6

S

M5

M1

M8

φ

M7

R

M3

Sequential Logic

© Prentice Hall 1995

Flip-Flop: Transistor Sizing

(1.8/1.2)

4.0

(3.6/1.2)

VQ

(7.2/1.2)

2.0

0.0 0.0

Digital Integrated Circuits

1.0

2.0

3.0

Sequential Logic

4.0

5.0

© Prentice Hall 1995

6 Transistor CMOS SR-Flip Flop VDD

M2

φ

Q S

Q R

M5 M1

Digital Integrated Circuits

φ

M4

M3

Sequential Logic

© Prentice Hall 1995

Charge-Based Storage φ

D

In

φ

D φ

(b) Non-overlapping clocks

φ

(a) Schematic diagram

Pseudo-static Latch Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Master-Slave Flip-Flop φ

φ

D

A

In

B φ

φ

φ φ

Overlapping Clocks Can Cause •Race Conditions •Undefined Signals Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

2 phase non-overlapping clocks φ1

φ2

D

In

φ2

φ1

φ1 φ2 tφ12 Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

2-phase dynamic flip-flop φ1

φ2

In

D

Input Sampled φ1 φ2 Output Enable Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Flip-flop insensitive to clock overlap VDD

VDD

M2 φ

M6

M4

X

In φ

M3

CL1

φ

M8 D

φ

M1

M7

CL2

M5

φ− section

φ− section

C2 MOS LATCH Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

2 C MOS

avoids Race Conditions

VDD

VDD

M2

M6 0

X

In 1

M3 M1

D 1

VDD

M2

M6

M4 X

In

0

M8 D

M7 M1

M5

(a) (1-1) overlap

Digital Integrated Circuits

VDD

M5

(b) (0-0) overlap

Sequential Logic

© Prentice Hall 1995

φ

Digital Integrated Circuits

φ Non-pipelined version

b

REG φ

φ

φ

Sequential Logic

.

φ

log

REG

Out

REG

log

REG

.

REG

b

REG

φ

a REG

a

REG

Pipelining

Out

φ

Pipelined version

© Prentice Hall 1995

Pipelined Logic using VDD

In

VDD

VDD

φ

φ

φ

F

φ

2 C MOS

C1

Out

G φ

C2

φ

C3

NORA CMOS What are the constraints on F and G? Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Example VDD

1

VDD

VDD

φ

φ

φ

φ

Number of a static inversions should be even

Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

NORA CMOS Modules VDD φ In1 In2 In3

VDD

VDD

φ PDN

φ

φ

PUN

Out

φ (a) φ-module

φ Combinational logic VDD

φ

VDD

Latch VDD

VDD

In4 φ

In 1 In 2 In 3

PDN φ

Digital Integrated Circuits

Out

φ (b) φ-module

In4 Sequential Logic

© Prentice Hall 1995

Doubled

2 C MOS

VDD

VDD

VDD

Latches VDD

Out In

In φ

Doubled n-C2MOS latch

Digital Integrated Circuits

φ

φ

φ

Out

Doubled n-C2 MOS latch

Sequential Logic

© Prentice Hall 1995

TSPC - True Single Phase Clock Logic VDD

VDD

VDD

VDD

PUN In φ

φ

Static Logic

φ

φ

Out

PDN

Including logic into

Inserting logic between latches

the latch

Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Master-Slave Flip-flops VDD

VDD

φ D

φ

D φ

D

φ

VDD

φ

D

φ

(a) Positive edge-triggered D flip-flop

D

VDD

φ

φ

φ

VDD

V DD

φ

Y

X

VDD

VDD

(b) Negative edge-triggered D flip-flop

VDD

D

(c) Positive edge-triggered D flip-flop using split-output latches Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Schmitt Trigger In

Out

•VTC with hysteresis

V OH

Vout

V OL

•Restores signal slopes VM–

Digital Integrated Circuits

Sequential Logic

VM+

Vin

© Prentice Hall 1995

Noise Suppression using Schmitt Trigger Vin

Vout

VM+

VM–

t0

Digital Integrated Circuits

t0 + tp

t

Sequential Logic

t

© Prentice Hall 1995

CMOS Schmitt Trigger V DD

M2

M4 X

Vin

M1

Vout

M3

Moves switching threshold of first inverter Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Schmitt Trigger Simulated VTC 5.0

6.0

4.0 4.0 Vout (V)

VX (V)

3.0 2.0

V M+

2.0 V M-

1.0 0.0 0.0

1.0

Digital Integrated Circuits

2.0 3.0 Vin (V)

4.0

5.0

0.0 0.0

Sequential Logic

1.0

2.0

3.0 V in (V)

4.0

5.0

© Prentice Hall 1995

CMOS Schmitt Trigger (2) VDD M4 M6 M3 In

Out M2 X

M5

VDD

M1

Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Multivibrator Circuits R S Bistable Multivibrator flip-flop, Schmitt Trigger

T Monostable Multivibrator one-shot

Astable Multivibrator oscillator Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Transition-Triggered Monostable

In

DELAY Out

td

Digital Integrated Circuits

td

Sequential Logic

© Prentice Hall 1995

Monostable Trigger (RC-based) VDD R

In

A

B

Out (a) Trigger circuit.

C

In

B

VM

Out

t t1

Digital Integrated Circuits

(b) Waveforms.

t2 Sequential Logic

© Prentice Hall 1995

Astable Multivibrators (Oscillators) 0

1

2

N-1

Ring Oscillator

V1

V3

V5

V (Volt)

5.0

3.0

1.0

-1.0

0

1

2

3

4

5

t (nsec)

simulated response of 5-stage oscillator

Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995

Voltage Controller Oscillator (VCO) V DD

VDD

M6

M4

Schmitt Trigger restores signal slopes

M2

In M1

Iref Vcontr

Iref M3

M5

Current starved inverter

t pH L (nsec)

6 4 2

0.0 0.5

Digital Integrated Circuits

1.5

V contr (V)

2.5

propagation delay as a function of control voltage

Sequential Logic

© Prentice Hall 1995

Relaxation Oscillator Out 1

Out 2 I2

I1

C

R Int

T = 2 (log3) RC Digital Integrated Circuits

Sequential Logic

© Prentice Hall 1995