## Chapter 3 Logic Gates

Chapter 3 3.1 Logic Gates Logic Circuits Combinational logic circuits use logic gates to perform logic functions. They are the building blocks of d...
Author: Esther Shelton
Chapter 3 3.1

Logic Gates

Logic Circuits

Combinational logic circuits use logic gates to perform logic functions. They are the building blocks of digital systems. By combining them in different ways any desired output for a given input can be achieved. The seven basic logic gates are NOT, AND, OR, NAND, NOR, X-OR and X-NOR. Each exhibits a different behaviour when input is applied and this is illustrated in the sections which follow. For each gate a symbol, behavioural description and an example, including truth table is given. Note also that the algebraic representation of each gate is given for each such example circuit. This will be discussed in detail in the next chapter, but is included for completeness and ease of reference. The NOT gate has only one input and one output and is the simplest gate. The remaining gates can all have one or many inputs, but all have only one output. Notice that two symbols are shown for the NOT gate. In some cases the gate described can be implemented using a combination of other gates. Where this is appropriate such equivalent combinational circuits are drawn in pale green boxes. Note that in this case only 2-input circuits are shown, though it is trivial to redraw any such circuit with more inputs. Before the logic gates are described it should be noted that there are two generally accepted methods of drawing logic gate symbols; the distinctive shape method and the rectangular shape with qualifying symbol method. Both are shown for each gate, though the preferred method used throughout this text is the distinctive shape method. Also note that each method has it’s own symbol for negation, i.e. inversion. Both are commonly used in digital circuits and should be understood. To illustrate this the symbols for a NOT gate are shown below. Distinctive Shape

Rectangular Shape w/Qualifying Symbol

1 Negation Symbol

1 Negation Symbol

When drawing large circuits or conceptual circuits the negation symbol for the rectangular shape method is commonly encountered. In algebraic terms a negation is signified by an overbar, i.e. X = A , in this case X is the inverse of A.

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3.2

The NOT gate

BEHAVIOUR : The Output is the inverse of the Input SYMBOLS : EXAMPLE :

A

Truth Table Input Output A X 0 1 1 0

X

ALGEBRAICALLY : X = A

3.3

The AND gate

BEHAVIOUR : The Output is 1 only if all the Inputs are 1 SYMBOL : EXAMPLE :

A B C

X

ALGEBRAICALLY : X = A B C

3.4

Truth Table Inputs Output ABC X 000 0 001 0 010 0 011 0 100 0 101 0 110 0 111 1

The OR gate

BEHAVIOUR : The Output is 1 if any or all of the Inputs are 1 SYMBOL : EXAMPLE :

A B C ALGEBRAICALLY : X = A + B + C

X

Truth Table Inputs Output ABC X 000 0 001 1 010 1 011 1 100 1 101 1 110 1 111 1 34

3.5

The NAND gate

BEHAVIOUR : The Output is 1 if any or all the Inputs are 0 SYMBOL : ALTERNATIVE IMPLEMENTATIONS :

EXAMPLE :

A B C

X

ALGEBRAICALLY : X = ABC

3.6

Truth Table Inputs Output ABC X 000 1 001 1 010 1 011 1 100 1 101 1 110 1 111 0

The NOR gate

BEHAVIOUR : The Output is 1 only if all of the Inputs are 0 SYMBOL : ALTERNATIVE IMPLEMENTATION :

EXAMPLE :

A B C ALGEBRAICALLY : X = A + B + C

X

Truth Table Inputs Output ABC X 000 1 001 0 010 0 011 0 100 0 101 0 110 0 111 0

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3.7

The X-OR (exclusive-OR) gate

BEHAVIOUR : The Output is 1 only if an odd number of the Inputs are 1 SYMBOL : ALTERNATIVE IMPLEMENTATION :

EXAMPLE :

A B C

X

ALGEBRAICALLY : X = A ⊕ B ⊕ C

3.8

Truth Table Inputs Output ABC X 000 0 001 1 010 1 011 0 100 1 101 0 110 0 111 1

The X-NOR (exclusive-NOR) gate

BEHAVIOUR : The Output is 1 only if an odd number of Inputs are 0 SYMBOL : ALTERNATIVE IMPLEMENTATION :

EXAMPLE :

A B C ALGEBRAICALLY : X = A ⊕ B ⊕ C

X

Truth Table Inputs Output ABC X 000 1 001 0 010 0 011 1 100 0 101 1 110 1 111 0

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3.9

The Universal Property of NAND gates and NOR gates

A combination of NAND or NOR gates can be used to represent other logic gates. This is a useful feature as ICs generally contain several gates. It means that costs can be minimised by implementing other gates required using redundant NAND or NOR gates. The gates that can be easily implemented are shown below; the NOT, AND, OR, NOR (in the case of NAND gates) and NAND (in the case of NOR gates). X-OR and X-NOR gates can also be implemented but the number of gates required is high, hence the usefulness of such an implementation is limited. Universal Property of NAND gates

Universal Property of NOR gates

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3.10 Combinational Circuits, Truth Tables and Timing Diagrams As was stated earlier, logic gates are combined into combinational logic circuits to perform certain logic functions. The circuit’s behaviour can be analysed by generating a truth table containing state information for each node in the circuit. The key to this method is the identification and labelling of the node(s), the input(s) and the output(s). The circuit’s behaviour can also be represented by a timing diagram, i.e. the waveforms at different points in the circuit can be plotted. An example circuit is shown below along with the resultant truth table and timing diagram. The circuit to be analysed is shown below. Intermediate nodes (d to l) have been identified and labelled accordingly. In order to make the analysis clearer different colours have been used. The three inputs have been labelled A, B and C and the output is labelled X.

d

g

e f

Output h X i j l k A

B C

Inputs

The resultant truth table of the above circuit is shown below. The output X depends on the states of the four intermediate nodes g, h, i and l. Hence these four nodes are highlighted in the truth table for easy examination.

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A 0 0 0 0 1 1 1 1

Input B C 0 0 1 1 0 0 1 1

d

e

Truth Table Intermediate Nodes f g h i j

1 1 1 1 0 0 0 0

1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0

0 1 0 1 0 1 0 1

1 0 0 0 0 0 0 0

0 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1

1 1 1 1 0 0 0 0

k

l

Ouptut X

1 0 1 0 1 0 1 0

0 0 0 0 0 1 0 1

1 0 0 1 0 1 1 1

The Timing Diagram for the circuit is shown below. A reference clock pulse has also been drawn. Note that the waveforms presented are ideal since we wish to convey the logical operation of the circuit, not the actual operation of a real circuit.

Clock

1 0

A B C d e f g h i j k l X

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