3

ASIC INDUSTRY TRENDS

ASSPs AND ASICs The term ASIC (Application Specific IC) has been a misnomer from the very beginning. ASICs, as now known in the IC industry, are really customer specific ICs. In other words, the gate array or standard cell device is specifically made for one customer. ASIC, if taken literally, would mean the device was created for one particular type of system (e.g., a disk-drive), even if this device is sold to numerous customers and/or is put in the IC manufacturer’s catalog. Currently, a device type that is sold to more than one user, even if it is produced using ASIC technology, is considered a standard IC or ASSP (Application Specific Standard Product). Thus, we are left with the following nomenclature guidelines (Figure 3-1).

ASIC: A device produced for only one customer. PLDs are included as ASICs because the customer “programs” that device for its needs only.

CSIC: What ASICs should have been called from the beginning. Some companies differentiate an ASIC from a CSIC by who completes or is responsible for the majority of the IC design effort. If it is the IC producer, the part is labeled a CSIC, if it is the end-user, the device is called an ASIC. This term is not currently used very often in the IC industry.

ASSP: A relatively new term for ICs targeting specific types of systems. In many cases the IC will be manufactured using ASIC technology (e.g., gate or linear array or standard cell techniques) but will ultimately be sold as a standard device type to numerous users (i.e., put into a product catolog). If the end-user helped the IC producer design the ASSP, that user is typically given a market leadtime (i.e., window of opportunity) to use the device before it is made available to its competitors. CSP: Customizable Standard Products are 70 to 90 percent standard with 10 to 30 percent of the chip available for user-specified logic, memory, or peripheral functions. Source: ICE, "Status 1996"

19181A

Figure 3-1. ASIC Industry Terminology

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ASIC Industry Trends

One problem many IC producers have run into while producing ASSPs is that in order to provide the optimum part, the IC producer must understand the system application at least as well as the end-user. Because this system-level expertise is not easy to acquire, most ASSP vendors have formed close relationships or partnerships with end-users. In this way, the IC vendor and enduser work closely together early in the system design cycle in order to properly define the ASSP device. In general, as standard ICs take aim at ever finer segments of the marketplace, they ultimately evolve into ASSPs. In other words, at some point in time there could be very few standard ICs; most devices produced would be aimed at specific system needs. An example would be certain DRAMs architecturally optimized for a hand-held telecom system, laptop PC, or HDTV set. This is precisely the direction the IC industry is now heading. Figure 3-2 shows some of the devices that National Semiconductor considers ASSPs. As IC producers customize their devices for specific system needs, the list of ICs labeled as ASSPs continues to expand. In 1995, Sharp Corporation plans to release an ASSP product based upon the 33MHz ARM RISC 32-bit MPU core. The ARM ASSP will include a 480x320 monochrome LCD controller, 115-kbaud serial data infrared transceiver, write-back cache controller, on-board SRAM optimized for real-time interrupt, and pulse-width modulators. As was mentioned earlier, 20 years from now there may be few “standard” ICs produced.

• Mainframe connectivity solutions • FDDI devices • Local area network (LAN) ICs • Telecommunications products (e.g., CODECs) • Graphics ICs • Mass storage devices • Real-time clocks • DRAM management ICs • Floppy-disk devices • UARTs Source: ICE, "Status 1996"

17776

Figure 3-2. Sampling of ASSPs from National Semiconductor

Although the 1995 ASIC market is estimated to have been $15.7 billion, the ASSP-type products (which are part of the special purpose MOS Logic category) are taking away some of its momentum (Figure 3-3). Overall, the ASIC market (not including full custom) is forecast to follow total IC industry growth rates fairly closely.

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ASIC Industry Trends

8

7.63

7 5.98

Billions of Dollars

6

5

4

4.74

3.75

28%

26%

26%

3

2

1

0 1992

1993

1994

1995 (EST)

Year Source: ICE, "Status 1996"

20204A

Figure 3-3. Special Purpose MOS Logic Market (1992-1995)

Does the proliferation of ASSPs and more customer-specific standard products mean an end to the ASIC market? No. This is because most of the pros and cons of ASICs versus ASSPs or standard products still exist. The primary advantage of ASSPs or standard products is the ability to immediately (most of the time) purchase the ICs and get the system to market quickly. However, ASIC devices allow the system producer to differentiate its product from the competition. The result is that many times the system producer is able to gain marketshare and/or better profit margins. In some cases standard products and ASICs are merging in an attempt to offer the benefits of both approaches. In 1993, TI announced that it was merging an enhanced version of its standard fixedpoint TMS320C25 DSP chip and 15,000 usable and customizable 0.8-micron CMOS gate-array gates on one device. Thus, the user is able to take advantage of well characterized high-performance DSP circuitry while at the same time adding unique features to give its system a differential advantage over its competitors. TI estimated that 30 percent of its total DSP IC sales in 1995 would be in customizable version form.* This percentage was expected to rise to 50 percent in 2000. * Through 1995 TI’s belief in the success of its customizable DSP was well founded. TI’s big jump in gate array sales in 1994 and 1995 was greatly due to the success of its gate array DSP program.

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Another grey area is where Cirrus Logic takes one of its ASSP ICs and customizes a portion of it for one of its customers. Typically only about 5-10 percent of the new design is customized for the end-user. This “tweaked” device is still normally classified as an ASSP since the majority of the circuitry is still ASSP-based. There is no question that the IC industry will continue to evolve toward devices that are specifically suited for the customers’ needs. ICE believes that various versions of ASICs and ASSPs will co-exist to help serve those needs in the most economical and efficient manner possible. ASIC Definitions Some basic definitions and classifications are shown below in order to define what ICE means when using the various terms used to describe today’s ASIC devices. ASIC stands for Application Specific Integrated Circuit and according to ICE’s definition includes gate arrays, standard cells (sometimes called cell-based), full custom, and programmable logic devices (PLDs). These devices are classified as either semicustom, custom, or PLDs. Formal definitions are given in Figure 3-4.

I. Semicustom IC - A monolithic circuit that has one or more customized mask layers, but does not have all mask layers customized, and is sold to only one customer.

Gate Array - A monolithic IC usually composed of columns and rows of transistors (organized in blocks of gates). One or more layers of metal interconnect are used to customize the chip. Sometimes called an uncommitted logic array (ULA). Linear Array - An array of transistors and resistors that performs the functions of several linear ICs and discrete devices. II. Custom IC - A monolithic circuit that is customized on all mask layers and is sold to only one customer.

Standard Cell IC - A monolithic IC that is customized on all mask levels using a cell library that embodies pre-characterized circuit structures. ICs that are designed with a silicon compiler are included in this category. Most "embedded" arrays are included in this category. Full Custom IC - A monolithic IC that is at least partially "handcrafted". Handcrafting refers to custom layout and connection work that is accomplished without the aid of a silicon compiler or standard cells. Source: ICE, "Status 1996"

13660E

Figure 3-4. ASIC Definitions

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III. Programmable Logic Device (PLD) - A monolithic circuit with fuse, antifuse, or memory cell-based circuitry that may be programmed (customized), and in some cases, reprogrammed by the user (insystem or prototype form).

Simple PLD (SPLD) - Usually a PAL or PLA, typically contains less than 750 logic gates. Complex PLD (CPLD) - A hierarchical arrangement of multiple PAL-like blocks. Field Programmable Gate Array (FPGA) - A PLD that offers fully flexible interconnects, fully flexible logic arrays, and requires functional placement and routing. Electrically Programmable Analog Circuit (EPAC) - A PLD that allows the user to program and reprogram basic analog functions. Source: ICE, "Status 1996"

13660E

Figure 3-4. ASIC Definitions (continued)

ICE does not include ASSPs in its ASIC market figures. An example of an ASSP part that is not classified as an ASIC by ICE is Hitachi’s H8/300H Series of microcontrollers. Although the H8/300H user is able to customize this MCU using an extensive Hitachi cell library, the finished devices are almost always allowed to be sold to other Hitachi customers after a certain period of time (Motorola has a similar program using its 68HC05 MCUs). In mid-1994, Motorola announced its FlexCore program that allows the end-user to use Motorola’s 32-bit MPUs as cores in cell-based designs. This program is significantly different from its, and Hitachi’s, MCU ASSP offerings in that the finished devices will most likely stay proprietary to the original customer. Thus, these devices are considered to be standard cell ASICs. The FlexCore-type ASIC program* is a prime example why ASSPs will not eliminate the market for ASICs. As was mentioned earlier, ASSPs will still hold an advantage in time-to-market, but they will never be able to compete with the product differentiation capability of robust ASIC offerings such as FlexCore. Another ASIC segment that needs additional clarification and discussion is the PLD category. ICE includes under the generic term PLD the simple bipolar fuse-programmable PAL devices (e.g., the 22V10) produced by AMD, TI, and National, the complex programmable (CPLD) devices (that typically have configurable macrocells, multiple feedback paths, etc.) that are usually MOS memory cell-based, and what are called field programmable gate arrays (FPGAs). Figure 3-5 compares the architectures of a typical CPLD and a typical FPGA. * Zilog has a similar program for its Z80 MCU devices.

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ASIC Industry Trends

SPLD Block

SPLD Block Global Bus

SPLD Block

SPLD Block

CPLD

Interconnect

Logic Block

I/O Cell

FPGA Source: CICC 1995/ICE, "Status 1996"

20205

Figure 3-5. CPLD Versus FPGA Structures

The FPGAs are produced using MOS memory cell (and thus are usually reprogrammable) or antifuse technology. The physical (e.g., line lengths) and electrical characteristics of the interconnects are unknown before programming, just like a gate array. As was shown, the PLD classification now encompasses a broad range of products and most people in the IC industry are aware that the term PLD is no longer synonymous with the nearly obsolete bipolar fuse-programmable PAL. Another definitional clarification that should be mentioned is in the standard cell category. Many of the standard cell designs produced in the ASIC industry use a combination of pre-characterized and “handcrafted” circuit structures. ICE categorizes an ASIC that has 50 percent or more of its circuitry composed of cells as a standard cell IC. If less than 50 percent of the circuitry is from precharacterized cells (with the majority of the design being handcrafted), the IC is considered a full custom ASIC. 3-6

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Another device that deserves some further discussion is the embedded array ASIC. When designing with this device, the customer first identifies any megacell functions that will be needed. The ASIC producer optimizes the layout of the cell-based design and then begins producing base wafers. While the base wafers are being fabricated, the customer is finishing design work for the uncommitted random logic area (gate array portion) that was set aside in the initial design. After the base wafer is finished being processed, the gate array area of the base wafer is metallized. The ultimate goal of the parallel random logic design and cell-based wafer fabrication efforts of the embedded array program is to shorten the turnaround time encountered with standard cell devices. Many embedded array producers are achieving turnaround times very close to those of gate arrays. Although both standard cell and gate array design and fabrication techniques are used on the embedded array, because all of the mask layers of the device are customized for the user, ICE will classify the embedded array ASICs (e.g., VLSI Technology’s Flex-Arrays) as standard cells. Throughout “Status 1996” ICE uses terms such as available, total, raw, and usable when referring to gate densities. Figure 3-6 shows the definitions followed by ICE in regard to gate count. Typical usable gate counts for various ASICs are shown in Figure 3-7.

AVAILABLE, TOTAL OR RAW GATES The number of unconnected gates on a device. USABLE GATES The number of gates that can typically be interconnected implementing an "average" design. Usable gate count will always be less than the number of available, total, or raw gates. Source: ICE, "Status 1996"

16779

Figure 3-6. Gate Count Definitions

ASIC Type

Usable Gate Percentage

Double-Level Metal MOS PLD

30 - 50

Triple-Level Metal MOS PLD

60 - 70

Double-Level Metal Channelled Gate Array

85 - 95

Double-Level Metal Channelless Gate Array

40 - 50

Triple-Level Metal Channelless Gate Array

60 - 70

Five-Layer Metal Channelless Gate Array

75 - 85

Standard Cell

85 - 95

Full Custom Source: ICE, "Status 1996"

100 16780B

Figure 3-7. Sampling of Usable Gate Counts

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As total gate densities have increased, the IC manufacturer has had to go to a greater number of interconnect levels (i.e., metal layers) to keep die size and usable gate counts manageable. This has been especially evident with the new triple-level metal PLDs. As will be discussed, the new PLD technologies are helping reduce PLD die size dramatically, and in turn, significantly reduce manufacturing costs. Of course the move to a greater number of metal layers comes with cost and complexity problems. With an increasing number of ASIC designs being pad limited (i.e., the die size is dictated by the number of I/O pads rather than the logic gate area) the move to more layers of metal has proceeded very slowly in the ASIC user base. ASIC Product Lifecycle Figure 3-8 shows the 1995 location of each of the major ASIC families on the product lifecycle curve. It is interesting to note that most of the classifications still reside on the growth side of the curve. As the ASIC market matures, the majority of the ASIC product types will be in or approaching the maturity stage of their lifecycles in the late 1990’s. Low density (i.e., less than 10,000 gates) gate arrays are considered to be in the saturation/decline stage. In 1995, many gate array vendors were shying away from accepting designs for low gate count arrays. As veteran IC buyers know, once products enter the latter stages of the lifecycle, price becomes a secondary concern to availability. Likewise, slow bipolar TTL PALs are quickly losing marketshare and are now in the decline stage. As shown, replacement products for the slow bipolar TTL PAL and low density gate array, such as MOS PLDs, are currently in the introduction or growth/maturity stage. THE LOGIC MARKET An analysis of the logic market provides a good background to the study of the ASIC market since a vast majority of ASIC products perform some basic logic function within a system. Approximately 20 percent of 1994 and 1995 worldwide IC output was for some form of logic device. Figure 3-9 shows the logic trends by technology. The most obvious trend shown on the graph is the tremendous growth of CMOS logic. In eight years (1987-1995), CMOS technology grew from 55 percent of the logic market to 85 percent. On the other hand, older technologies such as NMOS and bipolar are quickly being phased out. ECL technology, after maintaining about eight percent of the logic marketshare for several years, declined to around three percent in 1995 and is forecast to drop to a smaller marketshare percentage through the year 2000. Many of the better performance characteristics of ECL and other older technologies have been replicated in CMOS and BiCMOS technologies in recent years. These two technologies will dominate not only the logic market (98 percent in the year 2000), but all digital IC production in the foreseeable future.

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Sales

ASIC Industry Trends

Introduction

Growth

Maturity

Saturation

Decline and Obsolescence

4.5ns TTL PLD 5ns TTL PLD EPLD

EPAC Flash-PLD

10ns TTL PLD

EEPLD SRAM-PLD

Antifuse PLD CMOS Gate Array (≥500,000 Gates)

ECL PLD 7ns TTL PLD >10ns TTL PLD

CMOS Gate Array (≥100,000 and 10,000 7%

5,000 to 10,000 10%

$1.7B

1,500 to 3,000 33%

>3,000 to 5,000 40%

Source: ICE, "Status 1996"

20408

Figure 3-54. 1995 MOS PLD Revenue by Gate Count

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ASIC Industry Trends

It is interesting to note that in most cases the CMOS gate array suppler is not fighting the PLDs’ attack on the low-end market. Most CMOS gate array suppliers are concentrating on the highdensity, high-performance, and high unit volume segment of the gate array market. With business booming since 1992, gate array vendors have become very “selective” of the contracts they take for gate array devices. Oftentimes turning down business in the process! What this now means as far as the trend lines shown in Figure 3-53 is that the low-end CMOS gate array price per gate may stay flat in the future. With little competitive pressure, the low-end CMOS gate array price per gate could even increase in the late 1990’s. While an annual 30 percent or greater decline in the PLD price per gate may be difficult to sustain into the late 1990’s, there is little doubt that PLDs will become more competitive in price compared to low-end gate arrays. This is one reason that ICE is bullish about the future of the PLD/FPGA business. There is no doubt that, when comparing specific unit costs of gate arrays (even including NREs) and PLDs, gate array devices look favorable at all but the lowest volume levels. Why then has there been a surge in the PLD market over the past few years? The answer is the increasing importance of the “time to market” factor. For example, in today’s high-end disk-drive market, lifecycles of six months to a year are fairly common. PLD Technology Trends Over the last few years the PLD market has been the most dynamic of all IC markets with regard to new product introductions. Shown below is a sampling of some of the major PLD technology announcements made in 1995. • Xilinx began taking production orders for its 0.6µm three-layer metal antifuse-based PLDs (XC8100) in June of 1995. The antifuse devices contain from 1,000 to 9,000 usable gates with all routing resources located above the underlying sea-of-gates logic. • Xilinx introduced its flash-based (5V-only) PLDs in late 1995. The 0.6µm devices allow 10,000 program/erase cycles and in-system programming. The devices are offered in usable gate densities of 800 to 12K. • In 4Q95 Xilinx introduced its XC4000E series of SRAM-based FPGAs that offer 2.5K to 25K usable gates as well as on-chip dual-port SRAM capability. The devices are produced using 0.5µm three-layer metal CMOS technology. One-hundred piece quantities of the XC4020E (20,000 usable gates) cost $300 in 4Q95 and were expected to sell for $125 in volume in 2H96.

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• Xilinx is working on an optimized in-system reconfigurable SRAM-based PLD family (XC6200) that reconfigures in microseconds. The release date for these devices has not been given. • Beginning in 2Q95, Xilinx began phasing-in its 0.5µm technology (from 0.6µm) for its XC5000 SRAM-based FPGA family. The 0.6µm XC5000 family is shown in Figure 3-55.

Usable Gates

XC5202

XC5204

XC5206

XC5210

XC5215

2,200 - 2,700

3,900 - 4,800

6,000 - 7,500

Max I/O

84

124

148

196

244

Flip-Flops

256

480

784

1296

1936

Pricing* (10K Quantity)

$9

$15

$25

$38

$68

10,000 - 12,000 14,000 - 18,000

* 2Q95 prices for the XC5202, XC5204, XC5206 and XC5210 devices are in PC84 packages; the XC5215 device is in PQ208. Source: ICE, "Status 1996"

20177A

Figure 3-55. Xilinx’s XC5000 Family

Xilinx’s long-term PLD density roadmap is shown Figure 3-56.

Feature Size (µm) Die Size (mm) Number of Gates Metal Layers Wafer Size (mm)

1985/6

1994

1995

1996/7

Plan 2001

"Perhaps" 2001

2.0

0.6

0.5

0.35

0.20

0.15

7.5 x 7.5

17 x 17

17 x 17

17 x 17

25 x 25

38 x 38

800

25,000

50,000

100,000

500,000

1.25M

2

3

3

3-4

4-5

5-6

100

150

150

200

200

300

Source: Xilinx/ICE, "Status 1996"

20346A

Figure 3-56. Xilinx’s PLD Technology Roadmap

• In 1Q95 Xilinx purchased NeoCAD Inc., a developer of high performance design software for FPGAs. • In 1Q95 AMD announced that it signed a five-year deal with software developer Minc, Inc. (Boulder, CO.). The deal calls for Minc to develop and sell all of AMD’s PLD design software for its MACH CPLDs and PALs.

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ASIC Industry Trends

• In 1Q95 Altera described its FLEX 10K family of devices that are architecturally optimized for implementing memory on the PLD. The FLEX 10K is also designed to support on-chip ROM, multipliers, ALUs, and DSP functions. Figure 3-57 shows how the FLEX 10K is at the leading-edge of Altera’s broad line of PLD products.

FLEX 10K FLEX 8000 MAX 9000 I/O MAX 7000 FLASHlogic Classic and MAX 5000

Usable Gates Classic

MAX 5000

FLASHlogic

MAX 7000

MAX 9000

Usable Gates

150 - 900

600 - 3,750

800 - 3,200

Performance (MHz)

50 - 125

50 - 100

50 - 100

70 - 150

50 - 100

75

75

Pin count

24 - 68

24 - 100

44 - 208

44 - 208

84 - 304

84 - 304

84 - 560

Technology

EPROM

EPROM

FLASH

EEPROM

EEPROM

SRAM

SRAM

600 - 5,000 6,000 - 12,000

Source: Altera/ICE, "Status 1996"

FLEX 8000

FLEX 10K

2,500 - 50,000 10,000 - 100,000

20182

Figure 3-57. Altera’s PLD Product Line

• In 4Q95 Altera announced sampling of its EPF10K50 (50K gates) SRAM-based PLD. The device offers up to 20K bits of RAM or ROM. One-hundred unit pricing was $850 in 4Q95 with 1997 pricing projected to be $150 in 5,000-unit quantities. • In 3Q95 Altera introduced its MegaFunctions Partners Program (AMPP). The program is an alliance between Altera and intellectual property providers that will develop synthesizable functional blocks (e.g., display controllers, 8-bit 6502 processors, etc.) for insertion into Altera’s FLEX 10K family of SRAM-based PLDs. As of 3Q95 Altera was working with over 20 suppliers in the AMPP project. • In 3Q95 aftermarket IC supplier Rochester Electronics agreed to carry Altera’s discontinued high-density PLD devices.

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• In 1Q95 Altera began shipping its gate array-to-PLD design conversion tools. The tools support LSI Logic and Fujitsu gate arrays. Additional gate array vendors are to be announced. • Actel introduced its 3200DX family in 3Q95. The 6,500-gate 3265DX was available in 3Q95 with the 20,000-gate A32200DX available in January of 1996. Initially offered in 0.6µm technology , the family will move to 0.5µm processing in early 1996. Members of the 3200DX family of PLDs will be able to incorporate blocks of high-speed (5ns) dual-port SRAM (Figure 3-58).

JTAG

Logic Modules

SRAM 32 x 8 or 64 x 4

SRAM 32 x 8 or 64 x 4

SRAM 32 x 8 or 64 x 4

SRAM 32 x 8 or 64 x 4

SRAM 32 x 8 or 64 x 4

Logic Modules

SRAM 32 x 8 or 64 x 4

JTAG

Logic Modules JTAG

SRAM 32 x 8 or 64 x 4

SRAM 32 x 8 or 64 x 4

SRAM 32 x 8 or 64 x 4

SRAM 32 x 8 or 64 x 4

SRAM 32 x 8 or 64 x 4

SRAM 32 x 8 or 64 x 4

Fast Decode Module

JTAG

Source: Actel/ICE, "Status 1996"

20409

Figure 3-58. Actel’s 3200DX FPGA Architecture

• AMD introduced its 0.5µm MACH 5 PLDs in 3Q95. The devices offer 7.5ns performance, PCI compliance, and JTAG capability. The family is expected to move to 0.35µm processing in 1996.

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ASIC Industry Trends

1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9

Geometry Gates 60,000 gates

0.8µm

0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1

100,000+ 95,000 90,000 85,000 80,000 75,000 70,000 65,000 60,000 55,000 50,000 45,000 40,000 35,000 30,000 25,000 20,000 15,000 10,000 5,000 0

40,000 gates 0.6µm 26,000 gates 0.5µm 4,000 gates 1992

0.35µm

7,000 gates 1993

1994

1995

1996

Usable Gates/Chip

Minimum Geometry (µm)

• AT&T introduced its 0.35µm ORCA™ Family of SRAM-based FPGAs in 4Q95. A 15K-gate device is due out in 1Q96 with densities of up to 60K-gates to follow (Figure 3-59).

1997

Year Source: AT&T Microelectronics/ICE, "Status 1996"

20431

Figure 3-59. AT&T FPGA Density and Feature Size Trends

• In 4Q95 Lattice introduced a 3.5ns 3.3V 20-pin 16LV8 EEPROM-based PLD using 0.5µm technology. A 3.5ns 22V10 device is expected by 2Q96. • In 4Q95 Hitachi began selling FPGAs based on Crosspoint Solutions’ antifuse-based technology in Japan. Hitachi will also co-develop libraries to convert Crosspoint FPGAs to Hitachi gate arrays. • A new entrant emerged in the FPGA market in 2Q95—Gate Field, a division of EDA software supplier Zycad. The FPGAs are produced by Rohm using a 0.6µm flash-based process. Its 9K total gates (2.2K usable) devices were expected to be priced at $30/25K at the end of 1995. A 100K total gate device was due late in 1995. • Production quantities of IMP’s electrically programmable analog circuit (EPAC) began shipping in 1Q95. The EPACs are produced using a mixed-signal 1.2µm CMOS process with onchip EEPROM. The EPACs cost $25 (100) and are available in a mask-programmed version (MPAC).

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As discussed above, with a movement to high density PLD devices, the PLD producers are being asked to offer functions other than pure logic on-chip. Many PLD suppliers have begun offering PLDs with on-chip SRAM or ROM (e.g., Altera, Xilinx, etc.). Altera and Motorola are even contemplating adding MCU embedded functions to their PLD devices! The in-system reprogrammable PLD topic is one that has only recently surfaced (1994). Some of the early players in this area include: - AT&T (SRAM-based) - Altera (SRAM-based, MCM and monolithic) - AMD (EEPROM-based) - Atmel (SRAM-based) - Lattice (EEPROM-based) - Xilinx (SRAM-based and flash-based) As an example of a reconfigurable application, Altera states that its reprogrammable PLD can be configured as a display accelerator or circuit simulator as needed. Altera says, “. . . that by using reprogrammable logic the potential exists to configure the hardware for more direct processing of the data.” Chris DeMonico of AT&T states that there are three major reasons for logic reconfigurability. “First, to meet standards, which are evolving and therefore are in a constant state of flux; second, to keep up with system functionality changes; and third, to accommodate multiple data formats in a single device.” There is little doubt that reconfigurability will be a powerful tool to enhance a system’s efficiency. Some possible early system applications for reprogrammable logic include telecommunications, geophysical information processing, medical imaging, and computer architecture simulation. In the telecommunications area one can easily envision the need for a PLD device to dynamically reconfigure itself to accommodate multiple interface or telecommunications protocols and standards (Figure 3-60). Atmel describes its reconfigurable logic as “cache logic.” Since much of a system’s hardware logic is idle at a given time, the ability to reconfigure the logic on-the-fly to optimally serve the software’s immediate computational requirements can greatly accelerate the performance of the system. It should be noted that reconfigurable PLD logic is still in its infancy. 1995 design tools and programs were still not sufficient to manage dynamically reconfigurable hardware efficiently. However, as system designers continue to explore ways to increase system performance, ICE expects that reconfigurable PLDs will find an increasing market to serve.

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ASIC Industry Trends

(a) Telecom T1/T1E DSP Algorithm Engine

Synchronizer

2.048 Mbits/s (Europe) 1.544 Mbits/s (U.S.)

Line Interface Card

Extract timing from T1/T1E source

(b) Sonet/Synchronous Networks DSP Algorithm Engine

Synchronizer

DS3: 45 Mbits/s STS1E: 52 Mbits/s

Line Interface Card

Extract timing from T1/T1E source or bits

(c) Algorithm Engine

Fixed Algorithm Engine

Dual-Port RAM

DSP Core

Microcontroller

(d) ATM ATM Switch Fabric

Line Interface Card

Overhead channels Framing

(e) Graphics-Accelerator Card Hard Disk

Compression/Decompression FPGA

Video Engine

Source: AT&T Microelectronics/ICE, "Status 1996"

20180

Figure 3-60. FPGA Can Reconfigure to Meet Various Standards

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