Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Digital Integrated Circuits
NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high A
B
X
Y
Y = X if A and B
A
X
B
Y
Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1 Digital Integrated Circuits
High noise margins: VOH and VOL are at VDD and GND, respectively. No static power consumption: There never exists a direct path between VDD and VSS (GND) in steady-state mode. Comparable rise and fall times: (under the appropriate scaling conditions)
Properties of Complementary CMOS Gates High noise margins: VOH and VOL are at VDD and GND, respectively. No static power consumption: There never exists a direct path between VDD and VSS (GND) in steady-state mode. Comparable rise and fall times: (under the appropriate scaling conditions)
2. Determine “Worst Case Input” transition (Delay depends on input values) 3. Example: tpLH for 2input NAND - Worst case when only ONE PMOS Pulls up the output node - For 2 PMOS devices in parallel, the resistance is lower t pLH = 0.69Rp CL
2-input NAND
4. Example: tpHL for 2input NAND - Worst case : TWO NMOS in series t pHL = 0.69(2R n)CL
Domino Logic - Characteristics •Only non-inverting logic •Very fast - Only 1->0 transitions at input of inverter move VM upwards by increasing PMOS • Adding level restorer reduces leakage and charge redistribution problems • Optimize inverter for fan-out
