Combinational Circuits I

Paper: CII- Computer System Architecture Lesson: Combinational Circuits I Name: Sarabjeet Kaur College/ Department: Department of Computer Science, Indraprastha College for Women Author and Reviewer Details (Reviewer to add the details when this document reaches him/her)

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Combinational Circuits I

Learning Outcomes

By the end of this Chapter a student should be able to acquire:

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Familiarity with the following concepts: 1. Combinational Circuits 2. Sequential Circuits 3. Analysis of a Combinational Circuit 4. Design of a Combinational Circuit

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Design, Functionality and Applications of the following Combinational Circuits:

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Half Adder, Full Adder

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Half Subtractor, full Subtractor

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Combinational Circuits I

Table of Contents ●

Chapter 1: Combinational Circuits

1.1: Types of Circuits

1.2: The Process for Designing a Combinational Circuit

1.3: Analysis of a Combinational Circuit

1.4: Adders (Half Adder, Full Adder)

1.5 Summary

1.6 Exercises

1.7 Glossary

1.8 References

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Combinational Circuits I

1.1 Types of Circuits The digital electronic circuits can be classified as Combinational circuits and Sequential circuits. A Combinational circuit is an interconnection of logic gates, the elementary building blocks of digital circuits. The outputs of a combinational circuit at any time are a function of only the present inputs to the logic gates.

Figure 1.1.1: Combinational Circuit Source: Digital Design, M. Morris Mano, 3rd edition A Sequential circuit, like combinational circuit, is also an interconnection of logic gates but it also employs a set of memory elements. In contrast to the combinational circuits, the outputs of a sequential circuit are dependent on not only the present inputs, but may also be affected by the past inputs. The memory elements, such as flip flops, are responsible for storing the past state of the circuits. As shown in Figure 1.1.2, the memory elements form a feedback path to the circuit and thereby control its next state.

Figure 1.1.2: Sequential Circuit; Source: Self

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Combinational Circuits I

Multiplexers, Demultiplexers, Adders, Subtractors, Decoders, Encoders and Code Convertors are some combinational circuits that find wide deployment.

S.No. 1. 2.

3.

Combinational Circuit It contains no memory elements The present value of it’s outputs are determined solely by the present values of it’s inputs It’s behavior is described by the set of output functions

Sequential Circuit It contains memory elements The present value of it’s outputs are determined by the present value of it’s inputs and it’s past state It’s behavior is described by the set of next-state(memory) functions and the set of output functions

Table 1.1.1: Differences between Combinational and Sequential Circuits Source: Self

1.2. The Process for Designing a Combinational Circuit Given a requirement for the combinational circuit, the process of designing a combinational circuit involves deducing the circuit diagram or Boolean expressions required to implement it. Following steps are generally involved in this process:

1. Drawing a Block Diagram The first step for designing a combinational circuit involves clear specification of the objective of the circuit, so that its function and requirement is clearly understood. This understanding facilitates the deduction of the number and type of inputs and outputs of the circuit. Each input and output is then associated with a unique symbol. A block diagram summarizes this step of the design process and serves as a fundamental block to promote understandability of a combinational circuit in a glance.

2. Derivation of Truth Tables The second step of the design process concerns actually studying how the outputs can be obtained from the inputs. For this, generally a tabular representation is drawn up that lists all valid combinations of the input values to the circuit under design and their corresponding output values. The input n

values correspond to the 2 binary numbers derivable from the n input variables. This tabular representation is referred to as a Truth Table.

3. Derivation of Boolean Expressions Institute of Lifelong Learning, University of Delhi

Combinational Circuits I The next step of the design process involves extracting a Boolean expression for each of the output variables from the truth table. This is generally done with the help of techniques such as Boolean algebra, Karnaugh Map or Quine McCluskey’s method.

4. Circuit Diagram and it’s Verification The design process of a combinational circuit culminates in a circuit diagram. Each Boolean expression obtained in the previous step is laid down with the help of electronic gates. It is also important to verify the obtained circuit diagram. This may be done manually by hand or through a simulation program. It is important to note that there are generally some other objectives also that must be kept in mind while designing a combinational circuit. Admissible propagation delays, number or type of gates, area, power, testability, security and reliability are some such constraints. This text looks at a couple of examples for designing the combinational circuits in Section 1.4.

1.3. Analysis of a Combinational Circuit The objective of analyzing a combinational circuit is either to deduce its function or verify its working. The analysis process starts with a logic circuit diagram culminates in production/ verification of the corresponding Boolean expressions and/or truth table. The goal of analyzing a combinational circuit can thus be seen as just the opposite of the design process. Following steps are generally involved in the analysis process:

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Step 1: Label the input of logic gates by meaningful, unique symbols. Clearly,

at the onset, only the external inputs can be labelled.

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Step 2: Deduce the outputs of each logic gate for which the inputs were

labelled in Step 1. Assign a meaningful, unique label to the outputs. These labels may serve as an input to other gates.

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Step 3: Repeat step 2 till the external (final) output of the combinational

circuit is obtained. The external output denotes the Boolean expression corresponding to the logic circuit being analyzed.

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Step 4: The Truth tables can then be drawn corresponding to the Boolean

expression obtained in Step 3. If the goal of circuit analysis is only verification, then a manual corroboration of the truth table outputs is desirable. Boolean algebra may sometimes be used to derive alternate/ optimized boolean expressions from the expressions obtained in step 3. A simulator

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Combinational Circuits I program is also sometimes written to analyze the combinational circuits, define its test conditions and compare circuit output with functional description i.e. objective.

1.4 Adders Binary Addition is a commonly required computation in computer systems. The Combinational Circuit used to add two or more binary numbers is called an Adder. A Half Adder is used to perform addition of two bits while a Full Adder is used to perform addition of three bits. The subsections 1.4.1 and 1.4.2 discuss the design of a Half adder and a Full Adder respectively. 1.4.1 Half Adder Given the two bits to be added as inputs, namely the Augend and the Addend, the objective of a Half Adder is to generate their Sum and Carry. The term Augend is derived from Latin word 'augendum', which means 'to be increased'. It denotes a number in the addition operation, to which another number is to be added. The term Addend denotes a number that is to be added to the Augend. Figure 1.4.1.1 sums up this information in the form of a block diagram.

Figure 1.4.1.1: Block Diagram of a Half Adder; Source: Self

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Combinational Circuits I The addition of two Binary digits (bits) is carried out as illustrated in the Figure 1.4.2.1. The Carry in the first three cases is zero. However, in the fourth case, when both augend and addend are 1, the result of their addition is ‘10’, wherein the 0 is retained as the Sum and 1 is the Carry Out.

Figure 1.4.1.2: Addition of Two Bits; Source: Self

The Truth Table of a Half Adder can be drawn, corresponding to the combinations of the two input variables Augend and Addend (say X and Y respectively) and their corresponding outputs Sum and Carry (say S and C respectively), as illustrated in Figure 1.4.2.1.

Augend X

Addend Y

Sum S

Carry C

0

0

0

0

0

1

1

0

1

0

1

0

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Combinational Circuits I 1

1

0

1

Table 1.4.1.1: Truth Table of Half Adder; Source: Self

The Boolean Expressions for Sum and Carry for a half adder, being simple, are derivable directly from the truth table as follows: S= x’y + xy’ i.e. x ⊗y C = xy

The Circuit Diagram for the Half Adder can thus be drawn as in Figure 1.4.3.1

Figure 1.4.3.1: Circuit Diagram for a Half Adder; Source: Self

1.4.2 Full Adder We saw in the Section 1.4.1 that a half adder is capable of adding two bits of information. However, when we add two binary numbers, a carry from the previous significant bit is also required to be added along with the augend and addend. This necessitates the design of a circuit that can add three bits of information at a given instant of time. Such a circuit is called a Full Adder.

Thus the objective of a full adder is to generate the Sum (and Carry) of three bits, namely the Augend, Addend and the previous carry (i.e. carry from the lower significant bit). Figure 1.4.2.1 gives the block diagram of a Full Adder.

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Combinational Circuits I

Figure 1.4.2.1: Block Diagram of a Full Adder; Source: Self

The Truth Table of a Full Adder can be drawn, corresponding to the combinations of the three input variables Augend, Addend and Previous Carry ( X, Y and Z respectively) and their corresponding outputs Sum and Carry (S and C respectively), as illustrated by Table 1.4.2.1.

Augend X

Addend Y

Previous Carry Z

Sum S

Carry C

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

Table 1.4.2.1: Truth Table of Full Adder; Source: Self

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Combinational Circuits I It can be observed from the truth table that Sum =0 and Carry =1 when two of the three inputs are one (as in the half adder). Both the Sum and Carry are 1 when all the three inputs are 1 resulting in a decimal sum 3 ( = binary 11). The Boolean Expressions for Sum and Carry for a full adder, can be derived with the help of a Karnaugh Maps, as illustrated in Figure 1.4.2.2.

K- Map for Sum S

K- Map for Carry C

Figure 1.4.2.2: Karnaugh Maps for Sum and Carry of a Full Adder; Source: Self

From the Figure 1.4.2.2, S = x 'y 'Z + x'YZ' + xy'Z' + xyz = x’ (y’z + yz’) + X(y’z’ + yz) = x’ (y ⊗z) + X (y ⊗z) = x ⊗y ⊗z

(Recall that A ⊗ B = A’B + AB’

and A ⊗ B = A’B’ + AB)

(Assuming A = X and B = (y ⊗z))

C =xy+yz + zx

The Circuit Diagram for the Full Adder can thus be drawn as in Figure 1.4.2.3.

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Combinational Circuits I

Figure 1.4.2.3 : Circuit Diagram for a Full Adder; Source: Self

Value addition: Did You Know? Construction of a Full Adder using Half Adders A full adder can also be implemented with two half adders and one OR gate. The output from the second half adder is the exclusive-OR of z and the output of the first half adder i.e. x ⊕y,giving: S = z'(x ⊗y) + z(x⊗y)'

= z'(xy' + x'y) + z(xy' + x'y}' = z'(xy' + x 'y ) + z(xy + x'y') = xy' z' + x 'yZ' + xyz + x 'y'Z

The carry output is

c = z(x’y + xy’ ) + xy = xy'z + x'yz + xy Figure: Implementation of a Full Adder using Two Half Adders

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Combinational Circuits I Source: Digital Design, M. Morris Mano, 3rd edition

1.5 Summary ●

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This chapter introduces the reader to the popular classification of circuits as either the Combinational circuits or Sequential circuits, depending upon whether the memory elements are used in the circuit to store the outputs at a time instant, say t. The circuits that are comprised of only the electronic gates and do not use memory elements are called Combinational circuits. In contrast, the circuits that store and use the outputs of the previous state (t) to affect the outputs produced at the next state, t+1, are called sequential circuits. Designing a combinational circuit involves deducing the circuit diagram required to implement it. Analysis of a Combinational Circuit is reverse of the design process of a combinational circuit. Given a circuit diagram, the purpose is to deduce it’s boolean expression and the truth table. Boolean algebra or simulator programs are also sometimes used for analyzing the circuits. A Half Adder is a combinational circuit that is capable of adding two bits and producing two outputs viz. their Sum and Carry. A Full Adder is a combinational circuit that extends the capabilities of a half adder by allowing addition of three binary digits to produce two outputs namely, their Sum and Carry.

1.6 Exercises Objective Questions Q1. What is the output for the following circuit?

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Combinational Circuits I a. AB+C⊕ 𝑫𝑫 ’ c. AB + C⊗D Answer: c. AB + C⊗D

b. AB+C’⊕ 𝑫𝑫 d. AB + C′ ⊗D’

Q2. Which of the following gates can be used to replace all the logic gates of Q1? a. b. c. d.

AND OR NAND NOT

Answer: c.

NAND gate because it is a universal gate.

Q3. For adding two 8 bit numbers, we need: a. b. c. d.

1 2 4 8

full full full full

adder adders connected in parallel adders connected in parallel adders connected in parallel

Answer: d. 8 full adders connected in parallel. Such an adder that can contains multiple full adders to enable the addition of n bit binary numbers is called a parallel adder (for more details please look at the web links provided at the end of this lesson).

Q4. The largest decimal number a parallel adder consisting of 8 full adders can add is: a. b. c. d.

15 256 31 255

Answer: d.

8

255 because the largest number that can be added by 8 full adders is = 2 -1

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Subjective Questions

Q1. Design a Half Subtractor Solution. The Combinational Circuit used to perform Binary subtraction of two or more binary numbers is called a Subtractor. A Half Subtractor is used to perform subtraction of two bits. Given the two input bits, whose difference is to be calculated, namely, the Minuend and the Subtrahend, the objective of a Half Subtractor is to generate two outputs, namely, their Difference and Borrow. The term minuend is a Latin word implying a quantity or number from which another quantity or number is to be subtracted. The term Subtrahend denotes a number that is to be subtracted from the minuend. Figure Ex_1.1 sums up this information in the form of a block diagram.

Figure Ex_1.1: Block Diagram of a Half Subtractor; Source: Self

The subtraction of two Binary digits (bits) is illustrated in the Figure Ex_1.2. Only in case II where we need to subtract 1 from 0, do we need to borrow a 1, which makes the minuend 10. The resultant subtraction of 10 - 1 then produces the difference 1.

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Combinational Circuits I

Figure Ex_1.2: Subtraction of two Binary Digits; Source: Self The truth table of a half subtractor (Table Ex_1.1) follows from Figure Ex1.2.

Minuend X

Subtrahend Y

Difference D

Borrow B

0

0

0

0

0

1

1

1

1

0

1

0

1

1

0

1

Table Ex_1.1: Truth Table of Half Subtractor; Source: Self

The Boolean Expressions for Sum and Carry for a half subtractor, are derivable directly from the truth table as follows:

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Combinational Circuits I D= x’y’ + xy i.e. x⊕y B = x’y The Circuit Diagram for the Half subtractor can thus be drawn as in Figure Ex_1.3

Figure Ex_1.3: Circuit Diagram for a Half Subtractor; Source: Self

Q2. Design a full Subtractor Solution. A Full Subtractor is a Combinational Circuit used to perform addition of three binary digits. Given the two input bits, whose difference is to be calculated namely the Minuend and the Subtrahend, and a third input which denotes a borrow over from the previous stage, the objective of a full Subtractor is to generate two outputs namely their Difference and Borrow. Figure Ex_2.1 depicts the block diagram of a full subtractor.

Figure Ex_2.1: Block Diagram of a Full Subtractor; Source: Self

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Combinational Circuits I

3

The Truth Table of a full subtractor can be drawn, corresponding to the 2 binary combinations of the three input variables Minuend, Subtrahend and Borrow_In ( X, Y and Z respectively) and their corresponding outputs Difference and Borrow_Out (D and B respectively), as illustrated by Table Ex_2.1.

Minuend X

Subtrahend Y

Borrow_In Z

Difference D

Borrow _Out B

0

0

0

0

0

0

0

1

1

1

0

1

0

1

1

0

1

1

0

1

1

0

0

1

0

1

0

1

0

0

1

1

0

0

0

1

1

1

1

1

Table Ex_2.1: Truth Table of Full Subtractor; Source: Self

The Boolean Expressions for Difference and Borrow_Out outputs of a full adder, can be derived with the help of a Karnaugh Maps, as illustrated in Figure Ex_2.2.

K- Map for Difference D

K- Map for Borrow_Out B

Figure Ex_2.2: Karnaugh Maps for Difference and Borrow_Out of a

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Combinational Circuits I Full Adder; Source: Self

From the Figure Ex_2.2, D = x 'y 'Z + x'YZ' + xy'Z' + xyz = x’ (y’z + yz’) + X(y’z’ + yz) ⊕z) + X (y

= x’ (y

⊗z) (Since, A

⊕B = A’ B + AB’ and A

D= x ⊕y ⊕z

(Assuming A = X and B = (y

⊗ B =A’B ’ + AB ) ⊕z))

which is the same as the boolean expression for Sum output of the Full Adder. Boolean expression for Borrow output of the Full subtractor, as derived from Figure Ex_2.2 is: B =x’y+yz + zx’

The Circuit Diagram for the Full subtractor can thus be drawn as in Figure Ex_2.3

Figure Ex_2.2: Circuit Diagram for a full Subtractor; Source: Self

Q3. Deduce the Boolean Expression corresponding to the following circuit

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Combinational Circuits I diagram:

Figure Ex_3.1: Sample Circuit Diagram for deduction of boolean expression; Source: Self

Solution According to the steps laid down in Section 1.3, since the External inputs are already labelled (A, B and C), let us start by deducing the outputs of logic gates that are fed with these

external inputs, as follows: Figure Ex_3.2: Deducing the output of first level of logic gates; Source: Self

The output of the next logic gate (in this case the final output) can now be deduced in terms of the

partial outputs obtained in Figure , as follows: Figure Ex_3.2: Deducing the final Boolean Expression; Source: Self

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Glossary Block Diagram: A diagrammatic representation in which main parts of a system are represented by boxes called blocks, connected by lines to show the inputs, outputs ofm the

system and inter-relationships among the blocks. Boolean Algebra: Boolean algebra: a logical calculus of truth values or set membership named after George Boole. Circuit Diagram: A diagrammatic representation of a network that contains electronic components is known as an electronic circuit. Flip Flop: Also called a Latch, a memory element used to store one bit of information. Karnaugh Maps:

Named after Maurice Karnaugh, a karnaugh map is a diagramatic

representation that allows simplification of the boolean expressions. Truth Table: A truth table tabulates for a particular algebraic expression/ logic operation, the output values corresponding to all possible input combinations.

References Suggested Readings 1. M. Morris Mano. 2008. Digital Logic and Computer Design (8th Edition). Prentice Hall, Inc. Learning Pvt Ltd. ISBN: 9788120304 2. William Stallings. 2005. Computer Organization and Architecture: Designing for Performance (7th Edition). Prentice-Hall, Inc., Upper Saddle River, NJ, USA. 3. RAJARAMAN, V., RADHAKRISHNAN, T., AN NTRODUCTION TO DIGITAL COMPUTER DESIGN, Fifth Edition, ISBN: 978-81-203-3409-0

Web Links 1

http://williamstallings.com/ComputerOrganization/

2

https://en.wikipedia.org/wiki/Combinational_logic

3

https://www.cs.umd.edu/class/spring2003/cmsc311/Notes/Comb/adder.html Institute of Lifelong Learning, University of Delhi

Combinational Circuits I 4

http://www.allaboutcircuits.com/textbook/digital/chpt-9/combinational-logicfunctions/

5

http://users.encs.concordia.ca/~asim/COEN_6501/Lecture_Notes/L2_Notes.p df

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