Synthesis of Combinational Logic A

B

6.0 0 Gat 4 es

F=

Ax or

B

Lab 1 due tonight, Quiz 1 during Friday’s recitation 6.004 - Fall 2002

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L05 – Logic Synthesis 1

Boolean Minimization: An Algebraic Approach

Approach: repeated application of αA + α A = α

For any expression α and variable A: Hmmm… Can’t we re-write The truth table To make “mergeable” Terms more obvious?

Y = C B A + CB A + CBA + C BA Y = C B A + CB + C BA Y = C A + CB This is the basis for most software simplification approaches – e.g., Quine-McClusky reduction. 6.004 - Fall 2002

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L05 – Logic Synthesis 2

Karnaugh Maps: A Geometric Approach K-Map: a truth table arranged so that terms which differ by exactly one variable are adjacent to one another so we can see potential reductions easily. Truth Table C

A

B

Y

0

0

0

0

0

0

1

0

0

1

0

1

0

1

1

1

1

0

0

0

1

0

1

1

1

1

0

0

1

1

1

1

Here’s the layout of a 3-variable K-map filled in with the values from our truth table:

C\AB 00 0 0 1 0

01 0 1

11 1 1

10 1 0 010

It’s cyclic. The left edge is adjacent to the right edge. (It’s really just a flattened out cube).

000 110 100

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011 001 111 101 L05 – Logic Synthesis 3

On to Hyperspace 4-variable K-map for a multipurpose logic gate:  A ⋅B   A + B Y=  B  A ⊕ B

if CD = 00

\AB CD\

00 01 11 10

if CD = 01 if CD = 10 if CD = 11

00 0 0 0 1

01 0 1 1 0

11 1 1 0 0

10 0 1 1 1

Again it’s cyclic. The left edge is adjacent to the right edge, and the top is adjacent to the bottom.

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L05 – Logic Synthesis 4

Finding Subcubes We can identify clusters of “irrelevent” variables by circling adjacent subcubes of 1s. A subcube is just a lower dimensional cube.

C\AB 00 0 0 1 0

01 0 1

11 1 1

10 1 0

\AB CD\

00 01 11 10

00 0 0 0 1

01 0 1 1 0

11 1 1 0 0

10 0 1 1 1

The best strategy is generally a greedy one. - Circle the largest N-dimensional subcube (2N adjacent 1’s) - Continue circling the largest remaining subcubes (even if they overlap previous ones). - Circle smaller and smaller subcubes until no 1s are left.

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L05 – Logic Synthesis 5

Write Down Equations Write down a product term for the portion of each cluster/subcube that is invariant.

C\AB 00 0 0 1 0 \AB CD\

00 01 11 10 6.004 - Fall 2002

00 0 0 0 1

01 0 1 01 0 1 1 0

11 1 1 11 1 1 0 0

10 1 0 10 0 1 1 1

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Y = CA + CB

Y = ABC + ABD + ABD + BCD

L05 – Logic Synthesis 6

Recap: K-map Minimization 1) Copy truth table into K-Map 2) Identify subcubes, selecting the largest available subcube at each step, even if it involves some overlap with previous cubes, until all ones are covered. (Try: 4x4, 2x4 and 4x2, 1x4 and 4x1, 2x2, 2x1 and 1x2, finally 1x1)

3) Write down the minimal SOP realization Truth Table C

B

A

Y

0

0

0

0

0

0

1

1

0

1

0

0

0

1

1

1

1

0

0

0

1

0

1

0

1

1

0

1

1

1

1

1

6.004 - Fall 2002

The Thecircled circledterms termsare arecalled calledimplicants. implicants.An An implicant not completely contained in another implicant not completely contained in another implicant implicantisiscalled calledaaprime primeimplicant. implicant.

C\BA 00 0 0 1 0

01 1 0 9/19/02

11 1 1

10 0 1

Y = C A + CB

L05 – Logic Synthesis 7

A Case for Non-Minimal SOP Y = C A + CB

A(1) C(1)

1

B(1)

C\BA 00 0 0 1 0

01 1 0

A B Y(1) C Y

0

0

11 1 1

10 0 1

That’s what we call a “glitch” or “hazard”

tCD = 1 nS tPD = 2nS

NOTE: NOTE:The Thesteady steadystate statebehavior behaviorofof these thesecircuits circuitsisisidentical. identical.They They differ differinintheir theirtransient transientbehavior. behavior.

A C

Y = C A + CB + AB

Y

If you include equations for all prime implicants, the resulting implementation will be lenient (assuming lenient gates).

B 6.004 - Fall 2002

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L05 – Logic Synthesis 8

Practical SOP Implementation NAND-NAND

AB=A+B

“Pushing Bubbles” C

C A Y B

NOR-NOR

≡

Y B

xyz = x + y + z

AB=A+B C

C A Y B

≡

A Y B

x + y = xy

You might think all these extra inverters would make this structure less attractive. However, quite the opposite is true. 6.004 - Fall 2002

A

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L05 – Logic Synthesis 9

Are K-maps Really all that Useful? ¾ They are only manageable for small circuits (4-5 inputs at most)

¾ Sometimes you pick the wrong set of subcubes ¾ There are better techniques (better for computers, not us) ¾ SOP realizations aren’t all that relevant ¾ We’ve got gates to burn ¾ Low fan-in gates are better suited to current technologies that SOP (FPGAs, Standard Cells) ¾ Sometimes minimal circuits are glitchy ¾ Some important circuits aren’t amenable to minimal SOP realizations

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L05 – Logic Synthesis 10

Logic that defies SOP simplification Ci 0 0 0 0 1 1 1 1

A 0 0 1 1 0 0 1 1

B 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

Co 0 0 0 1 0 1 1 1

S

Full Adder AB Co

FA

Ci

C/AB

00

01

11

10

0

0

1

0

1

1

1

0

1

0

C/AB

00

01

11

10

0

0

0

1

0

1

0

1

1

1

CO

S S = ABC + ABC + ABC + ABC Co = ABC + ABC + ABC + ABC

Can simplify the carry out easily enough, eg... Co = BC + AB + AC But, the sum, S, doesn’t have a simple sum-of-products implementation even though it can be implemented using only two 2-input gates. 6.004 - Fall 2002

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L05 – Logic Synthesis 11

Logic Synthesis Using MUXes Truth Table A B C

If C is 1 then copy B to Y, otherwise copy A to Y

Y

2-input Multiplexer

C

B

A

Y

0

0

0

0

0

0

1

1

0

1

0

0

0

1

1

1

1

0

0

0

1

0

1

0

1

1

0

1

1

1

1

1

A 4-input Mux implemented as a tree I0 0 I1 1 S

A

B C

Y

A

B

0

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Y

S

S

1

S0 S1

C schematic

I2 0 I3 1 1

0 1 1

Gate symbol 9/19/02

L05 – Logic Synthesis 12

Systematic Implementation of Combinational Logic Consider implementation of some arbitrary Boolean function, F(A,B) ... using a MULTIPLEXER as the only circuit element:

A 0 0 0 0 1 1 1 1 6.004 - Fall 2002

Full-Adder Carry Out Logic

0 0 0 1 0 1 1 1 A,B,Cin

B Cin Cout 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 9/19/02

0 1 2 3 4 5 6 7

Cout

L05 – Logic Synthesis 13

General Table Lookup Synthesis A

B

Muxes Muxesare areUNIVERSAL! UNIVERSAL! 10 01

AB Fn(A,B) 00 01 10 11

0 1 1 0

Y

=

A

Y

S

A

MUX Logic

Fn(A,B)

00 B1 1

A = B

Y

Y= A B

Y

Y

S

A

Generalizing: In theory, we can build any 1-output combinational logic block with multiplexers.

2Ninput mux. For an N-input function we need a _____ BIG Multiplexers? How about 10-input function? 20-input?

B0 11 S

A InInfuture futuretechnologies technologies muxes muxesmight mightbe bethe the “natural “naturalgate”. gate”. B0 B1 1

Y

S

A 6.004 - Fall 2002

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L05 – Logic Synthesis 14

A Mux’s Guts Decoder A decoder generates all possible product terms for a set of inputs

A B

0

A B

1

A B

2

A B

3

I 00

Selector

Multiplexers can be partitioned into two sections.

I 01

Y

I 10

A DECODER that identifies the desired input,and a SELECTOR that enables that input onto the output.

I 11

Hmmm, by sharing the decoder part of the logic MUXs could be adapted to make lookup tables with any number of outputs

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L05 – Logic Synthesis 15

A New Combinational Device D1 D2

DECODER: k SELECT inputs, N = 2k DATA OUTPUTs.

DN

Selected Dj HIGH; all others LOW.

HIGH is a synonym for ‘1’ and LOW means the same as ‘0’

k NOW, we are well on our way to building a general purpose table-lookup device. We can build a 2-dimensional ARRAY of decoders and selectors as follows ... 6.004 - Fall 2002

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L05 – Logic Synthesis 16

Shared Decoding Logic There’s an extra level of inversion that isn’t necessary in the logic. However, it reduces the capacitive load on the module driving this one.

A B Cin

Fixed “AND plane”

Decoder

These are just “DeMorgan”ized NOR gates

0

1

2

3

4

5

6

7

S Cout

This ROM stores 16 bits in 8 words of 2 bits.

Configurable Selector

Configurable “OR plane”

We can build a general purpose “table-lookup” device called a Read-Only Memory (ROM), from which we can implement any truth table and, thus, any combinational device Made from PREWIRED connections , and CONFIGURABLE connections that can be either connected or not connected 6.004 - Fall 2002

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L05 – Logic Synthesis 17

ROM Implementation Technology

PFET with gate tied to ground = resistor pullup that makes wire “1” unless one of the NFET pulldowns is on.

A

Hardwired AND logic Programmable OR logic

B

Advantages: - Very regular design (can be entirely automated)

Cin

Problems: - Active Pull-ups (Static Power) - Long metal runs S (Large Caps) Cout - Slow 6.004 - Fall 2002

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JARGON: Inputs to a ROM are called ADDRESSES. The decoder’s outputs are called WORD LINES, and the outputs lines of the selector are called BIT LINES.

L05 – Logic Synthesis 18

Speeding up ROMS 000 001 010 011

The key to making ROMS go fast is to minimize the capacitances of those long wires running through the array. The best way to accomplish this is to build square arrays:

100 101

00

110 01 111 10

A B CIN

11

S

COUT

A B CIN

0

1

S 6.004 - Fall 2002

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0

1

COUT L05 – Logic Synthesis 19

Logic According to ROMs ROMs ignore the structure of combinational functions ... • Size, layout, and design are independent of function • Any Truth table can be “programmed” by minor reconfiguration: - Metal layer (masked ROMs) - Fuses (Field-programmable PROMs) - Charge on floating gates (EPROMs) ... etc.

ROMs ROMstend tendto to generate generate“glitchy” “glitchy” outputs. outputs.WHY? WHY?

Model: LOOK UP value of function in truth table... Inputs: “ADDRESS” of a T.T. entry ROM SIZE = # TT entries... ... for an N-input boolean function, size = __________ 2N x #outputs Why do ROM SIZES grow by factors of 4?

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L05 – Logic Synthesis 20

Example: 7-sided Die What nature can’t provide… electronics can (with the magic of LEDs!). We want to construct a readout displaying the following symbols:

An array of LEDs, labeled as follows, can be used to display the outcome of the die: T V

U W

Y

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X Z

L05 – Logic Synthesis 21

ROM-Based Design Truth Table for a 7-sided Die A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

T 0 0 0 0 1 1 1 1

U 0 0 1 1 1 1 1 1

V W X Y Z 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1

Once we’ve written out the truth table we’ve basically finished the design

Possible optimizations: - Eliminate redundant outputs - Addressing tricks T V Y

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U W

X Z

L05 – Logic Synthesis 22

A Simple ROM implementation A B C

A different set of AND gates might make this a lot simpler

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

T/Z 0 0 0 0 1 1 1 1

U/Y 0 0 1 1 1 1 1 1

V/X 0 0 0 0 0 0 1 1

W 0 1 0 1 0 1 0 1

T V Y

No output depends on this product term or WORD LINE

6.004 - Fall 2002

T/Z U/Y V/X W 9/19/02

U W

X Z

That was easy but there is clearly some waste. - unused products - over-specified terms

L05 – Logic Synthesis 23

Another General-Purpose Logic Device What if the AND terms of a ROM’s decoder were programmable in the same way that the OR terms are? Then we could use some of our logic minimization tricks to reduce the size of the ROM array. This logic is so simple we should just build it with 2 gates!

T/Z = A U/Y = A + B V/X = AB W =C

T V Y

U W

X Z

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

T/Z 0 0 0 0 1 1 1 1

U/Y 0 0 1 1 1 1 1 1

V/X 0 0 0 0 0 0 1 1

W 0 1 0 1 0 1 0 1

PLA – Programmable Logic Array 6.004 - Fall 2002

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L05 – Logic Synthesis 24

PLA 7-sided Die implementation “AND plane”

PLAs like ROMs support the synthesis of arbitrary logic functions using SOP implementations.

A B C

However, they allow for - minimal realizations - smaller (faster) arrays

The BIT lines of PLAs tend to be long and limit their speed

T/Z U/Y V/X W

C AB B A 6.004 - Fall 2002

Regular structure - automatic generation - easy design - still slower than optimized gates

T V

“OR plane”

Y

9/19/02

U W

X Z

L05 – Logic Synthesis 25

PLA Folding

another PLA optimization In practice, many bit lines can be split, and their wiring channel can be shared between two outputs. This sharing is possible when the product terms of the two outputs are “disjoint”. This “folding” has two benefits. It reduces the logic array, and it reduces A the overall size of the capacitance of the bit-lines, thus yielding a faster circuit. B Similarly, it is possible to bring inputs into both sides of the C array but then things start to T/Z look a lot like a pair of mirrored PLAs. U/Y V/X T

W

V

C AB B A 6.004 - Fall 2002

Y

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U W

X Z

L05 – Logic Synthesis 26

PALs: Programmable Array Logic User-programmable ANDs Fixed ORs Another approach to structured logic design is Programmable Array Logic (PAL). These were once popular off-theshelf devices. They basically replaced TTL gates in the ‘80s and fueled the minicomputer revolution. Today, they are practically fossils PALs have a programmable decoder (AND plane) with fixed selector logic (OR plane). These devices were useful for implementing large fan-in gates and SOP logic expressions. They could be purchased as unprogrammed chips and configured in the field using an inexpensive programmer.

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L05 – Logic Synthesis 27

Standard Cells First, a library of fixed-pitch logic cells (gates, registers, muxes, adders, I/O pads, …) are created. A data sheet for each cell describes its function, area, power, propagation delay, output rise/fall time as function of load, etc. DREG A B C

6.004 - Fall 2002

AOI.21

D

Q

Z

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L05 – Logic Synthesis 28

Standard Cell Example H routing: metal3

Similar to designing with board level components 20 years ago. CAD tools place and route cells. - minimize area - meet timing specs

V routing: metal2 in-cell: metal1 poly

In this case, the router needed so much space for running wires that cell rows were pushed apart. In many cases, wiring determines the size of the layout!

vdd pfets nfets gnd

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L05 – Logic Synthesis 29

Fast Turn-around: Gate Arrays Gate arrays use fixed arrays of transistors that are “personalized” in a final processing step that adds wires and contacts.

metal 2 vertical wiring tracks

VDD

Most popular architecture is “Sea-ofGates” where the core of the chip is a metal 1 continuous array of FETs. Routing horizontal occurs over the top of unused wiring tracks transistors. Pros: - can be prefabricated - only last few masks are customized

6.004 - Fall 2002

GND from IEEE JSSC, V25, No5, Oct 1990

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L05 – Logic Synthesis 30

Gate Array Example INV

A

Y

B

NOR

GND

3 nFETs

The last two layers of metal are used to define the function of the transistors. Side-by-side gates are isolated from one another by turning off the gate of a transistor between them. This is called “gate-isolation.”

A B Y 3 pFETs

gate isolation VDD

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L05 – Logic Synthesis 31

Summary • Sum of products • Karnaugh maps • Use minimal cover of prime implicants to get minimal SOP • Use all prime implicants to get lenient (glitch-free) implementation • Primitive, manual version of logic optimization algorithms • SOP implementation methods • NAND-NAND, NOR-NOR

• Muxes used to build table-lookup implementations • ROMs • Decoder logic generates all possible product terms • Selector logic determines which p’terms are or’ed together • PLAs are ROMs with optimized decoders that generate only the product terms that are needed

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L05 – Logic Synthesis 32