SUBJECT NAME : DIGITAL LOGIC CIRCUITS SUBJECT CODE : EC2261 UNIT –I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS

PART-A

(1 MARK)

1.How many outputs are on a BCD decoder? A)4

B)16

C)8

D)10

2. Which digital system translates coded characters into a more useful form? A) encoder

B) display

C) counter

D) decoder

3.The expansion inputs to a comparator are used for expansion to a(n): A) 4-bit system

B) 8-bit system

C) BCD system

D) counter system

4. What control signals may be necessary to operate a 1-line-to-16 line decoder? A)flasher circuit control signal B) a LOW on all gate enable inputs C) input from a hexadecimal counter D) a HIGH on all gate enable circuits 5. 40How many exclusive-NOR gates would be required for an 8-bit comparator circuit? A)4

B)6

C)8

D)10

6. How many flip-flops are required to make a MOD-32 binary counter? A)3

B)45

C)5

D)6

7.The terminal count of a modulus-11 binary counter is ________. A) 1010

B) 1000

C) 1001

D) 1100

8. A decoder converts ________. A) noncoded information into coded form

B) coded information into noncoded form

C) HIGHs to LOWs

D) LOWs to HIGHs

9. The output of a NOT gate is HIGH when ________. A) the input is LOW

B) the input is HIGH

C) the input changes from LOW to HIGH

D) voltage is removed from the gate

10.The output of an OR gate is LOW when ________. A) all inputs are LOW

B) any input is LOW

C) any input is HIGH

D) all inputs are HIGH

11. Any number with an exponent of zero is equal to: A) zero

B) one

C) that number

D) ten

12. In the decimal numbering system, what is the MSD? A) The middle digit of a stream of numbers B) The digit to the right of the decimal point C) The last digit on the right D) The digit with the most weight 13.Which of the following statements does NOT describe an advantage of digital technology? A) The values may vary over a continuous range B) The circuits are less affected by noise C) The operation can be programmed D) Information storage is easy 14. What is a digital-to-analog converter? A) It takes the digital information from an audio CD and converts it to a usable form. B) It allows the use of cheaper analog techniques, which are always simpler C) It stores digital data on a hard drive. D) It converts direct current to alternating current. 15. What are the symbols used to represent digits in the binary number system? A) 0,1

B) 0,1,2

C) 0 through 8

D) 1,2

16.A full subtracter circuit requires ________. A) two inputs and two outputs

B) two inputs and three outputs

C) three inputs and one output

D) three inputs and two outputs

17. The output of an AND gate is LOW ________. A) all the time

B) when any input is LOW

C) when any input is HIGH

D) when all inputs are HIGH

18. Give the decimal value of binary 10010 A) 610

B) 910

C) 1810

D) 2010

19. A demultiplexer has ________. A) one data input and a number of selection inputs, and they have several outputs

B) one input and one output C) several inputs and several outputs D) several inputs and one output 20. In positive logic, ________. A) a HIGH = 1, a LOW = 0

B) a LOW = 1, a HIGH = 0

C) only HIGHs are present

D) only LOWs are present

ANSWER 1

2

3

4

5

6

7

8

9

10

D

D

B

B

C

C

A

B

A

A

11

12

13

14

15

16

17

18

19

20

B

D

A

A

A

D

B

C

A

A

PART-B

(2 MARKS)

21. Substract (0101)2 From (1011)2(A.U.APRIL/MAY 2010) 1011 -0101=0110 22. Convert 0.1289062 decimal number to its hex decimal equivlent. ( A.U.APRIL/MAY 2008) 0.1289062 * 16 =2.0625 0.0625*16=1.0 =(0.21)16 23. Define binary logic? (A.U.APRIL/MAY 2010) Binary logic consists of binary variables and logical operations. The variables are designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1 and 0. There are three basic logic operations: AND, OR, and NOT. 24. What are the basic digital logic gates? The three basic logic gates are AND gate, OR gate and NOT gate 25. What is a Logic gate? .( A.U.APRIL/MAY 2008) Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function.

26. Which gates are called as the universal gates? What are its advantages? (A.U.APRIL/MAY 2012) The NAND and NOR gates are called as the universal gates. These gates are used to perform any type of logic application. 27. Define combinational logic(AU.APRIL/MAY 2012) When logic gates are connected together to produce a specified output for certain specified combinations of input variables, with no storage involved, the resulting circuit is called combinational logic. 28. Explain the design procedure for combinational circuits. (A.U.NOV/DEC 2006) The problem definition Determine the number of available input variables & required O/P variables. Assigning letter symbols to I/O variables Obtain simplified Boolean expression for each O/P. Obtain the logic diagram. 29. Define Half adder and full adder. ( A.U.APRIL/MAY 2009) The logic circuit that performs the addition of two bits is a half adder. The circuit that performs the addition of three bits is a full adder. 30. Define Decoder? (A.U.NOV/DEC 2011) A decoder is a multiple - input multiple output logic circuit that converts coded inputs into coded outputs where the input and output codes are different. 31. What is binary decoder? ( A.U.APRIL/MAY 2009) A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n out puts lines. 32. Define Encoder? (A.U.NOV/DEC 2011) An encoder has 2n input lines and n output lines. In encoder the output lines generate the binary code corresponding to the input value. 33. What is priority Encoder? (A.U.NOV/DEC 2006) A priority encoder is an encoder circuit that includes the priority function. In priority encoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence.

34. Define multiplexer? (A.U.NOV/DEC 2011) Multiplexer is a digital switch. If allows digital information from several sources to be routed onto a single output line. 35. What do you mean by comparator. (A.U.APRIL/MAY 2010) A comparator is a special combinational circuit designed primarily to compare the relative magnitude of two binary numbers. PART- C

(16 MARKS)

36. Implement the 4-bit magnitude comparator and explain its operation. (A.U.NOV/DEC 2011) 37. What is the advantage of using tabulation method? Determine the prime implicants of the following using tabulation method. f(A,B, C, D,E) =∑(2, 3,6,7,11,12,13,14,15,23,28,29,30,31) (A.U May/Jun 11) 38.Implement the switching function F=∑(0,1,3,4,12,14,15) Using an 8 input multiplexer. (A.U NOV/DEC 2010) (A.U.APRIL/MAY 2012) 39. Design a circuit that converts 8421 BCD code to Excess -3 code.(A.U NOV/DEC 2010) 40. Implement the given Boolean function using multiplexer. F(A,B,C)= ∑(1,3,5,6). (A.U NOV/DEC 2010) 41. State and prove De-morgan’s theorem. (A.U NOV/DEC 2008) (A.U.NOV/DEC 2011) 42.Perform the following using 12 bit 2’s complement arithmetic. (1) 8-7 (2) -8-7 (3) -8+7 (4) A.U NOV/DEC 2008) 43. Minimise the following using quine –Mc Clusky method. ∑m(0,1,2,8,9,15,17,212,24,25,27,31).(A.U NOV/DEC 2008)

UNIT-II

SYNCHRONOUS SEQUENTIAL CIRCUITS

PART-A

(1 MARK)

44. How many flip-flops are required to produce a divide-by-128 device? A)1

B)4

C)6

D)7

45. Which of the following is correct for a D latch? A) The output toggles if one of the inputs is held HIGH B) Q output follows the input D when the enable is HIGH C) Only one of the inputs can be HIGH at a time. D) The output complement follows the input when enabled 46.A J-K flip-flop is in a "no change" condition when ________. A) J = 1, K = 1

B) J = 1, K = 0

C) J = 0, K = 1

D) J = 0, K = 0

47.On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________. A) the clock pulse is LOW B) the clock pulse is HIGH C) the clock pulse transitions from LOW to HIGH D) the clock pulse transitions from HIGH to LOW 48. In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns? A)2

B)6

C)12

D)24

49. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit? A) ring shift

B) clock

C) Johnson

D) binary

50. How many clock pulses will be required to completely load serially a 5-bit shift register? A)2

B)3

C)4

D)5

51. What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time? A) parallel-in, parallel-out

B) parallel-in, serial-out

C) serial-in, parallel-out

D) serial-in, serial-outOption C

52. A flip-flop has ________. A) one stable state

B) no stable states

C) two stable states

D) none of the above

53. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses? A) 0000

B) 0010

C) 1000

D) 1111

54. To operate correctly, starting a ring shift counter requires: A) clearing all the flip-flops

B) presetting one flip-flop and clearing all others

C) clearing one flip-flop and presetting all others D) presetting all the flip-flops

55. In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns? A)2

B)6

C)12

D)24

56.A modulus-12 ring counter requires a minimum of ________. A) 10 flip-flops

B) 12 flip-flops

C) 6 flip-flops

D) 2 flip-flops

57.The T FF act as a divide by ----------- FF A)4

B)6

C)2

D) 8

58.For implementing a 5 bit sequence generator, how many FFs are required A)2

B)3

C)4

D)5

ANSWER 44

45

46

47

48

49

50

51

D

B

D

C

C

A

D

C

52

53

54

55

56

57

58

C

C

B

C

B

C

B

PART-B

(2 MARKS)

59. What are the classification of sequential circuits? (A.U.APRIL/MAY 2010) The sequential circuits are classified on the basis of timing of their signals into two types. They are, 1)Synchronous sequential circuit. 2)Asynchronous sequential circuit.

60. Define Flip flop. .( A.U.APRIL/MAY 2008) The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.

61.What are the different types of flip-flop? (A.U.APRIL/MAY 2010) There are various types of flip flops. Some of them are mentioned below they are, RS flip-flop SR flip-flop D flip-flop JK flip-flop T flip-flop 62.What is the operation of D flip-flop? . (A.U.APRIL/MAY 2012) In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset. 63. What is the operation of JK flip-flop? . (A.U.APRIL/MAY 2012) When K input is low and J input is high the Q output of flip-flop is set. When K input is high and J input is low the Q output of flip-flop is reset. When both the inputs K and J are low the output does not change When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge. 64. What is the operation of T flip-flop? (A.U.NOV/DEC 2006) T flip-flop is also known as Toggle flip-flop. When T=0 there is no change in the output. When T=1 the output switch to the complement state (ie) the output toggles. 65. Define race around condition. ( A.U.APRIL/MAY 2009) In JK flip-flop output is fed back to the input. Therefore change in the output results change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called ‘race around condition’. 66. What is edge-triggered flip-flop? (A.U.NOV/DEC 2012)

The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.

67. What is a master-slave flip-flop? (A.U.NOV/DEC 2011) A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave. 68.Define rise time. (A.U.NOV/DEC 2011) The time required to change the voltage level from 10% to 90% is known as rise time(tr). 69.Define fall time. A.U.APRIL/MAY 2011) The time required to change the voltage level from 90% to 10% is known as fall time(tf). 70.Define skew and clock skew. A.U.APRIL/MAY 2011) The phase shift between the rectangular clock waveforms is referred to as skew and the time delay between the two clock pulses is called clock skew. 71.Define setup time. (A.U.NOV/DEC 2006) The setup time is the minimum time required to maintain a constant voltage levels at the excitation inputs of the flip-flop device prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as tsetup. 72. Define hold time. (A.U.NOV/DEC 2006) The hold time is the minimum time for which the voltage levels at the excitation inputs must remain constant after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as thold . 73. Define propagation delay. (A.U.APRIL/MAY 2010) A propagation delay is the time required to change the output after the application of the input. 74.Define registers. (A.U.APRIL/MAY 2010)

A register is a group of flip-flops flip-flop can store one bit information. So an n-bit register has a group of n flip-flops and is capable of storing any binary information/number containing n-bits. 75.Define shift registers. (A.U.NOV/DEC 2006) The binary information in a register can be moved from stage to stage within the register or into or out of the register upon application of clock pulses. This type of bit movement or shifting is essential for certain arithmetic and logic operations used in microprocessors. This gives rise to group of registers called shift registers. 76.What are the different types of shift type? (A.U.NOV/DEC 2006) There are five types. They are, _Serial In Serial Out Shift Register _Serial In Parallel Out Shift Register _Parallel In Serial Out Shift Register _Parallel In Parallel Out Shift Register _Bidirectional Shift Register 77.Explain the flip-flop excitation tables for RS FF. (A.U.NOV/DEC 2010) RS flip-flop In RS flip-flop there are four possible transitions from the present state to the next state. They are, _ 0_0 transition: This can happen either when R=S=0 or when R=1 and S=0. _ 0_1 transition: This can happen only when S=1 and R=0. _ 1_0 transition: This can happen only when S=0 and R=1. _ 1_1 transition: This can happen either when S=1 and R=0 or S=0 and R=0. 78. Define sequential circuit? In sequential circuits the output variables dependent not only on the present input variables but they also depend up on the past history of these input variables. 79.Give the comparison between combinational circuits and sequential circuits. Combinational circuits Sequential circuits Memory unit is not required Memory unity is required ,Parallel adder is a combinational circuit Serial adder is a sequential circuit 80. What do you mean by present state? (A.U.APRIL/MAY 2010)

The information stored in the memory elements at any given time define. s the present state of the sequential circuit. 81. What do you mean by next state? The present state and the external inputs determine the outputs and the next state of the sequential circuit.

82. State the types of sequential circuits? (A.U.NOV/DEC 2010) 1. Synchronous sequential circuits 2. Asynchronous sequential circuits 83. Define synchronous sequential circuit(A.U.NOV/DEC 2010) In synchronous sequential circuits, signals can affect the memory elements only at discrete instant of time.

PART- C

(16 MARKS)

84. Explain the operation of triggered D FF. (A.U May/Jun 11) 85.How will you cnvert D FF into JK FF? Explain. (A.U NOV/DEC 2010) (A.U.APRIL/MAY 2012) 86.Explain the operation of master slave JK FF. (A.U NOV/DEC 2010) 87.Design a mod 9 counter and explain its working. (A.U NOV/DEC 2010) A.U.NOV/DEC 2011) 88. Design a mod 7 counter using JK FF. (A.U NOV/DEC 2008) (A.U.APRIL/MAY 2011) 89. Design a BCD up/down counter using S-R FF (A.U.NOV/DEC 2008) (A.U.APRIL/MAY 2011) 90.Convert a S-R FF into a D FF. (A.U.NOV/DEC 2008)

UNIT-III PART-A

ASYNCHRONOUS SEQUENCTIAL CIRCUIT (1 MARK)

91. How many address bits are needed to select all memory locations in the 2118 16K × 1 RAM? A)8

B)10

C)14

D)16

92. The check sum method of testing a ROM: A) indicates if the data in more than one memory location is incorrect B) provides a means for locating and correcting data errors in specific memory locations C) allows data errors to be pinpointed to a specific memory location D) simply indicates that the contents of the ROM are incorrect. 93.What is the meaning of RAM, and what is its primary role? A) Readily Available Memory; it is the first level of memory used by the computer in all of its operations B) Random Access Memory; it is memory that can be reached by any sub- system within a computer, and at any time. C) Random Access Memory; it is the memory used for short-term temporary data storage within the computer. D) Resettable Automatic Memory; it is memory that can be used and then automatically reset, or cleared, after being read from or written to. 94. The storage element for a static RAM is the ________. A) diode

B) resistor

C) capacitor

D) flip-flop

95. In a DRAM, what is the state of R/W during a read operation? A) Low

B) High

C) Hi-Z

D) None of the above

96.How many 2K × 8 ROM chips would be required to build a 16K × 8 memory system? A)2

B)4

C)8

D)16

97.What is the maximum time required before a dynamic RAM must be refreshed? A)2ms

B)4ms

C)8ms

D)10ms

98. Why are ROMs called nonvolatile memory? a) They lose memory when power is removed b) They do not lose memory when power is removed 99.The refresh period for capacitors used in DRAMs is ________. A) 2 ms

B) 2 s

100. The mask ROM is ________.

C) 64 ms

D) 64 s

A) MOS technology

B) diode technology

C) resistor-diode technology

D) DROM technology

101.Which is typically the longest: bit, byte, nibble, word? A) Bit

B) Byte

C) Nibble

D) Word

102. In ASM, the decision box is represented by A)circle

B) oval

C) Diamond

d)rectangle

103.In ASM, the state is represented by A)trapezoid

B) oval

C) Diamond

d)rectangle

C) Diamond

d)rectangle

104.In ASM, stop symbol is A)trapezoid

B) oval

105.In sequence generators design ------------- FFs are used A) SR

B)JK

C)T

D)D

ANSWER 91

92

93

94

95

96

97

98

C

D

C

D

B

C

A

B

99

100

101

102

103

104

105

A

A

D

C

D

B

D

PART-B

(2 MARKS)

106. Define merger graph. A.U.NOV/DEC 2011) The merger graph is defined as follows. It contains the same number of vertices as the state table contains states. A line drawn between the two state vertices indicates each compatible state pair. It two states are incompatible no connecting line is drawn. 107. Define Asynchronous sequential circuit? A.U.NOV/DEC 2011) In asynchronous sequential circuits change in input signals can affect memory element at any instant of time. 108.Give the comparison between synchronous & Asynchronous sequential circuits? (A.U.APRIL/MAY 2010)

Synchronous sequential circuits Asynchronous sequential circuits. Memory elements are clocked flip-flops Memory elements are either unlocked flip - flops or time delay elements.Easier to design More difficult to design. 109. The following wave forms are applied to the inputs of SR latch. (A.U.APRIL/MAY 2010) Determine the Q waveform Assume initially Q = 1 ,Here the latch input has to be pulsed momentarily to cause a change in the latch output state, and the output will remain in that new state even after the input pulse is over.

110.What is race around condition? .( A.U.APRIL/MAY 2008) In the JK latch, the output is feedback to the input, and therefore changes in the output results change in the input. Due to this in the positive half of the clock pulse if J and K are both high then output toggles continuously. This condition is known as race around condition. 111.Give the comparison between synchronous & Asynchronous counters. ( A.U.APRIL/MAY 2008) Asynchronous counters Synchronous counters In this type of counter flip-flops are connected in such a way that output of 1st flip-flop drives the clock for the next flipflop. In this type there is no connection between output of first flip-flop and clock input of the next flip – flop All the flip-flops are Not clocked simultaneously All the flip-flops are clocked simultaneously. 112. What is combinational circuit? .( A.U.APRIL/MAY 2009) Output depends on the given input. It has no storage element. 113. When do race condition occur? .( A.U.APRIL/MAY 2009) -two or more binary state variables change their value in response to the change in i/p variable 114. What are secondary variables? (A.U.NOV/DEC 2011) -present state variables in asynchronous sequential circuits 115. What is fundamental mode sequential circuit? (A.U.NOV/DEC 2011) -input variables changes if the circuit is stable -inputs are levels, not pulses -only one input can change at a given time 116.What are excitation variables? (A.U.APRIL/MAY 2011)

-next state variables in asynchronous sequential circuits 117.What is critical race? (A.U.APRIL/MAY 2011) -final stable state depends on the order in which the state variable changes -race condition is harmful 118.What is non critical race? -final stable state does not depend on the order in which the state variable changes -race condition is not harmful

119.What are the different techniques used in state assignment? : (A.U.NOV/DEC 2011) -shared row state assignment -one hot state assignment 120. What are the steps for the design of asynchronous sequential circuit? (A.U.NOV/DEC 2011) -construction of primitive flow table -reduction of flow table -state assignment is made -realization of primitive flow table

PART- C

(16 MARKS)

121. Design an asynchrnous sequential circuit that has 4 inputs x2 and x1 and one output z. when x1=0, the output z is 0. The first change in x2 that occurs while x1 is 1 will cause z to be 1. The output z will remain 1 until x1 returns to 0. (A.U NOV/DEC 2008) : (A.U.NOV/DEC 2011) 122. Design an asynchrnous sequential circuit that has 2 inputs x,y and one output z. The output z=1 if x changes from 0 to 1, z=0 if changes from 0 to 1 and z=0 otherwise. Realize the circuit using JK FFs.(A.U NOV/DEC 2010) 123. Design an asynchrnous sequential circuit that will output only second pulse received whenever a control input is asserted from LOW to HIGH state and will ignore any other pulse. (A.U NOV/DEC 2010)

124. Explain the step involed in designing of an asynchronous sequential logic circuits. (A.U NOV/DEC 2010) 125. Design an asynchrnous sequential circuit that has 2 inputs x,y and one output z. whenever y is 1, input x is transferred to z. when y is 0 and the output does not change for any change in x. (A.U NOV/DEC 2010) (A.U.APRIL/MAY 2011)

UNIT-IV PROGRAMMABLE LOGIC DEVICES, MEMORY AND LOGIC FAMILIES

PART-A

(1 MARK)

126. The generic array logic (GAL) device is ________. A) one-time programmable

B) reprogrammable

C) a CMOS device

D) reprogrammable and a CMOS device

127. The difference between a PLA and a PAL is: A) The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a programmable AND plane. B) The PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a programmable AND plane. C) The PAL has more possible product terms than the PLA. D) PALs and PLAs are the same thing. 128. PALs tend to execute ________ logic. A) SAP

B) SOP

C) PLA

D) SPD

129. ________ are used at the inputs of PAL/GAL devices in order to prevent input loading from a large number of AND gates. A) Simplified AND gates

B) Fuses

C) Buffers

130. Why must CMOS devices be handled with care? A) so they don’t get dirty B) because they break easily C) because they can be damaged by static electricity discharge 131.What is the major advantage of ECL logic?

D) Latches

A) very high speed

B) wide range of operating voltage

C)very low cost

D) very high power

132.The ________ memory an store is aa even if its power supply is cut A) SRAM

B) DRAM

C) DDRAM

D) ROM

133.The ________ is faster in terms of access A) SRAM

B) DRAM

C) PROM

D) EPROM

134.A 8Kbit memory has ________ Address lines A) 23

B) 213 C) 13

D) 3

135.A SRAM Cell consists of ________ MOSFETs in total A) 3

B) 4 C) 5

D) 6

136.The DRAM uses ________ for its data storage A) Floating gate transistor

B) MOSFET

C) Diode

D) Capacitor

137.An EPROM is erased using ________ A) Electromanetic radiation

B) X rays

C) UV rays

D) IR rays

138.In PROM, we can A) store the data once and read multiple times

B) store and erase data once

C) store and erase data multiple times

D) store once and read once

139.The flash EEPROM uses a ________ A) MOSFET

B)FLOTOX transistor C)FAMOS D)Fuses

140.The FLOTOX transistor uses ________ A) Tunneling

B)leakage C)avalanche injection D)charging & dicharging

ANSWER 126

127

128

129

130

131

132

133

B

A

B

C

C

A

D

A

134

135

136

137

138

139

140

C

D

D

C

A

B

A

PART-B 141. Explain PROM. (A.U.APRIL/MAY 2011) PROM (Programmable Read Only Memory)

(2 MARKS)

It allows user to store data or program. PROMs use the fuses with material like nichrome and polycrystalline. The user can blow these fuses by passing around 20 to 50 mA of current for the period 5 to 20μs.The blowing of fuses is called programming of ROM. The PROMs are one time programmable. Once programmed, the information is stored permanent.

142. Explain EPROM. (A.U.APRIL/MAY 2011) EPROM(Erasable Programmable Read Only Memory) EPROM use MOS circuitry. They store 1’s and 0’s as a packet of charge in a buried layer of the IC chip. We can erase the stored data in the EPROMs by exposing the chip to ultraviolet light via its quartz window for 15 to 20 minutes. It is not possible to erase selective information. The chip can be reprogrammed. 143. Explain EEPROM. (A.U.NOV/DEC 2011) EEPROM(Electrically Erasable Programmable Read Only Memory) EEPROM also use MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated floating gate in the device. EEPROM allows selective erasing at the register level rather than erasing all the information since the information can be changed by using electrical signals. 144. What is RAM? (A.U.NOV/DEC 2011) Random Access Memory. Read and write operations can be carried out. 145. What is programmable logic array? How it differs from ROM? In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM. 146.What is mask - programmable? .( A.U.APRIL/MAY 2009) With a mask programmable PLA, the user must submit a PLA program table to the manufacturer. 147. What is field programmable logic array? .( A.U.APRIL/MAY 2009)

The second type of PLA is called a field programmable logic array. The user by means of certain recommended procedures can program the EPLA. 148. List the major differences between PLA and PAL PLA: Both AND and OR arrays are programmable and Complex Costlier than PAL PAL AND arrays are programmable OR arrays are fixed ,Cheaper and Simpler 149. Define PLD. (A.U.NOV/DEC 2010) Programmable Logic Devices consist of a large array of AND gates and OR gates that can be programmed to achieve specific logic functions. 150. Give the classification of PLDs. (A.U.NOV/DEC 2010) PLDs are classified as PROM(Programmable Read Only Memory), Programmable Logic Array(PLA), Programmable Array Logic (PAL), and Generic Array Logic(GAL) 151. Define PROM. PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates connected to a decoder and a programmable OR array. 152. Define PLA(A.U NOV/DEC 2003) PLA is Programmable Logic Array(PLA). The PLA is a PLD that consists of a programmable AND array and a programmable OR array. 153. Define PAL(A.U NOV/DEC 2003) PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array with output logic. 154. Why was PAL developed ? A.U NOV/DEC 2005) It is a PLD that was developed to overcome certain disadvantages of PLA, such as longer delays due to additional fusible links that result from using two programmable arrays and more circuit complexity.

155. Why the input variables to a PAL are buffered(A.U.APRIL 2007) The input variables to a PAL are buffered to prevent loading by the large number of AND gate inputs to which available or its complement can be connected.

156. What does PAL 10L8 specify ? (A.U.APRIL 2007) PAL - Programmable Logic Array 10 - Ten inputs L - Active LOW Ouput 8 - Eight Outputs

157.Give the comparison between PROM and PLA. A.U NOV/DEC 2005) PROM PLA 1. And array is fixed and OR Both AND and OR arrays are array is programmable. Programmable. 2. Cheaper and simple to use. Costliest and complex than PROMS.

PART- C

(16 MARKS)

158.Explain the working of a 3 input TTL totempole NAND gate. (A.U NOV/DEC 2010) 159.Compare the various digital logic families. (A.U.APRIL/MAY 2011) 160. A combinational circuit is defined by the following function. f1(a,b,c) = Σ(0,1,6,7) f2(a,b,c) = Σ(2,3,5,7) Implement the circuit with the PLA having 3 inputs, 3 product terms and two outputs. (A.U APR/MAY 2005), (A.U NOV/DEC 2005) 161. Using ROM, design a combinational circuit which accepts 3 bit number and generates an output binary number equivalent to square of input number. (A.U NOV/DEC 2005) (A.U.APRIL/MAY 2011) 162. Explain the operation of bipolar Ram cell with suitable diagram. (A.U NOV/DEC 2005) 163. Explain the different types of ROM. (A.U NOV/DEC 2006) 164. What is Ram? Explain the different types of RAM in detail. 165. Draw the circuit of a CMOS two input NAND gate and explain its operation. (A.U NOV/DEC 2003) (A.U.APRIL/MAY 09)

166. Draw the circuit of a NMOS two input NOR gate and explain its operation. (A.U NOV/DEC 2003) 167. Discuss about the TTL parameters. Draw the TTL inverter circuit. (A.U NOV/DEC 2004) 168. Name the different categories and their use of Bipolar and MOS families. (A.U APR/May 2005) 160. Draw the circuit of TTL NAND gate and explain its operation (NOV/DEC 2005), (A.U NOV/DEC 2006) 169. Draw the circuit of NMOS NAND gate and explain its operation (A.U NOV/DEC 2005) 170. Draw the ECL circuit and explain its operation clearly. 171. Explain the totem circuit of TTL logic family. (A.U.APRIL/MAY 09)

UNIT-V

VHDL

PART-A

(1 MARK)

172.ALM is the acronym for ________. A) Array Logic Matrix

B) Arithmetic Logic Module

C) Asynchronous Local Modulator

D) Adaptive Logic Module

Option D 173.In an HDL application of a stepper motor, after an up/down counter is built what is done next? A) Build the sequencer C) Test the decoder

B) Test it on a simulator D) Design an intermediate integer variable

: Option B 174.What is the HDL key issue in the design of the MUX and DEMUX? A) Having the MUX and DEMUX part of the library B) Using the case statement in the process C) Describing the functions

D) Assigning signals under certain conditions Option D 175.Why are control inputs included in an HDL magnitude comparator? A) For cascading the chips

B) For control signal input

C) For signal control

D) For internal interconnections

Option A 176.What VHDL techniques are used to describe a priority encoder? A)Integer outputs and priority coding B) Signal outputs and priority coding C) Tristate outputs and priority coding D) Variables and priority coding Option C 177.The input are declared in verilog using ________. A) Always

B) input

C) output

D) module

178.If we give expression, the type of modeling is called as ________. A) General

B) dataflow

C) behavioral

D) structural

179.Conditional statements like if else, case can be used only in ________. A) dataflow

B) behavioral

C) structural

D) none of the above

180.In VHDL, V stands for ________. A) Verilog

B) VLSI

C) VHSIC

D) Very efficient

181.In VHDL, always the ________ file should be included A) Library

B) header

C) assembly

D) target

182.IN bit is used to declare A) 1 bit output

B) 1 bit input

C) 2 bit output

D) 2 bit input

183.For don’t cares ________ symbol is used A) ‘1’ B)’ 0’

C) ‘X’

D) ‘U’

184.Begin statement is not used in A) dataflow

B) behavioral

C) structural

D) none of the above

185.For describing circuits like flip flops ________ statement is used A) Always

B) entity

C) component

D) process

186.The VHDL is based on the ________ library

A) IEE

B) WORK C) IEEE

D) Standard

ANSWER 172

173

174

175

176

177

178

179

D

B

D

A

C

D

B

B

180

181

182

183

184

185

186

C

A

B

C

A

D

C

PART-B

(2 MARKS)

187.What is Test Bench? (A.U.APRIL/MAY 2010) The test bench name comes from the analogy with a real hardware test bench, on which a device under test is stimulated with waveform generates and observed with probes. A VHDL test bench consists of an architecture body containing an instance of component to be tested and processes that generate stimuli on signals, terminals or quantities connected to component instance. 188.What is Moore FSM(A.U.APRIL/MAY 2010) The output of a Moore finite state machine (FSM) depends only on the state and not on its inputs. This type of behaviour can be modeled using a single process with the case statement that switches on the state value. 189.What are the different kinds of the test bench? 

Stimulus only



Full test bench



Simulator specific



Hybrid test bench



Fast test bench

190.Name two subprograms and give the difference between these two. 1) Function: Only one output is possible in function.. 2) Procedure: Many outputs possible using procedure 191.What is variable class give example for variable?

An object of variable class can also hold a single value of a given type , However in this case different values can be assigned to a variable at different time. Ex: variable ss: integer; 192. Write the acronym for VHDL? (A.U.APRIL 2007) VHDL is an acronym for VHSIC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits). 193. What are the different types of modeling VHDL? (A.U.APRIL 2007) 1) Structural modeling 2) Data flow modeling 3) Behavioral modeling 4) Mixed type of modeling 194. What is a package and what is the use of these packages . A package declaration is used to store a set of common declaration such as components types procedures and functions these declaration can then be imported into others design units using a use clause. 195.What is variable class give example for variable? (A.U.APRIL/MAY 2010) An object of variable class can also hold a single value of a given type , However in this case different values can be assigned to a variable at different time. Ex: variable ss: integer; 196. Name two subprograms and give the difference between these two. (A.U.APRIL/MAY 2010) 1) Function: Only one output is possible in function.. 2) Procedure: Many outputs possible using procedure 197. What is subprogram overloading? ? (A.U.NOV/DEC 2010) If two or more subprogram to be executed in a same name. Overloading of subprogram should be performed 198. Write the VHDL coding for a sequential statement (d-flipflop ) ? (A.U.NOV/DEC 2010) entity dff is port(clk,d:in std_logic;

q:out std_logic); end; architecture dff of dff is begin process(clk,d) begin if clk’ event and clk=’ 1’ then q