Tutorial 2 - Finite State Machine Design & Synthesis

Tutorial 2 - Finite State Machine Design & Synthesis ECE-520/ECE-420 ~ Spring 1999 ~ Rev. 99.1 Dr. Paul Franzon --------------------------------------...
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Tutorial 2 - Finite State Machine Design & Synthesis ECE-520/ECE-420 ~ Spring 1999 ~ Rev. 99.1 Dr. Paul Franzon --------------------------------------------------------------------------------------------------------------------As you may recall from introductory logic design courses, controllers are usually implemented as Mealy or Moore type FSM (Finite State Machine). In a Mealy machine, the outputs depend on the present state and the value of the inputs, and can change asynchronously. In a Moore machine, the outputs depend only on the present state and change synchronously with the state transition and the clock edge.

1 FSM Specification: For this tutorial, we will use an example of controller for a vending machine that dispenses gum.

Coin Sensor

Nickel Dime

Vending Machine FSM

Door Change

Gum & Change Release Mechanism

Reset Clock

Vending Machine Block Diagram

The vending machine delivers a pack of gum after it has received 15 cents in coins. The vending machine has a single coin slot that accepts nickels or dimes, one at a time. A mechanical sensor indicates to the FSM whether a nickel or dime has been deposited. The controller’s outputs cause a single pack of gum to be released and a nickel is returned if the customer has deposited two dimes. The Nickel or Dime inputs are active-high and will be asserted for one clock period when the appropriate coin has been inserted into the coin slot. When 15 cents or more has been deposited, the machine will assert the active-high Door output until reset. External logic will provide an active-low Reset input to the machine each time a pack of gum is dispensed. If 20 cents has been deposited, the machine will assert the active-high Change output for 1 clock cycle. A state diagram consisting of nodes and arcs is commonly used to represent the FSM behavior. For a Mealy implementation, the nodes represent unique states of the circuit and the arcs represent the inputs that cause a transition from one state to another, in conjunction with the machine’s outputs. The state diagram for a Mealy machine implementation of the vending machine controller is shown on the following page.

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Reset/00

Outputs = Door Change

S0

Nickel/00

Dime/00

S1

Nickel/00 S2

Dime/11

Dime/10

Nickel/10 S3 !Reset/10

Mealy Vending Machine FSM

For a Moore implementation, the nodes represent unique states of the circuit and the machine’s outputs, and the arcs represent the inputs that cause a transition from one state to another. The state diagram for a Moore machine implementation of the vending machine controller is shown below. Reset

Outputs = [Door Change]

S0 [00] Nickel

Dime

S1 [00] Nickel S2 [00]

Dime

Dime

Nickel

S3 [11]

S4 [10] !Reset

Moore Vending Machine FSM

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2 Tutorial Organization: You will find files necessary for this tutorial in the ece520_info/tutorials/tutor2/bin/ locker. These include RTL descriptions of a Mealy and a Moore FSM written in Verilog, a Verilog test fixture for each, and the command scripts necessary to guide the Synopsys synthesis tool’s translation of each RTL description to a gate-level netlist. The tutorial is separated into the following parts: • Section 3 “Pre-Synthesis Simulation using Stand-Alone Cadence Verilog.” • Section 4 “Verilog RTL Synthesis using Synopsys Design Analyzer.” • Section 5 “Post-Synthesis Simulation using Stand-Alone Cadence Verilog.” • Section 6 “Cadence Timing Analysis Tool: Pearl.” • Section 7 “Running the tools in Scripts.” • Section 8 “References.”

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Pre-Synthesis Simulation using Stand-Alone Cadence Verilog. 3.1 Initial Setup. This section describes the steps necessary to configure your environment and obtain the files needed to complete this tutorial. This section will only need to be accomplished once. 1. The following steps will create working directories for the vending machine designs in your Cadence locker, change your current working directory to the vending machine directories, and then copy the files required for pre-synthesis simulation to them. eos> mkdir ~/ece520/cadence/vend eos> mkdir ~/ece520/cadence/vend/mealy eos> mkdir ~/ece520/cadence/vend/moore eos> attach ece520_info eos> cd ~/ece520/cadence/vend/moore eos> cp /ncsu/ece520_info/tutorials/tutor2/bin/ moore/* . eos> cd ~/ece520/cadence/vend/mealy eos> cp /ncsu/ece520_info/tutorials/tutor2/bin/ mealy/* . Ensure that your vend/mealy/ directory contains the files named mealyVend.cmd, mealyVend.dc, mealyVend.v, runmeall*, simmax, simmin, std-cell.tech, testMealy.v, testmax.v and testmin.v. Also ensure that your vend/moore/ directory contains the files named mooreVend.cmd, mooreVend.dc, mooreVend.v, runmeall*, simmax, simmin, std-cell.tech, testMoore.v, testmax.v and testmin.v. 3.2 Mealy Machine Simulation. This section will describe the steps used to simulate and verify the Mealy design implementation using the stand-alone Cadence Verilog tool. Note that the steps outlined here are very similar to those from Tutorial 1 - Introduction to ASIC Design Methodology. 1. Change your current working directory to the one created for the Mealy machine design. eos> cd ~/ece520/cadence/vend/mealy

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2. With a text editor, open and inspect the file named mealyVend.v. You should note that there exist several Synopsys directives within the comments of this file. These specify the state enumeration used, the state vector, and that the case statement is executed in parallel and all cases are fully specified. You should also note that the case statement describes the machines behavior based upon the current state and that within particular states, combinational logic is inferred to determine the outputs. Take a moment to recognize the correlation between these and the state diagram shown in the specification. 3. To execute the simulation, enter the following at your EOS prompt: eos> add cadence eos> verilog testMealy.v Note that it may not be readily apparent from the output of the Verilog $monitor(...) system task whether the FSM behaves as expected. 4. Ensure that mealy.shm directory was created during the simulation above. Invoke the SimWave waveform display tool by entering the following at your EOS prompt: eos> wd & After a moment, the SimWave waveform display window should appear. Note: If you have not added the Cadence tools to your path during this session, you will need to enter “add cadence” at your EOS prompt before you can use the SimWave tool. 5. From the SimWave window menu bar, select: File -> Database -> Load... After a moment, the Load Database window should appear. 6. In the Load Database window, ensure that the shm button is selected in the Format box and left-click with the mouse to highlight mealy.shm in the Directories box. Then left-click on the button labeled OK. 7. From the SimWave window menu bar, select: Edit -> Add Signals... After a moment, the SimWave Browser should appear. 8. Use the SimWave Browser to traverse the simulation hierarchy into the test_fixture instance and select all of the signals for display except i. 9. In the SimWave Browser, select the Display Signals icon to display the selected signals in the waveform display window. 10. In the SimWave waveform display, select the Zoom Fit icon to display the entire simulation result. 11. Carefully examine the signals and determine whether or not the Mealy implementation meets the design specification. In particular, note that the Door output is momentarily asserted at approximately 86 ns into the simulation when only two nickels have been deposited, and

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that the Change output is asserted at about 196 ns when only one dime has been deposited. This example illustrates the output glitches that can be inherent in the asynchronous nature of the Mealy machine. 3.3 Moore Machine Simulation. This section will describe the steps used to simulate and verify the Moore design implementation using the stand-alone Cadence Verilog tool. 1. Change your current working directory to the one created for the Mealy machine design. eos> cd ~/ece520/cadence/vend/moore 2. With a text editor, open and inspect the file named mooreVend.v. Note that the case statement describes the machines behavior based upon the current state and that within each state, there is no combinational logic inferred to determine the FSM outputs. They depend entirely upon the current state of the machine. Take a moment to recognize the correlation between these and the state diagram shown in the specification. 3. To execute the simulation, enter the following at your EOS prompt: eos> verilog testMoore.v Note: If you have not added the Cadence tools to your path during this session, you will need to enter “add cadence” at your EOS prompt before you can use the Verilog tool. 4. Ensure that moore.shm directory was created during the simulation above. Invoke the SimWave waveform display tool by entering the following at your EOS prompt: eos> wd & 5. From the SimWave window menu bar, select: File -> Database -> Load... After a moment, the Load Database window should appear. 6. In the Load Database window, ensure that the shm button is selected in the Format box and left-click with the mouse to highlight moore.shm in the Directories box. Then left-click on the button labeled OK. 7. From the SimWave window menu bar, select: Edit -> Add Signals... 8. Move completely down through the simulation hierarchy into the test_fixture instance and select all of the signals for display except i. 9. In the SimWave Browser, select the Display Signals icon to display the selected signals in the waveform display window. 10. In the SimWave waveform display, select the Zoom Fit icon to display the entire simulation result.

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11. Carefully examine the signals and determine whether or not the Moore implementation meets the design specification. In particular, note that the Door and Change outputs are appropriately asserted according to the specification. Generally, the fully synchronous nature of Moore finite state machines make them easier to implement and debug, however Mealy machines encode control in fewer states and therefore often require less hardware.

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Verilog RTL Synthesis using Synopsys Design Analyzer. 4.1 Mealy Machine Synthesis. This section will describe the steps used to synthesize the Mealy design implementation using the Synopsys Design Analyzer tools. Again, note that the steps outlined here are very similar to those from Tutorial 1 - Introduction to ASIC Design Methodology. 1. Change your current working directory to the one created for the Mealy machine design. eos> cd ~/ece520/cadence/vend/mealy 2. With a text editor, open and inspect the file named mealyVend.dc. This file contains a list of Synopsys commands that will be executed sequentially by the Design Analyzer. Note that each command has been fully commented for you so that you can recognize and understand the steps taken during synthesis to produce an optimal design that will function properly within a set of given constraints. Please take a moment to read carefully over the contents of this file and note the following commands and their purpose: • set_fsm_state_vector {CurrentState_reg[0]...} specifies the instance names for the flip-flops used to implement the state-vector. • set_fsm_encoding {“S0=2#00” “S1=2#10”...} specifies the bit encoding for states in the current design. • set_fsm_encoding_style auto specifies the encoding style Synopsys should use for assigning un-encoded states in the current design. • group -fsm -design_name mealyVend_fsm creates and names a new level of hierarchy for the finite state machine. • report_fsm displays the state machine attributes and information for the current design. • extract -minimize creates a technology independent state-table representation of the finite state machine’s behavior and minimizes all state transition logic. • set_fsm_minimize true specifies that state minimization should be performed on the finite state machine during compile. 3. To invoke the Design Analyzer tool, enter the following at your EOS prompt: eos> add synopsys eos> design_analyzer & After a moment, the Synopsys Design Analyzer window should appear. 4. To access the Command Window, select; Setup -> Command Window... from the Design Analyzer menu bar. After a moment, the Command Window should appear.

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5. At the design_analyzer prompt in the Command Window, enter: design_analyzer> include mealyVend.dc This command will cause Synopsys to read and execute the commands from the script file. You should see the contents of the file echoed to the Command Window along with responses from the synthesis tool. Remember that you can access the results later on since they are simultaneously echoed to a view_command.log file in the working directory. Note: Without exception, you must determine and correct all conditions that lead to “error” statements. You can choose to accept conditions that lead to “warning” statements, but only when you determine that the ramifications are acceptable within your design. 6. The script will take a few moments to execute. You can determine when synthesis is complete be observing the design_analyzer prompt in the Command Window. When a blinking cursor re-appears, the script should have been executed completely. 7. In the Synopsys Design Analyzer, left click on the mealyVend symbol in order to select it. You should notice that it’s border becomes a dashed line and that the down arrow button in the lower left-hand side of the window becomes active. Left-click on the button to see a “symbol view” of the synthesized FSM. 8. You should now see that the Symbol View button, pictured as a black-box with inputs and outputs on the left-hand side of the window, is active and high-lighted, and that the Schematic View button, pictured as an AND gate, is also active. Left-click on the Schematic View button to see the synthesized Mealy FSM circuit. 9. Take a moment to examine the design and recognize that the outputs do in fact depend upon a combination of the current state flip-flops and the inputs. Also note that there exists an asynchronous path from the Nickel input and the Door output. Synopsys relies upon static timing analysis algorithms to determine whether timing constraints are met. This is inadequate for asynchronous paths and requires that you perform a full functional verification of to verify asynchronous behavior. Since it is often difficult to perform a full verification, you are should ensure that all paths in your designs are synchronized. 10. When you are finished, select; File -> Quit from the Synopsys Design Analyzer menu bar. 4.2 Moore Machine Synthesis. This section will describe the steps used to synthesize the Moore design implementation using the Synopsys Design Analyzer tools. Again, note that the steps outlined here are very similar to those from Tutorial 1 - Introduction to ASIC Design Methodology. 1. Change your current working directory to the one created for the Mealy machine design. eos> cd ~/ece520/cadence/vend/moore

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2. Invoke the Design Analyzer tool, enter the following at your EOS prompt: eos> add synopsys eos> design_analyzer & After a moment, the Synopsys Design Analyzer window should appear. 3. To access the Command Window, select; Setup -> Command Window... from the Design Analyzer menu bar. After a moment, the Command Window should appear. 4. At the design_analyzer prompt in the Command Window, enter: design_analyzer> include mooreVend.dc Note: Without exception, you must determine and correct all conditions that lead to “error” statements. You can choose to accept conditions that lead to “warning” statements, but only when you determine that the ramifications are acceptable within your design. 5. The script will take a few moments to execute. You can determine when synthesis is complete be observing the design_analyzer prompt in the Command Window. When a blinking cursor re-appears, the script should have been executed completely. 6. In the Synopsys Design Analyzer, left click on the mooreVend symbol in order to select it. You should notice that it’s border becomes a dashed line and that the down arrow button in the lower left-hand side of the window becomes active. Left-click on the button to see a “symbol view” of the synthesized FSM. 7. You should now see that the Symbol View button, pictured as a black-box with inputs and outputs on the left-hand side of the window, is active and high-lighted, and that the Schematic View button, pictured as an AND gate, is also active. Left-click on the Schematic View button to see the synthesized Moore FSM circuit. 8. Take a moment to examine the design and recognize that the outputs do in fact depend only upon the current state flip-flops and the not the inputs. 9. When you are finished, select; File -> Quit from the Synopsys Design Analyzer menu bar.

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Post-Synthesis Simulation using Stand-Alone Cadence Verilog. 5.1 Mealy Machine Simulation. This section will describe the steps used to simulate and verify the gate level Mealy design created by Synopsys using the Standard Delay Format (SDF) files to “forward annotate” best and worst case timing information to the Cadence Verilog tool. Again, note that the steps outlined here are very similar to those from Tutorial 1 - Introduction to ASIC Design Methodology.

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1. Change your current working directory to the one created for the Mealy machine design. eos> cd ~/ece520/cadence/vend/mealy 2. The simmax* file is a script file containing a rather lengthy command to invoke the standalone Cadence Verilog tool with the gate level netlist created by Synopsys. This command also causes Cadence to incorporate the maximum timing delay information created by Synopsys into the simulation. At your EOS prompt, enter the following: eos> simmax This will cause Cadence to simulate much as before, except that the waveform database is now called wavesmax.shm. You should also note that the Cadence response includes a statement that the SDF “back annotation” completed successfully. Note: If you have not added the Cadence tools to your path during this session, you will need to enter “add cadence” at your EOS prompt before you can proceed with this section. 3. This step will mimic the one above except that it will do so for the minimum timing delays. At your EOS prompt, enter the following; eos> simmin Now the Cadence simulation will save the results to a wavesmin.shm database. 4. As before, enter the following at your EOS prompt to invoke the SimWave tool; eos> wd & In a moment, a SimWave:0 waveform display window should appear. 5. Using the SimWave:0 window menu bar, select; File -> Database -> Load... to open the wavesmax.shm database. 6. Again using the SimWave:0 waveform display window menu bar, select; File -> Database -> Load... to open the wavesmin.shm database. 7. A new SimWave:1 window should open. Since it isn’t needed, from it’s menu bar, select; File -> Close Window 8. As before, use the SimWave:0 menu bar to select; Edit -> Add Signals... 9. From the Simwave Browser that appears, click and hold on the File button in the upper right-hand corner and select A: wavesmax.shm to access the maximum timing delay data. 10. Traverse the hierarchy and as before, add all of the signals to the waveform display that are contained in the test_fixture instance. 11. Again from the Simwave Browser, click and hold on the File button in the upper right-hand corner and select A: wavesmin.shm to access the minimum timing delay data. 12. Traverse the hierarchy and add the signals to the waveform display as above.

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13. Close the SimWave Browser and carefully examine the waveforms in the SimWave:0 window. In particular, you should note that the output glitches still appear. 14. When you are finished with the waveform display, select; File -> Exit from the SimWave menu bar. 5.2 Moore Machine Simulation. This section will describe the steps used to simulate and verify the gate level Moore design created by Synopsys using the Standard Delay Format (SDF) files to “forward annotate” best and worst case timing information to the Cadence Verilog tool. 1. Change your current working directory to the one created for the Mealy machine design. eos> cd ~/ece520/cadence/vend/moore 2. The simmax* file is a script file containing a rather lengthy command to invoke the standalone Cadence Verilog tool with the gate level netlist created by Synopsys. This command also causes Cadence to incorporate the maximum timing delay information created by Synopsys into the simulation. At your EOS prompt, enter the following: eos> simmax This will cause Cadence to simulate much as before, except that the waveform database is now called wavesmax.shm. You should also note that the Cadence response includes a statement that the SDF “back annotation” completed successfully. Note: If you have not added the Cadence tools to your path during this session, you will need to enter “add cadence” at your EOS prompt before you can proceed with this section. 3. This step will mimic the one above except that it will do so for the minimum timing delays. At your EOS prompt, enter the following; eos> simmin Now the Cadence simulation will save the results to a wavesmin.shm database. 4. As before, enter the following at your EOS prompt to invoke the SimWave tool; eos> wd & In a moment, a SimWave:0 waveform display window should appear. 5. Using the SimWave:0 window menu bar, select; File -> Database -> Load... to open the wavesmax.shm database. 6. Again using the SimWave:0 waveform display window menu bar, select; File -> Database -> Load... to open the wavesmin.shm database. 7. A new SimWave:1 window should open. Since it isn’t needed, from it’s menu bar, select; File -> Close Window

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8. As before, use the SimWave:0 menu bar to select; Edit -> Add Signals... 9. From the Simwave Browser that appears, click and hold on the File button in the upper right-hand corner and select A: wavesmax.shm to access the maximum timing delay data. 10. Traverse the hierarchy and as before, add all of the signals to the waveform display that are contained in the test_fixture instance. 11. Again from the Simwave Browser, click and hold on the File button in the upper right-hand corner and select A: wavesmin.shm to access the minimum timing delay data. 12. Traverse the hierarchy and add the signals to the waveform display as above. 13. Close the SimWave Browser and carefully examine the waveforms in the SimWave:0 window. In particular, you should note that output glitches no longer appear. 14. When you are finished with the waveform display, select; File -> Exit from the SimWave menu bar.

6 Cadence Timing Analysis Tool: Pearl. 6.1 Mealy Timing Analysis eos> cd ~/ece520/cadence/vend/mealy eos> pearl mealyVend.cmd 6.2 Moore Timing Analysis eos> cd ~/ece520/cadence/vend/moore eos> pearl mooreVend.cmd Note: If you have not added the Cadence tools to your path during this session, you will need to enter “add cadence” at your EOS prompt before you can run the Pearl.

7 Running the tools in Scripts. To ensure process repeatability, it is a good idea to use scripts. Examine the file runmeall. This script will run through all the steps of the tutorial except the waveform viewer. At the EOS prompt, type: 7.1 Mealy Script eos> cd ~/ece520/cadence/vend/mealy eos> runmeall 7.2 Moore Script eos> cd ~/ece520/cadence/vend/moore eos> runmeall

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Note: If you have not added the Cadence and Synopsys tools to your path during this session, you will need to enter “add cadence” and “add synopsys” at your EOS prompt before you can run the script

8 References. 8.1 On-Line Documentation. The available on-line documentation for the Cadence tool suite is called OpenBook. It is accessed by entering the following at your EOS prompt: eos> add cadence eos> openbook & The available on-line documentation for the Synopsys tool suite is called IView. It is accessed by entering the following at your EOS prompt: eos> add synopsys eos> iview & There is additional, “man page” style help available for Synopsys commands when using DC Shell. It is accessed by entering the following at the dc_shell prompt: dc_shell> help The available on-line documentation for the Pearl tool suite is called OpenBook. It is accessed by entering the following at your EOS prompt: eos> add cadence eos> openbook & Openbook -> Timing -> Pearl User Guide Chapter 4 explains all commands for Pearl. 8.2 Texts. • Smith, M.J., “Application Specific Integrated Circuits,” Addison-Wesley, ISBN 0201-50022-1. • Smith, Douglas J., “HDL Chip Design,” Doone, ISBN 0-9651934-3-8. • Kurup and Abbasi, “Logic Synthesis using Synopsys,” Kluwer Academic, ISBN 07923-9786-X. • Thomas and Moorby, “The Verilog Hardware Description Language,” Kluwer Academic, ISBN 0-7923-9723-1. • Palnitkar, Samir, “Verilog HDL, A Guide to Digital Design and Synthesis,” Prentice Hall, ISBN 0-13-451675-3. • Sternheim, Eli, “Digital Design and Synthesis with Verilog HDL,” Automata, ISBN 0-9627488-2-X. • Lee, J.M., “Verilog Quickstart,” Kluwer Academic, ISBN 0-7923-9927-7.

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