Tutorial: Modeling and Testing Finite State Machines (FSM) Finite State Machines (FSMs) have been introduced to aid in specifying the behavior of sequential circuits. For example, we want to design part of a laser surgery system such that a surgeon can activate a laser by pressing a button B (B=1). The laser should stay on (X=1) for exactly 3 clock cycles, then shut off (X=0). We want to ensure that the laser will only stay on for 3 clock cycles regardless of whether the button is pressed for multiple clock cycles or if the button is pressed again while the laser is activated. Figure 1(a) illustrates the FSM describing the behavior of the three cycle high laser controller. To implement the three cycles high laser controller we modify the standard controller architecture for our particular application. Because we have four states, we need a 2-bit state register. Additionally, the FSM accepts input B indicating a button press, and output X controlling the laser. The FSM inputs and outputs are connected to the combinational logic block as shown in Figure 1(b). Figure 1: Three cycle high laser controller’s (a) FSM and (b) corresponding controller architecture. Inputs: B Outputs: X

B

X=0 Off

Combinational Logic

X n1 n0

B’ s1

s0

B X=1

X=1

X=1

On1

On3

On2

clk

(a)

State Register

(b)

Modeling FSM in Verilog We begin modeling the FSM controller architecture by declaring a module, laser_timer, and its corresponding interface, as shown in Figure 2. The laser_timer module has three inputs (RST, CLK, B) and one output (X). It is important to include a reset signal in all sequential circuits. The reset signal is used to indicate the

Figure 2: Verilog Module Declaration module laser_timer(RST, CLK, B, X); // user interface input RST, CLK; input B; output X; reg X; // states parameter parameter parameter parameter

Off On1 On2 On3

= = = =

2'b00; 2'b01; 2'b10; 2'b11;

// variables reg [1:0] State; reg [1:0] NextState;

…

Figure 3: State Register Process // process modeling state register always @ (posedge RST or posedge CLK) begin if( RST == 1 ) State