VHDL. Chapter B. State Machine. Outline. Memory Controller Example. Finite State Machine Structure. Memory Controller (Conventional Design)

Chapter B State Machine Outline z Finite State Machine – Moore & Mealy FSM – Memory Control Example – Extended Memory Controller – Two & Three Proce...
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Chapter B State Machine

Outline z

Finite State Machine – Moore & Mealy FSM – Memory Control Example – Extended Memory Controller – Two & Three Process State Machine

VHDL

– One Process State Machine z

Algorithmic State Machine – Simple Example (“111…1” Detector) – Multiplier Example

VHDL - Flaxer Eli

Ch B - 1

State Machine

VHDL - Flaxer Eli

Memory Controller Example

Finite State Machine Structure (Mealy machine)

ready

state

idle input s

Next-state Logic

excitation

State Memory

current state

F

Ch B - 2

State Machine

Output Logic

ready

outputs

ready

G

outputs oe we

idle decision

0 0

0 0

write

0

1

read

1

0

ready

decision

clock

read_write State memory: Usually edge-triggered D or JK flip-flops

clock

write

read_write

ready

read

Moore Machine ready

VHDL - Flaxer Eli

Ch B - 3

State Machine

VHDL - Flaxer Eli

Memory Controller (Conventional Design) State idle

00

01

11

10

oe

we

00

00

01

01

00

0

0

State Machines In VHDL z

11

10

10

0

0

write

11

11

00

00

11

0

1

read

10

10

00

00

10

1

0

A given state diagram can be easily translated into a high level VHDL description without having to generate the state transition table.

z

11

Ch B - 4

Outputs

read_write, ready

PS: q0 q1

decision 0 1

State Machine

In VHDL each state can be translated to a case in a CASE-WHEN construct.

z

The state transitions can then be specified in IF-THEN-ELSE statements.

NS: Q0 Q1

VHDL - Flaxer Eli

Q0 = q 0 q 1 + q 0 ready

we = q 0 q 1

Q1 = q 0 q 1 ready + q 0 q 1 read_write + q 0 q 1 ready

oe = q 0 q 1

State Machine

Ch B - 5

VHDL - Flaxer Eli

State Machine

Ch B - 6

Memory Controller Using VHDL (p1) ENTITY example IS PORT ( read_write, ready, clk : oe, we : END example;

Memory Controller Using VHDL (p2) WHEN decision => oe