## State Machine Analysis and Design

State Machine Analysis and Design Sequential Circuit • Output depends on current input and past history of input – Clock – Memory • The “memory” of...
Author: Ann Hall
State Machine Analysis and Design

Sequential Circuit • Output depends on current input and past history of input – Clock – Memory

• The “memory” of the circuits is finite – Most applications do not need long history – A circuit is built with limited resources • Thus it can’t remember all the past input

• The number of past input patterns are finite – Many of these are actually equivalent – History can be characterized with states

State and state variable • “State” embodies all the information about the past needed to predict current output based on current input • A “State” can be represented with bits – State variables, one or more bits of information

State machines: clocked synchronous sequential circuits • Use edge-triggered flip-flops • All flip-flops are triggered from the same master clock signal, and therefore all change their states together (i.e. simultaneously) • Feedback sequential circuits – No explicit flip-flops; states stored in feedback loops • Example: edge-triggered D flip-flop itself (4 states) • Sections 7.9 (advanced courses)

Clock signals • Very important with most sequential circuits – State variables change at clock edges.

What happen in a cycle? • Wait for state variables to become stable • Generate output from current input and stable variables • Generate new state variables (next state) – Feed new state variables to flip-flops – Early enough so flip-flop can take new values

State 0 1 2

Input 0 Input 1 Input 2 …

Input 0 Input 1 Input 2 …

Describing Sequential Circuits • State table – For each current-state, specify next-states as function of inputs – For each current-state, specify outputs as function of inputs

• State diagram – Graphical version of state table

State/output table

State-machine structure (Mealy) output depends on state and input

typically edge-triggered D flip-flops

State-machine structure (Moore) output depends on state only

typically edge-triggered D flip-flops

State-machine structure (pipelined)

• It is desirable that the outputs do not change during a cycle – Output-coded state assignment • Outputs taken directly from flip-flops, valid sooner after clock edge

– Pipelined outputs • Outputs depends on the input and state in the previous cycle

Notation, characteristic equations • Notation Q∗ means “the next value of Q.” • “Excitation” is the input applied to a device that determines the device’s next state, i.e. excitation + Q will determine Q∗. • “Characteristic equation” specifies the Q∗ of a device as a function of its excitation. It describes the functional behavior of the device without detailed timing behavior -- simplified description that helps with analysis of state machines.

Common latch and flip-flop characteristic equations

State-machine analysis steps Assumption: Starting point is a logic diagram. 1. Determine next-state logic F and output logic G. 2a. Construct the state table – For each state/input combination, determine the excitation value. – Using the characteristic equation, determine the corresponding next-state values (e.g. trivial with D and T flip-flop’s).

2b. Construct the output table – For each state/input combination, determine the output value (Can be combined with the state table in 2a.)

3. Draw the state diagram.

Example: state machine analysis (which model?)

Excitation equations (for D0, D1)

Transition equations (for Q and Q∗) • Excitation equations (covering next-state logic F):

• Characteristic equations for D flip-flop:

• Substitute excitation equations into characteristic equations:

Transition equations and transition/state/output tables (transition equations) (for output logic G)

Transition table

State table

State/output table

State diagram

• Circles for states, totally 4 in this example • Arrows for transitions (note output information)

Modified state machine (which model?) MAXS

MAXS = Q0 ⋅ Q1

Updated state/output table, state diagram

Why is MAXS “inside the circle”? Unlike MAX, MAXS only depends on present state, i.e. Q1 and Q0.

Timing diagram for the state machine

• • • •

State transitions take place only when EN = 1 MAX can be changed by EN within a clock cycle (Mealy) MAXS does not depend on EN (Moore) States: A – 00, B – 01, C – 10, D – 11 for Q1∗ Q0∗

State-machine design and synthesis

The creative part, like writing a C++ program

Turning the crank, like a compiler generates .exe

• Example: Design a combination lock with two inputs, X1 and X2. Unlock for sequence X1, X2, X2 (one input per clock).

Example: combination lock • Design a combination lock with two inputs, X1 and X2. Open the lock if given the sequence X1, X2, X2. That is, in sequence, X1X2 = 10, 01, 01 to effect state transitions. Then “re-start”. State X1 X2 -------------------------- ----------------------------------------------Meaning Name 00 01 10 11 Unlock -------------------------- ----------------------------------------------Start

A

A

A

B

A

0

Got X1

B

A

C

A

A

0

Got X1,X2

C

A

D

A

A

0

Got X1,X2,X2 D

A

A

B

A

1

(State D is like State A, except in State D, Unlock = 1.)

State assignment • Can minimize number of states, but hardly anyone bothers to do this anymore – thus often a design is not the most lean. • Need to assign state-variable combinations to these states. – Minimum number of variables for n states is log2 n – Using more than the minimum number may be advantageous in some situations, i.e. one state variable per state – Example: Here we have 4 states using 2 state variables Q1, Q2:

A ==> Q1Q2 = 00 B ==> Q1Q2 = 01 C ==> Q1Q2 = 10 D ==> Q1Q2 = 11

Up to this point is “art”, the rest will be “turning the crank.”

Transition table • Substitute state-variable combinations for states in the state table. State X1 X2 -------------------------- ----------------------------------------------Meaning Q1Q2 00 01 10 11 Unlock -------------------------- ----------------------------------------------Start

00

00

00

01

00

0

Got X1

01

00

10

00

00

0

Got X1,X2

10

00

11

00

00

0

Got X1,X2,X2 11

00 00 01 00 1 ---------------------------------------------Q1∗ Q2∗

Transition equations; circuit • Transition table specifies each state variable (Q1∗, Q2∗) as a combinational logic function of Q1, Q2, X1, X2. – Find a realization for Q1∗, Q2∗ with your favorite means – ad hoc, minimal sum-of-products or K-maps, etc.

• Build the circuit. Can you identify your “next-state logic F”? Q1

Q1∗

D

Q

D

Q

Q1 UNLOCK

Q2 X1 X2 CLK

Q2∗

Q2

Another design example (Wakerly section 7.4.1) • Design a machine with inputs A and B and output Z that is 1 if: – A had the same value at the two previous ticks, or – B has been 1 since the last time the above was true – Once Z=1, can stay there as long as B = 1, regardless of A changes

Timing diagram and state sequence

State assignment • There are 6,720 different state assignments of 5 states with 3 state variables, i.e. (8!/(5!3!))5! . 5 states need at least 3 FF’s (23 total). – How many different ways to choose 5 states out of 8 possible states? – 5! ways to assign these states to each different choice from above.

• Here are a few “obvious” or “interesting” ones:

Transition/output table (decomposed assignment)

• Simple substitution from text states into state variables. • With D flip-flops, excitation table is identical to transition table. • Remember, Q* = D for D flip-flops.

Develop excitation equations

• Assume unused states have next-state = 000

Don’t cares for the next-state entries of unused states

D1 = 1 D2 = Q1•Q3’•A’+Q3•A+ Q2•B D3 = A

Logic diagram D1 = 1 D2 = Q1•Q3’•A’+Q3•A+ Q2•B D3 = A

Read Section 7.5 on designing state machines using state diagrams

State machine design steps •

• •

• • • • • •

Construct a state/output table corresponding to the description or specification – Using mnemonic names for the states – May start with a state diagram Minimize the number of states (optional) State assignment – Choose state variables and assign state-variable combinations to the named states Substitute the state-variable combinations into the state/output table to create the transition/output table Choose a flip-flop type Construct an excitation table that shows the required excitation Derive excitation equations from the excitation table Derive output equations Draw a logic diagram

1s-counting machine •

Design a state machine Two inputs, X and Y, and one output Z. Z should be 1 if the number of 1’s on X and Y since reset is a multiple of 4, and 0 otherwise.

Transition/excitation and output table • State assignment: S0-S3 = (00, 01, 11, 10) – Try a different state assignment in homework

D1 = Q2 • X′ • Y + Q1′ • X • Y + Q1 • X′ • Y′ + Q2 • X • Y′ D2 = Q1′ • X′ • Y + Q1′ • X • Y′ + Q2 • X′ • Y′ + Q2′ • X • Y Z = Q1′ • Q2′

Excitation maps for D1 and D2 inputs

Combinational lock •

Design a state machine One input X. Two outputs UNLK and HINT. UNLK is 1 if and only if X is 0 and the sequence received on X at the preceding seven clock ticks was 0110111. HINT is 1 if and only if the current value of X is the correct one to move the machine closer to being in the “unlocked” state (where UNLK = 1).

Transition/excitation and output table • State assignment A-H:0-7

K-maps for D1, D2, and D3

D1 = Q1•Q2′•X + Q1′•Q2•Q3•X′ + Q1•Q2•Q3′ D2 = Q2′•Q3•X + Q2•Q3′•X D3 = Q1•Q2′•Q3′ + Q1•Q3•X′ + Q2′•X′ + Q1′•Q3′•X′ + Q2•Q3′•X

K-maps for UNLK and HINT

UNLK = Q1•Q2•Q3•X HINT = Q1′•Q2′•Q3′•X′ + Q1•Q2′•X + Q2′•Q3•X + Q2•Q3•X′+ Q2•Q3′•X

Another example •

Design a state machine that recognize a binary number that can be evenly divided by 4 – Input: D, providing bits from MSB to LSB, 1 bit per cycle – Output: Y if the bits received so far can be evenly divided by 4

State

D

Y

0

1

S00

S00

S1

1

S1

S0

S1

0

S0

S00

S1

0

Design State Machines using State Diagrams • Sometimes people like graphical approaches – It is simpler

• However, it is also more error prone – A state table is an exhaustive listings of the next state for each state/input combination • You will not miss a case

– In a stage diagram, every input combination should be covered exactly by one expression • Given an input combination, one and only one expression is true • It is not easy to see

Ambiguity in state diagram • In a properly constructed state diagram, each input combination is covered exactly once by an expression of an outgoing arc • Ambiguous: double-covered or uncovered • Some input combinations are covered by more than one expressions (double-covered) – Given such an input combination, you have two or more transitions to follow – AND of any two expressions should be 0

• Some input combinations are not covered by any expressions (uncovered) – Given such an input combination, you do not have any transitions to follow – OR of all expressions should be 1

Example of an ambiguous state diagram

1965 Ford Thunderbird tail lights

Flashing sequence for T-bird tail-lights

Left turn

Right turn

State diagram for T-bird tail-lights state machine

Corrected and enhanced state diagram for T-bird tail-lights state machine

State assignment for T-bird tail-lights state machine

Transition list for T-bird tail-lights state machine