Finite State Machines •  Finite State Machines (FSMs) are a useful abstraction for sequential circuits with centralized “states” of operation •  At each clock edge, combinational logic computes outputs and next state as a function of inputs and present state

inputs

Finite State Machines

Combinational Logic

+ present state

•  Design methodology for sequential logic -- identify distinct states -- create state transition diagram -- choose state encoding -- write combinational Verilog for next-state logic -- write combinational Verilog for output signals •  Lots of examples

outputs + next state

n

n Q

Registers

D

CLK

Reminder: Lab #2 due tonight! Lab #3 tutorial Sun @ 7pm in 34-301 6.111 Fall 2009

Lecture 5

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6.111 Fall 2009

Two Types of FSMs

•  A level-to-pulse converter produces a singlecycle pulse each time its input goes high.

•  Moore FSM: inputs x0...xn

Comb. Logic

n

2

Design Example: Level-to-Pulse

Moore and Mealy FSMs : different output generation next state S+

Lecture 5

•  It’s a synchronous rising-edge detector. Q

D

Comb. Logic

Registers

CLK

•  Sample uses:

outputs yk = fk(S)

–  Buttons and switches pressed by humans for arbitrary periods of time

n

–  Single-cycle enable signals for counters

present state S

•  Mealy FSM: direct combinational path!

inputs x0...xn

Comb. Logic

S+ n

D

Comb. Logic

Q

Registers

CLK

outputs yk = fk(S, x0...xn)

L Whenever input L goes from low to high...

n

Level to P Pulse Converter

CLK

...output P produces a single pulse, one clock period wide.

S 6.111 Fall 2009

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Valid State Transition Diagrams

Step 1: State Transition Diagram •  Block diagram of desired system: Synchronizer unsynchronized user input

D Q

L=1

Edge Detector

D Q

L

Level to Pulse FSM

00

L=0

P

CLK

“if L=1 at the clock edge, then jump to state 01.”

L=0

L=1

L=1

00

01

Low input, Waiting for rise

P=0

Edge Detected!

L=0

P=1

6.111 Fall 2009

L=1

This is the output that results from this state. (Moore or Mealy?)

L=0

•  Often a starting state is specified •  Each state specifies values for all outputs (Moore) 5

6.111 Fall 2009

Lecture 5

Choosing State Representation

6

Step 2: Logic Derivation Transition diagram is readily converted to a state transition table (just a truth table)

Choice #1: binary encoding

L=1

L=1

For N states, use ceil(log2N) bits to encode the state with each state represented by a unique combination of the bits. Tradeoffs: most efficient use of state registers, but requires more complicated combinational logic to detect when in a particular state.

L=0

00

P=0

Edge Detected!

L=0

L=1

11

01

Low input, Waiting for rise

P=1

High input, Waiting for fall

P=0

L=0

Current State

In

S1 S0 0 0 0 0 0 1 0 1 1 1 1 1

L 0 1 0 1 0 1

Next State

S1 0 0 0 1 0 1

+

S0 0 1 0 1 0 1

Out +

P 0 0 1 1 0 0

•  Combinational logic may be derived using Karnaugh maps

Choice #2: “one-hot” encoding

S1S0 for S1 : 00 01 11 10 +

L

For N states, use N bits to encode the state where the bit corresponding to the current state is 1, all the others 0. Tradeoffs: more state registers, but often much less combinational logic since state decoding is trivial.

6.111 Fall 2009

L=0

L=1

P=0

•  So for each state: for any combination of input values there’s exactly one applicable arc

P=0

Lecture 5

P=1

•  Arcs leaving a state are collectively exhaustive, i.e., for any combination of input values there’s at least one applicable arc

11 11

L=0

“if L=0 at the clock edge, then stay in state 00.”

High input, Waiting for fall

Edge Detected!

•  Arcs leaving a state are mutually exclusive, i.e., for any combination input values there’s at most one applicable arc

Binary values of states

High input, Waiting for fall

11

01

Low input, Waiting for rise

P=0

•  State transition diagram is a useful FSM representation and design aid:

L=1

Lecture 5

0 0 0 0 X 1 0 1 1 X

for S0+:

S 1S 0 00 01 11 10 L

0 0 0 0 X 1 1 1 1 X 7

6.111 Fall 2009

L

Comb. Logic

S1+ = LS0 S 0+ = L

S+ n

D

Q

Comb. Logic

Registers

CLK

n

S

Lecture 5

P = S 1S 0

P S0

S1

for P:

0 1 0 0 X 1 1 0

8

Design of a Mealy Level-to-Pulse

Moore Level-to-Pulse Converter next state S+

inputs

Comb. Logic

x0...xn

direct combinational path!

Q

D

outputs yk = fk(S)

Comb. Logic

Registers

n CLK

Comb. Logic

n

S

•  Since outputs are determined by state and inputs, Mealy FSMs may need fewer states than Moore FSM implementations

P = S 1S 0

1. When L=1 and S=0, this output is asserted immediately and until the state transition occurs (or L changes).

Moore FSM circuit implementation of level-to-pulse converter: S0

L

CLK

+

D

S0

P

Q

CLK

D

S 1+

Q

Q Q

Comb. Logic

Q

D

Registers

n

present state S

S1+ = LS0 S 0+ = L

S+ n

L=0 | P=0

0

L P

L=1 | P=1

Input is low

2

Clock

1

Stat e

Input is high L=0 | P=0

S1

1

L=1 | P=0

Output transitions immediately. State transitions at the clock edge.

2. While in state S=1 and as long as L remains at 1, this output is asserted. 6.111 Fall 2009

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6.111 Fall 2009

Lecture 5

Mealy Level-to-Pulse Converter L=1 | P=1

0

Input is low

Pres. State

1

Input is high L=0 | P=0

L=0 | P=0

L=1 | P=0

Moore/Mealy Trade-Offs

In

Next State

Out

S

L

S+

P

0

0

0

0

0

1

1

1

1

0

0

0

1

1

1

0

•  How are they different?

–  Moore: outputs = f( state ) only –  Mealy outputs = f( state and input ) –  Mealy outputs generally occur one cycle earlier than a Moore: Moore: delayed assertion of P

Mealy FSM circuit implementation of level-to-pulse converter: L

S+ CLK

D

Q Q

S

P

S

•  FSM’s state simply remembers the previous value of L •  Circuit benefits from the Mealy FSM’s implicit single-cycle assertion of outputs during state transitions 6.111 Fall 2009

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Mealy: immediate assertion of P

L

L

P

P

Clock

Clock

State [0]

State

•  Compared to a Moore FSM, a Mealy FSM might... –  Be more difficult to conceptualize and design –  Have fewer states 11

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Example: Intersection Traffic Lights

FSM Example GOAL: Build an electronic combination lock with a reset button, two number buttons (0 and 1), and an unlock output. The combination should be 01011.

•  Design a controller for the traffic lights at the intersection of two streets – two sets of traffic lights, one for each of the streets. •  Step 1: Draw starting state transition diagram. Just handle the usual green-yellow-red cycle for both streets. How many states? Well, how many different combinations of the two sets of lights are needed? •  Step 2: add support for a walk button and walk lights to your state transition diagram. •  Step 3: add support for a traffic sensor for each of the streets – when the sensor detects traffic the green cycle for that street is extended.

RESET “0” “1”

STEPS: 1.  Design lock FSM (block diagram, state transitions) 2.  Write Verilog module(s) for FSM

Example to be worked collaboratively on the board…

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6.111 Fall 2009

Step 1A: Block Diagram

Button Enter Button 0 Button 1

fsm_clock

b0_in button b1_in

unlock reset

0

RESET Unlock = 0

Unlock LED

1

0

1 “0” Unlock = 0

1

“01” Unlock = 0 0

1 b0 state

button

14

RESET

fsm

reset button

Lecture 5

Step 1B: State transition diagram

lock Clock generator

UNLOCK

0

0

LED DISPLAY

“01011” Unlock = 1

1

“0101” Unlock = 0

1

“010” Unlock = 0

b1 0 6 states ! 3 bits

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Step 2: Write Verilog

Step 2A: Synchronize buttons // // // //

module lock(input clk,reset_in,b0_in,b1_in, output out); // synchronize push buttons, convert to pulses

module button( input clk,in, output out ); reg r1,r2,r3; always @(posedge begin r1