Digital logic families Digital logic has evolved over the years and this process has led to the development of a variety of families of digital logic integrated circuits. Each family has its own advantages and limitations. This document describes the main logic families and their characteristics. Among the technologies discussed here are DL, RTL, DTL, ECL, TTL, CMOS and BiCMOS. All of these technologies were developed in the 1950s/1960s and evolved over time. Some of these are still in use today.
Diode Logic (DL) Diode Logic (DL) is the most primitive of all the digital logic families. It is extremely simple and inexpensive because it only uses passive components. In fact, it combines diodes and resistors so sometimes it is known as Diode-Resistor Logic (DRL). Since DL does not use active components such as transistors, it does not provide amplification and therefore inversion is not available. For this reason, DL only provides AND and OR functions. Lack of amplification leads to signal degradation. This is due to the fact there is a voltage drop across diodes and to the fact that when diodes conduct, a voltage divider develops with the inputs. DL is an obsolete family, primarily due to its limitations in terms of inversion and degradation.
1
www.ice77.net
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0 OFFTIME = 200nS VB ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
D1 1 V
1N4376
D2 1 V
2 V
2
1N4376 R1 1k
0
DL implementation of the OR function
5.0V
2.5V
0V V(VA:1)
V(VB:1)
5.0V
(250.000n,4.2321) 2.5V
SEL>> 0V 0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(D2:K) Time
Waveforms for the OR function The circuit performs the correct logic but the voltage drop across the diode produces a considerably lower high output voltage (4.2321V).
2
www.ice77.net
V+
V+
V1 R1 5Vdc
1k
0
D1
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
2 V
1 V
1N4376 D2
OFFTIME = 200nS VB ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
2 V
1 1N4376
DL implementation of the AND function
5.0V
2.5V
0V V(VA:1)
V(VB:1)
5.0V
2.5V (150.000n,767.935m) SEL>> 0V 0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(D1:A) Time
Waveforms for the AND function The circuit performs the correct logic but the voltage drop across the diode produces a considerably higher low output voltage (767mV).
3
www.ice77.net
Resistor-Transistor Logic (RTL) Resistor-Transistor Logic (RTL) was invented around 1956. This type of technology, unlike DL, uses active devices such as transistors and therefore can provide inversion. The voltage range goes from 0V for low (0) to 3.5V for high (1). RTL is very inefficient because it dissipates a great amount of power through heat. RTL has two variants that attempt to improve some of its aspects: 1. When inputs are directly connected to the gate of the BJT, in order to save space and reduce fabrication costs, RTL is known as Direct-Coupled Transistor Logic (DCTL). 2. When capacitors are placed in parallel with input resistors, to speed up operation, RTL is known as Resistor-Capacitor Transistor Logic (RCTL). Fairchild Semiconductor introduced the first generation of RTL monolithic integrated circuits in either 1962 or 1963. RTL is an obsolete digital logic family.
4
www.ice77.net
0
V2 3.5Vdc R1 640
Q1
R2
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
V
V
40240
470
0
RTL implementation of the NOT function
5.0V
2.5V
0V V(VA:1) 4.0V
2.0V
SEL>> 0V 0s
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
V(R1:1) Time
Waveforms for the NOT function This circuit is nothing more than a common-emitter amplifier.
5
www.ice77.net
0
V3 3.5Vdc R1 640
R3
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
470
V
OFFTIME = 200nS VB ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
Q1
40240
R4 R2
470
V
V
470
0 V4 -1Vdc
0
RTL implementation of the NOR function The NOR function can be implemented by the circuit shown above which consists of parallel inputs, a single BJT and two separate power supplies. 5.0V
2.5V
SEL>> 0V V(VA:1)
V(VB:1)
4.0V
2.0V
0V 0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(Q1:c) Time
Waveforms for the NOR function
6
www.ice77.net
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
0
VA V
V3
OFFTIME = 200nS VB ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
3.5Vdc VB R1
V
640
R3
Q1
R4
VA
Q2
V
VB 40240
470
40240
470
0
RTL implementation of the NOR function (AGC) The NOR function can be implemented by the circuit shown above. Compared to the previous, this one has only one power supply but it has one BJT per input. The inputs are now isolated, an advantage over the previous circuit. This solution has been used in 1962 for the Apollo Guidance Computer which, during the Apollo Project, allowed astronauts to land on the Moon. 5.0V
2.5V
SEL>> 0V V(VA:1)
V(VB:1)
4.0V
2.0V
0V 0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(R1:1) Time
Waveforms for the NOR function
7
www.ice77.net
0
V1 3.5Vdc R3 640
V
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
OFFTIME = 200nS VB ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
Q1
R1
V
470
Q2
R2
V
40240
470
40240
0
RTL implementation of the NAND function The NAND function is implemented by the circuit shown above which consists of two parallel inputs, two stacked BJTs and a single power supply.
8
www.ice77.net
5.0V
2.5V
0V V(VA:1)
V(VB:1)
5.0V
(150.000n,3.9110) (50.000n,3.5000)
(250.000n,3.5000)
2.5V (350.000n,155.671m) SEL>> 0V 0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(R3:1) Time
Waveforms for the NAND function
9
www.ice77.net
Diode-Transistor Logic (DTL) Diode-Transistor Logic (DTL) was invented in the 1950s. It is a major improvement over DL and RTL because it eliminates signal degradation and reduces power dissipation by means of a transistor which restores digital values and a set of input diodes which replace input resistors. DTL has two variants that attempt to improve some of its aspects: 1. When a capacitor is placed in parallel with the base resistor and an inductor is placed in series with the collector resistor, DTL is known as Complemented Transistor Diode Logic (CTDL). 2. When a Zener diode and a single power supply are connected to the base of the transistor, DTL is known as High-Threshold Logic (HTL). Signetics introduced the first generation of DTL monolithic integrated circuits in 1962. DTL was used in the IBM 1401 decimal computer that was delivered in 1959.
10
www.ice77.net
0
V1 5Vdc
R2 R1
1k 4.7k V
D1
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
V
Q1
D2
D1N3902
D1N3902
MPS706
0
DTL implementation of the NOT function
5.0V
2.5V
0V V(VA:1)
5.0V
2.5V
SEL>> 0V 0s
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
V(R2:1) Time
Waveforms for the NOT function
11
www.ice77.net
0
V1 5Vdc
R2 4k D1
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
V
V
D1N3902
R3
V
MPS706
2k
D2
OFFTIME = 200nS VB ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
Q1
D1N3902 R1
0 2k
0
DTL implementation of the NOR function (I) The NOR function can be implemented by the circuit shown above. R3 is in the circuit to limit excess current from entering the base of the transistor but slows down the switching of the circuit. For this reason the NAND circuit is faster than this NOR circuit.
5.0V
2.5V
SEL>> 0V V(VA:1)
V(VB:1)
5.0V
2.5V
0V 0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(Q1:c) Time
Waveforms for the NOR function
12
www.ice77.net
0 0
0 V2
V1
V3
5Vdc 5Vdc
5Vdc R2 1k
R1
R3
4.7k
4.7k
V
Q2 OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
D1
D2
Q1
MPS706
D3
D4
VB CLK
V
D1N3902
D1N3902
D1N3902
MPS706
0
D1N3902
V
OFFTIME = 200nS ONTIME = 200nS DELAY = 0 STARTVAL = 1 OPPVAL = 0
0
DTL implementation of the NOR function (II) The NOR function can also be implemented by the circuit shown above. Essentially, this solution is a combination of two inverters. The one on the left is the mirror image of the one of the right. R2 is the common collector resistor. This NOR circuit is faster than the previous one. 5.0V
2.5V
0V V(VA:1)
V(VB:1)
5.0V
2.5V
SEL>> 0V 0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(Q2:c) Time
Waveforms for the NOR function By comparing the waveforms for the two NOR circuits, it should be clear that the transition from 00 to 01 is much faster in the second NOR implementation. Eliminating the base resistor speeds up the circuit considerably.
13
www.ice77.net
0
V1 5Vdc
R2
R1
1k
4.7k
D2
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
V
V
D1N3902
D1
V
MPS706
D1N3902
D3
OFFTIME = 200nS VB ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
Q1
D1N3902
0
DTL implementation of the NAND function The NAND function is implemented by the circuit shown above. D1 avoids the situation where one of the inputs is 0 and a sufficient voltage builds at the base of the transistor to turn in into conduction.
5.0V
2.5V
0V V(VA:1)
V(VB:1)
5.0V
2.5V
SEL>> 0V 0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(R2:1) Time
Waveforms for the NAND function
14
www.ice77.net
Emitter-Coupled Logic (ECL) Emittler-Coupled Logic (ECL) was invented in 1956 by Hannon S. Yourke at IBM. By using a differential amplifier, along with a specific range of input voltages, it is possible to overdrive BJTs so they never enter the saturation region. This type of situation allows extremely high speeds because overdriving avoids the diffusion time that affects the transistor when it transitions from the saturation region to the active region. ECL is fast but it requires a substantial amount of power which in turn produces high heat dissipation. In ECL technology, input impedance is high and output impedance is low. ECL uses only NPN transistors. ECL was originally known as Current-Steering Logic (CSL) because current can be steered to one side of the differential amplifier while the other side is practically shut off (typical feature of differential amplifiers). ECL is also known as Current-Mode Logic (CML) or Current-Switch Emitter-Follower logic (CSEF). When MOSFETs replace BJTs, ECL technology is know as Source-Coupled FET Logic (SCFL). Motorola introduced the first generation of ECL monolithic integrated circuits in 1962 and called it MECL I. Since then, ECL has been on the market and it’s still used today. VCC
Output
Input R1
R2 220
R3 245
907
Q5
PN2222 A+B
Q6
Q4
V
PN2222 -(A+B)
Q1
Q2
PN2222
Q3
PN2222
PN2222
V
R9
1k
D1
PN2222
D1N4003 D2
R10
VEE
1k
D1N4003 V
V
R4 50k
V1 = -0.8V V2 = -1.70V TD = 0 TR = 0 TF = 0 PW = 2us PER = 4us
R5
R7
R6 50k
779
R8 6.1k
VEE 4.98k
VA
VEE V1 = -0.8V V2 = -1.70V TD = 0 TR = 0 TF = 0 PW = 4us PER = 8us
0
VB
VCC VEE
VEE
Compensation
VCC
-5.2Vdc
0Vdc
0
0
0
Circuit schematic for the MECL 10K by Motorola
15
www.ice77.net
The circuit shown on the previous page can be divided into three sections: input, compensation and output. The input section has two inputs that are placed in parallel (VA and VB). The input range has an excursion of less than 1 V. It varies between –1.75V and –1.6V for a low signal (0) and between –0.9V and –0.75V for a high signal (1). The core of the circuit is the differential amplifier formed by Q1, Q2 and Q3. With a 0 or a 1 at the input, as previously explained, the differential amplifier is overdriven. One side is on and the other is off (one transistor draws all the current and starves the other transistor). The active side (Q1, Q2 or Q3) acts as a common-emitter stage with emitter degeneration which provides feedback and therefore additional stability. R6 acts as a current source that sinks the current from the active branch of the differential amplifier. The compensation section, formed by Q4, R7, R3, D1, D2 and R8, provides temperature and voltage compensation. Essentially, it interfaces input and output stages and locks the circuit in the desired voltage/current range. The output section is formed by Q5 and Q6. The upper power supply VCC is set to 0V. This is done to avoid variations in voltage from VCC (making it a ground is to set a stable point for the circuit). The lower power supply VEE is –5.2V. ECL can only provide the OR and NOR functions. -0.5V
-1.0V (5.0000u,-800.000m) (1.0000u,-1.7000) -1.5V SEL>> -2.0V V(Q1:b)
V(Q2:b)
-0.5V
(5.2000u,-698.580m)
-1.0V
(1.0000u,-1.6965) -1.5V
-2.0V 0s V(Q5:e)
1.0us V(Q6:e)
2.0us
3.0us
4.0us
5.0us
6.0us
7.0us
8.0us
Time
Waveforms for the OR/NOR functions ECL has two variants that attempt to improve some of its aspects: 1. When VCC=5V and VEE=0V, ECL is known as Positive Emitter-Coupled Logic (PECL). For both inputs and outputs, low logic (0) corresponds to 3.4V and high logic (1) corresponds to 4.2V. 2. When VCC is reduced to 3.3V, in order to reduce power, ECL is known as LowVoltage Positive Emitter-Coupled Logic (LVPECL). For output voltages, low logic (0) corresponds to 1.6V and high logic (1) corresponds to 2.4V. ECL was used in the IBM 7030 “Stretch” supercomputer that was delivered in 1961. 16
www.ice77.net
Transistor-Transistor Logic (TTL) Transistor-Transistor Logic (TTL) was invented in 1961 by James L. Buie at TRW. In an attempt to reduce the space utilized on a chip, TTL replaced DTL’s diodes with multipleemitter transistors. The result was a higher level of integration. TTL is also faster than DTL because it discharges the BE junction of the output transistor more quickly. Standard TTL chips works with a 5V power supply. For the inputs, the low logic signal (0) should be between 0V and 0.8V and the high logic signal (1) should be between 2V and 5V. For the outputs, the low logic signal (0) stays between 0V and 0.5V the high logic signal (1) corresponds to values between 2.7V and 5V.
TTL input and output Sylvania introduced the first generation of TTL monolithic integrated circuits in 1963. Since then, TTL has evolved and newer generations have been designed to speed up the technology as well as to reduce power consumption. From 1964 to 2004, different generations of TTL technologies have been invented: L (low-power) and H (high-speed) came in 1964, S (Schottky) in 1969, LS (low-power Schottky) and ALS (advanced low-power Schottky) in 1976?, F (fast) in 1979, AS (advanced Schottky) in 1980? and G in 20041. TTL has been on the market for a long time. It was assigned the 5400, 6400 and 7400 codes. Texas Instruments invented the 5400 line for military applications. The 7400 family was designed for the regular market and became very popular, particularly in the 70s and the 80s, at least until the advent of Very-Large Scale Integrated (VLSI) circuits. The 6400 series did not have a great success and it was a transitional series between 5400 and 7400 in terms of temperature ranges.
1
According to Wikipedia, ALS was born either in 1976, 1980 or 1985 and AS was born either in 1980 or 1985.
17
www.ice77.net
0
V2 5Vdc
R2
R1
4.7k
1k MPSW43 Q1
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
Q2
V
MPSW43
V
0
TTL implementation of the NOT function The NOT function is implemented by the circuit shown above. This circuit is very similar to its DTL counterpart. Notice that the two diodes are replaced by an NPN transistor in the np/pn sequence. 5.0V
2.5V
SEL>> 0V V(VA:1) 5.0V
2.5V
0V 0s
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
V(R2:1) Time
Waveforms for the NOT function
18
www.ice77.net
0 0
0 V2
V1
V3
5Vdc 5Vdc
5Vdc R2 1k
R1
R3
4.7k
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
Q3
4.7k
V
Q1
Q2
Q4
VB CLK
V
MPS706
MPS706
MPS706
0
MPS706
V
OFFTIME = 200nS ONTIME = 200nS DELAY = 0 STARTVAL = 1 OPPVAL = 0
0
TTL implementation of the NOR function The NOR function is implemented by the circuit shown above. This circuit is very similar to its DTL counterpart (diodes are replaced by transistors). 5.0V
2.5V
0V V(VA:1)
V(Q4:e)
5.0V
2.5V
SEL>> 0V 0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(R2:1) Time
Waveforms for the NOR function
19
www.ice77.net
0
V3 5Vdc
R4
R2 R1
130
1.6k
Q4
4k
MPS706
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0 OFFTIME = 200nS VB ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
Q1
Q3
D1 MR504
MPS706
V
MPS706
Q2
Q5
V
MPS706 V
MPS706
R3 1k
0 0
TTL implementation of the NAND function The NAND function is implemented by the circuit shown above. When the output of the circuit goes to logic 1, the chip offers high resistance at the collector of Q3 and this is undesirable because this situation lowers the fanout (the ability to connect many gates at the output without overloading the circuit). To overcome this deficiency, the totem-pole was invented. Although the solution is not optimal, the output is not symmetrical, it is a reasonable way to go about the high resistance problem. The totem-pole consists of a few additional components: 2 resistors (R3 and R4), 2 transistors (Q4 and Q5) and a diode (D1). The totem-pole is added to the right of what looks like a two-input inverter and it helps to overcome the high output resistance previously mentioned.
20
www.ice77.net
5.0V
2.5V
0V V(VA:1)
V(VB:1)
5.0V
2.5V
SEL>> 0V 0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(D1:2) Time
Waveforms for the NAND function
21
www.ice77.net
Complementary Metal-Oxide Semiconductor (CMOS) Complementary Metal-Oxide Semiconductor (CMOS) was invented in 1963 by Frank Wanlass at Fairchild semiconductor. This type of technology introduced a new design approach that completely revolutionized the electronics industry: n and p transistors are dual to each other and that they can be combined to provide logic by reducing power consumption (as opposed to previous technologies where only one type of transistor was used). When compared to older technologies, CMOS drastically reduces power consumption and heat dissipation. CMOS, in fact, consumes power only during changes between logic states, thus only when both transistors are simultaneously active and conduct current. Power dissipated is a function of four variables and it’s described by P=αCV2f where α is the so-called activity factor, C is capacitance, V is voltage and f is frequency (the activity factor is a number between 0 and 1 that describes how busy is a CMOS device). CMOS technology became the leading technology for VLSI circuits because it could be highly integrated. As a result, microprocessors and microcontrollers are now made of CMOS devices. CMOS devices have speed limitations due to internal capacitance which slows down their operation. CMOS is sensitive to electrostatic discharge or ESD so when handling CMOS devices, additional care needs to be used to avoid damage. CMOS can operate at different power supply voltages ranging from 3V to 15V. Just like TTL, which became popular with the 7400 family, CMOS has become famous with the 4000 family. RCA introduced the first generation of CMOS monolithic integrated circuits either in 1968 or in 1970.
22
www.ice77.net
23
www.ice77.net
24
www.ice77.net
Static circuits Static circuits do not use any external clock. 0
V1 5Vdc M2
IRFP9141
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
V
V
M1
IRFP253
0
Static CMOS implementation of the NOT function The NOT function is implemented by the circuit shown above. This circuit shows the symmetry and the duality of CMOS technology. The two transistors are complementary and they are mirror images of each other. 5.0V
4.0V
2.0V
0V 0s V(VA:1)
20ns 40ns V(M1:d)
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
Time
Waveforms for the NOT function The transistors are modeled with the following parameters: Wp=100µ, Lp=2µ, Vtpo=-0.7V, Cbdp=2.293pF, Cgspo=818.1pF, Cgdpo=511.3pF Wn=100µ, Ln=2µ, Vtno=+0.7V, Cbdn=4.368pF, Cgsno=1.329pF, Cgdno=496pF 25
www.ice77.net
0
V1 5Vdc
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
M3 VA IRFP9141
VA V
OFFTIME = 200nS VB ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
VB V
M4 VB IRFP9141
M1
V
M2
VA
VB IRFP253
IRFP253
0
Static CMOS implementation of the NOR function The NOR function is implemented by the circuit shown above. This circuit shows the duality of CMOS technology. N transistors are complementary to P transistors (N in parallel and P in series). For static CMOS circuits, for n NMOS transistors, there is an equal number of PMOS transistors. 5.0V
2.5V
0V V(VA)
V(VB)
5.0V
2.5V
SEL>> 0V 0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(M1:d) Time
Waveforms for the NOR function The transistors are modeled with the following parameters: Wp=100µ, Lp=2µ, Vtpo=-0.7V, Cbdp=2.293pF, Cgspo=818.1pF, Cgdpo=511.3pF Wn=100µ, Ln=2µ, Vtno=+0.7V, Cbdn=4.368pF, Cgsno=1.329pF, Cgdno=496pF
26
www.ice77.net
0
V1 5Vdc
M3
M4
VA
VB IRFP9141
IRFP9141
V
M1 VA IRFP253
M2 VB IRFP253
OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
VA V
OFFTIME = 200nS VB ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
VB V
0
Static CMOS implementation of the NAND function The NAND function is implemented by the circuit shown above. This circuit shows the duality of CMOS technology. N transistors are complementary to P transistors (N in series and P in parallel). For static CMOS circuits, for n NMOS transistors, there is an equal number of PMOS transistors. 5.0V
2.5V
0V V(VA)
V(VB)
5.0V
2.5V
SEL>> 0V 0s
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
V(M4:d) Time
Waveforms for the NAND function The transistors are modeled with the following parameters: Wp=100µ, Lp=2µ, Vtpo=-0.7V, Cbdp=2.293pF, Cgspo=818.1pF, Cgdpo=511.3pF Wn=100µ, Ln=2µ, Vtno=+0.7V, Cbdn=4.368pF, Cgsno=1.329pF, Cgdno=496pF 27
www.ice77.net
Complementary Pass-Transistor Logic (CPL) is a CMOS subclass that uses NMOS transistors to provide the logic. It’s generally faster than standard CMOS circuits because eliminating PMOS transistors leads to a reduction in capacitance within the circuit. CPL needs complements of all inputs and provides complements of the implemented functions. V+ OFFTIME = 100nS DSTM1 ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
VA1
VB0
V
U1A 1
2
M1
VA0
M3
M2N6659
VA1 M2N6845
74F04 U3A
OFFTIME = 200nS DSTM2 ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
VB1
VB1
V
U2A 1
2
1 M2
VB0
M2N6659
2 V
NOR
V
OR
74F04
VB1 V+
74F04
VB0 V+
M4
M2N6659
M6
VA0 M2N6845
V1
U4A
3.3Vdc 1
VB0
0
M5
M2N6659
2
74F04
VB1
CPL implementation of NOR/OR functions 5.0V
2.5V
SEL>> 0V V(VA1)
V(VB1)
4.0V
2.0V
0V 0s V(M3:g)
50ns V(M6:g)
100ns
150ns
200ns
250ns
300ns
350ns
400ns
Time
Waveforms for the NOR/OR functions The transistors are modeled with the following parameters: Wp=2µ, Lp=100n, Vtpo=-0.3V, Cbdp=899.2fF, Cgspo=2.288fF, Cgdpo=138.5fF Wn=100m, Ln=100n, Vtno=+0.3V, Cbdn=118fF, Cgsno=1.885fF, Cgdno=7.564fF
28
www.ice77.net
Cascode Voltage Switch Logic (CVSL) is a CMOS subclass that uses NMOS transistors to provide the logic. It’s generally faster than standard CMOS circuits because eliminating PMOS transistors leads to a reduction in capacitance within the circuit. CVSL needs complements of all inputs and provides complements of the implemented functions. 0
0
V1
V2
3.3Vdc
OFFTIME = 100nS DSTM1 ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
3.3Vdc
M5
M6
VA1 V
U1A
IRFF9110 1
2
IRFF9110
VA0 NOR
OR
74F04 V
OFFTIME = 200nS DSTM2 ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
V
VB1
M3
V
U2A
VA0
1
2
VB0
IRFF110 M1
74F04
M2
VA1
VB1
IRFF110
IRFF110
M4 VB0 IRFF110
0
0
Static CVSL implementation of NOR/OR functions 5.0V
2.5V
0V V(VA1)
V(VB1)
4.0V
2.0V
SEL>> 0V 0s V(M6:d)
50ns V(M2:d)
100ns
150ns
200ns
250ns
300ns
350ns
400ns
Time
Waveforms for the NOR/OR functions The transistors are modeled with the following parameters: Wp=10µ, Lp=1µ, Vtpo=-0.5V, Cbdp=324.9fF, Cgspo=2.397fF, Cgdpo=306.4fF Wn=1m, Ln=1µ, Vtno=+0.5V, Cbdn=377.8fF, Cgsno=739.4fF, Cgdno=82.14fF 30
www.ice77.net
0
0
V1
V2
3.3Vdc
3.3Vdc
M5
OFFTIME = 100nS DSTM1 ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
M6
VA1 V
U1A
IRFF9110 1
2
IRFF9110
VA0 NOR
AND
74F04 V
OFFTIME = 200nS DSTM2 ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
V
VB1 M1
V
U2A 1
2
VA1 VB0
M3
IRFF110
M4
VA0
74F04
VB0
IRFF110
M2
IRFF110
VB1 IRFF110
0
0
Static CVSL implementation of NAND/AND functions 5.0V
2.5V
0V V(VA1)
V(VB1)
4.0V
2.0V
SEL>> 0V 0s V(M4:d)
50ns V(M5:d)
100ns
150ns
200ns
250ns
300ns
350ns
400ns
Time
Waveforms for the NAND/AND functions The transistors are modeled with the following parameters: Wp=10µ, Lp=1µ, Vtpo=-0.5V, Cbdp=324.9fF, Cgspo=2.397fF, Cgdpo=306.4fF Wn=1m, Ln=1µ, Vtno=+0.5V, Cbdn=377.8fF, Cgsno=739.4fF, Cgdno=82.14fF
31
www.ice77.net
Dynamic circuits Dynamic circuits use external clocks. V+ OFFTIME = 200nS DSTM1 ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
VA1
VB0 pr0A
V
U1A 1
2
M1
VA0
pr0B
M2N6659 CLK
VA1
M2N6845
M2N6845
74F04 U3A
OFFTIME = 400nS DSTM2 ONTIME = 400nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
eV1A
VB1 V
U2A 1
2
M2N6659
1
VB1 M2
VB0
M2N6659
V
NOR
V
OR
74F04
VB1 V+
74F04 OFFTIME = 100nS CLK ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
2
CLK
CLK VB0
V
M3
pr0C
M2N6659
pr0D
CLK
VA0 V+
M2N6845
M2N6845
U4A V1
eV1B
M2N6659 1
VB0
2
CLK
3.3Vdc M4
M2N6659
74F04
VB1
0
Dynamic CPL implementation of the NOR/OR function 5.0V
2.5V
0V V(VA1)
V(VB1)
5.0V
2.5V
SEL>> 0V 0s V(U3A:Y)
100ns V(U4A:Y)
200ns V(CLK)
300ns
400ns
500ns
600ns
700ns
800ns
Time
Waveforms for the NOR/OR functions The transistors are modeled with the following parameters: Wp=2µ, Lp=100n, Vtpo=-0.3V, Cbdp=899.2fF, Cgspo=2.288fF, Cgdpo=138.5fF Wn=100m, Ln=100n, Vtno=+0.3V, Cbdn=118fF, Cgsno=1.885fF, Cgdno=7.564fF The PMOS transistor (pr0B) is called the weak-keeper. It is small in size and it helps to avoid output voltage degradation.
32
www.ice77.net
0
0
V1
V2
3.3Vdc
3.3Vdc
CLK M5
OFFTIME = 200nS DSTM1 ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
M6 pr0
VA1 V
U1A 1
2
IRFF9110
IRFF9110
VA0 NOR
OR
74F04 V
OFFTIME = 400nS DSTM2 ONTIME = 400nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
VA0
V
U2A 1
V
M3
VB1
2
M1 VB0
M2
VA1 IRFF110
74F04
IRFF110 VB1 M4
IRFF110 VB0
IRFF110
OFFTIME = 100nS CLK ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
CLK V
eV1 CLK IRFF110
0
Dynamic CVSL implementation of NOR/OR functions 5.0V
2.5V
SEL>> 0V V(VA1)
V(VB1)
V(CLK)
100ns V(M3:d)
5.0V
2.5V
0V 0s
200ns V(M2:d)
300ns
400ns
500ns
600ns
700ns
800ns
Time
Waveforms for the NOR/OR functions The transistors are modeled with the following parameters: Wp=500µ, Lp=100n, Vtpo=-0.5V, Cbdp=324.9pF, Cgspo=2.397pF, Cgdpo=306.4pF Wn=1m, Ln=1µ, Vtno=+0.5V, Cbdn=377.8fF, Cgsno=739.4fF, Cgdno=82.14pF
34
www.ice77.net
0
0
V1
V2
3.3Vdc
OFFTIME = 200nS DSTM1 ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
3.3Vdc
CLK M5
M6 pr0
VA1 V
U1A 1
2
IRFF9110
IRFF9110
VA0 NAND
AND
74F04 V
OFFTIME = 400nS DSTM2 ONTIME = 400nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
V
U2A 1
2
V
M1
VB1 VA1
M3
IRFF110
VB0
M4
VA0 M2
74F04
VB0
IRFF110
IRFF110
VB1 IRFF110
OFFTIME = 100nS CLK ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
CLK V
eV1 CLK IRFF110
0
Dynamic CVSL implementation of NAND/AND functions 5.0V
2.5V
SEL>> 0V V(VA1)
V(VB1)
V(CLK)
100ns V(M3:d)
5.0V
2.5V
0V 0s
200ns V(M5:d)
300ns
400ns
500ns
600ns
700ns
800ns
Time
Waveforms for the NAND/AND functions The transistors are modeled with the following parameters: Wp=500µ, Lp=100n, Vtpo=-0.5V, Cbdp=324.9pF, Cgspo=2.397pF, Cgdpo=306.4pF Wn=1m, Ln=1µ, Vtno=+0.5V, Cbdn=377.8fF, Cgsno=739.4fF, Cgdno=82.14pF
35
www.ice77.net
Domino Logic is a CMOS subclass that uses NMOS transistors to provide the logic. It’s generally faster than standard CMOS circuits because eliminating PMOS transistors leads to a reduction in capacitance within the circuit. When the clocks is 0 (precharge phase), pr0 charges the node below it to 1. When the clock is 1 (evaluation phase), NMOS transistors provide the logic to the output. The clock signal can also be split and two separate clocks can be supplied to the circuit. Sometimes, these two signals overlap. Domino does not need complements of all inputs. 0
V1 3.3Vdc wk
pr0 OFFTIME = 200nS VA ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
IRFU9010
VA IRFP9141
V
U1A
OFFTIME = 400nS VB ONTIME = 400nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
1
VB M1
CLK
VA
CLK
V
M2 VB IRFP253
OFFTIME = 100nS CLK ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
2 74F04
V
IRFP253
eV1
V
IRFP253
0
Domino implementation of the OR function 5.0V
2.5V
SEL>> 0V V(VA)
V(VB)
5.0V
2.5V
0V 0s V(CLK)
100ns V(U1A:Y)
200ns
300ns
400ns
500ns
600ns
700ns
800ns
Time
Waveforms for the OR function The transistors are modeled with the following parameters: Wp=1m, Lp=1µ, Vtpo=-0.3V, Cbdp=2.293fF, Cgspo=818.1fF, Cgdpo=5.113fF Wn=1m, Ln=1µ, Vtno=+0.3V, Cbdn=4.368fF, Cgsno=1.329fF, Cgdno=4.96fF PMOS transistor IRFU9010 acts as a weak-keeper. It is small in size (1/10 of NMOS) and it helps to avoid output voltage degradation.
36
www.ice77.net
0
V1 3.3Vdc pr0 OFFTIME = 200nS VA ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0 OFFTIME = 400nS VB ONTIME = 400nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
VA
wk
IRFP9141
IRFF9233
U1A
V
1 M2
VB V
2 74F04
V
VB IRFP253
CLK M1 OFFTIME = 100nS CLK ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
CLK
VA IRFP253
V
eV1
IRFP253
0
Dynamic CMOS implementation of the AND function 5.0V
2.5V
0V V(VA)
V(VB)
5.0V
2.5V
SEL>> 0V 0s V(CLK)
100ns V(U1A:Y)
200ns
300ns
400ns
500ns
600ns
700ns
800ns
Time
Waveforms for the AND function The transistors are modeled with the following parameters: Wp=1m, Lp=1µ, Vtpo=-0.3V, Cbdp=2.293fF, Cgspo=818.1fF, Cgdpo=5.113fF Wn=1m, Ln=1µ, Vtno=+0.3V, Cbdn=4.368fF, Cgsno=1.329fF, Cgdno=4.96fF PMOS transistor IRFF9233 acts as a weak-keeper. It is small in size (1/10 of NMOS) and it helps to avoid output voltage degradation.
37
www.ice77.net
Bipolar-CMOS (BiCMOS) Bipolar-CMOS (BiCMOS) was invented in 1969. This type of technology is hybrid in nature because it combines bipolar transistors (BJTs) to field effect transistors (MOSFETs) in order to combine the advantages of both devices. The BJT has low output resistance, high switching speed and high voltage gain. The MOSFET exhibits high input impedance and low power consumption. BiCMOS has also some disadvantages that prevent this type of technology from becoming popular. Since BJTs are much bigger than CMOS circuits, it is virtually impossible to fabricate integrated circuits at competitive prices because their fabrication would require additional steps and therefore additional costs. BiCMOS has also higher power consumption than CMOS so BiCMOS is not particularly appealing when saving energy is an issue. The circuit can be divided in two stages: the input stage consists of CMOS transistors whereas the output stage is made by BJT transistors.
38
www.ice77.net
VCC
VCC
M4 OFFTIME = 100nS DSTM1 ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
V
IRFP9140
Q1
Q2N4141 M1
IRFP462
0 VCC V
M2 V1 IRFP462
5Vdc
0
Q2
M3
Q2N4141
IRFP462
0
0
BiCMOS implementation of the NOT function 6.0V (45.000n,4.5129)
4.0V
2.0V
(150.000n,-265.399m) 0V
-2.0V 0s
20ns V(DSTM1:1)
40ns V(M2:d)
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
Time
Waveforms for the NOT function The transistors are modeled with the following parameters: Wp=1µ, Lp=45n, Vtpo=-0.5V, Cbdp=2.293fF, Cgspo=1.038pF, Cgdpo=291.9fF Wn=1µ, Ln=45n, Vtno=+0.5V, Cbdn=5.156fF, Cgsno=1.947pF, Cgdno=135.8fF 39
www.ice77.net
VCC
VCC
M6
IRFP9140
M7 OFFTIME = 100nS DSTM1 ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
OFFTIME = 200nS DSTM2 ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
VA
VA
IRFP9140
V
M1
Q2N4141
M2
VB V
IRFP462
IRFP462
0
0
M3 VB
V
M4 VA
IRFP462
VCC
Q1
IRFP462
Q2
Q2N4141
M5
V1 5Vdc
IRFP462
0 0
0
BiCMOS implementation of the NOR function 6.0V (40.000n,4.4887)
4.0V
2.0V
(320.000n,-257.165m) 0V
-2.0V 0s
50ns 100ns V(DSTM1:1) V(DSTM2:1) V(Q1:e)
150ns
200ns
250ns
300ns
350ns
400ns
Time
Waveforms for the NOR function The transistors are modeled with the following parameters: Wp=1µ, Lp=45n, Vtpo=-0.5V, Cbdp=2.293fF, Cgspo=1.038pF, Cgdpo=291.9fF Wn=1µ, Ln=45n, Vtno=+0.5V, Cbdn=5.156fF, Cgsno=1.947pF, Cgdno=135.8fF 40
www.ice77.net
VCC
VCC
M7
VCC
M6
VA
VB
IRFP9140
IRFP9140
M1 OFFTIME = 100nS DSTM1 ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
VA
VA
IRFP462
V
Q1
M2 OFFTIME = 200nS DSTM2 ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 OPPVAL = 0
Q2N4141
VB
VB
IRFP462
V
0
V
M3 VB IRFP462
VCC
M4 V1
VA IRFP462
5Vdc
0
Q2
Q2N4141
M5
IRFP462
0
0
BiCMOS implementation of the NAND function 6.0V (40.000n,4.5323)
4.0V
2.0V
(340.000n,-258.443m) 0V
-2.0V 0s
50ns 100ns V(DSTM1:1) V(DSTM2:1) V(Q1:e)
150ns
200ns
250ns
300ns
350ns
400ns
Time
Waveforms for the NAND function The transistors are modeled with the following parameters: Wp=1µ, Lp=45n, Vtpo=-0.5V, Cbdp=2.293fF, Cgspo=1.038pF, Cgdpo=291.9fF Wn=1µ, Ln=45n, Vtno=+0.5V, Cbdn=5.156fF, Cgsno=1.947pF, Cgdno=135.8fF
41
www.ice77.net
