DIGITAL LOGIC & STATE MACHINE DESIGN

SPRING 2014

HOMEWORK VI DUE : May 1, 2014 READ : Related portions of Chapters IV, VI, VII, VIII and IX ASSIGNMENT : There are thirteen questions. Solve all homework and exam problems as shown in class and past exam solutions.

1) Consider the following sequential circuit : y1 x

seq. circuit

D z

y0

clock

y1

Q

x

y1 clock

C

y0 Q

y0

D

y1

Q

y0 clock

C

y1

z

y0

Q y0

Analyze the sequential circuit in the style shown in class. This question is identical to textbook problem 7.12 except that FF y2 is renamed y0. Note that this circuit does not seem to have a purpose. Nevertheless, do a timing analysis and write that there is no purpose. Note also that this is a Moore circuit since the only sequential circuit output, z, is not a function of input x. Also, this is a non-finite memory circuit since the FFs do not form a shift register.

2) Consider the following sequential circuit : x

seq. circuit

z1

x

J

clock

z0

z1

x

y1

clock

C x

Q

x

clock

y1 Q

K

y0

y1

y1

y0

J

Q

z0 y0

C Q K

y0

Analyze the sequential circuit in the style shown in class. Since FF y1 output is sequential circuit output z1 and FF y0 output is sequential circuit output z0, this circuit is also a Moore circuit : The sequential circuit outputs, z1 and z0, are not a function of input x. Finally, this is a non-finite memory circuit since the FFs do not form a shift register. NYU School of Engineering

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Handout No : 18

April 17, 2014

3) Consider the following sequential circuit : x1

msb z1

Most significant FF

Y x0

Q y1

z0 Q

x1 y0

x0 Q

C

clock

x1 x0 y0

x1

x1 y0

T

clock z1

x0

Q

T x1

C x0

x0

z0 clock

Analyze the sequential circuit in the style shown in class. Note that there are 2 (two) inputs hence there are four sets of next state columns. Is this sequential circuit a Moore or Mealy circuit ? Why ?

4) Consider the following 1-input, 1-output sequential circuit : The input/output relationship of the sequential circuit is that the circuit checks for three successive 1s. x clock

z

After receiving three 1s in a row, the following clock period, it outputs a 1 for two clock periods. Then, it starts checking for three 1s again. Hence, its cycle of checking bits is 5 clock periods. If it does not receive a 1 when it is waiting for a 1, the next clock period, it starts checking for three 1s again.

Obtain the state diagram and the state table of this sequential circuit as discussed in class. Is this a finite memory or non-finite memory sequential circuit ? Why ?

5) Solve Problem 4.14 (d). Draw by hand the corresponding 2-level AND-OR gate network, assuming that single-rail inputs are available. Determine the TTL LS SSI chip usage for the case of developing a new PCB. That is, which TTL LS SSI chips are used, the number of chips used for each kind and the number of unused SSI gates for this 2-level AND-OR gate network. You will point out the distinguished 1-cell(s). Do that by giving their minterm numbers as done in class. Remember also to state whether a term is an essential prime implicant or a secondary essential prime implicant or a prime implicant.

6) By using the minterm list in Problem 4.14 (d), obtain the minimal product-of-sums expression. Draw by hand the corresponding 2-level OR-AND gate network, assuming that single-rail inputs are available. Determine the TTL LS SSI chip usage for the case of developing a new PCB. NYU School of Engineering

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Handout No : 18

April 17, 2014

You will point out the distinguished 0-cell(s). Do that by giving their maxterm numbers. Remember also to state whether a term is an essential prime implicant or a secondary essential prime implicant or a prime implicant.

7) Solve Problem 4.18 (d). Draw by hand the minimal 2-level NAND-NAND gate network, assuming that single-rail inputs are available. Determine the TTL LS SSI chip usage for the case of developing a new PCB. You will not use the method given in Section 4.3.6 in the textbook. You will point out the distinguished 1-cell(s). Do that by giving their minterm numbers. Note that all the don’t cares need not be covered. Remember also to state whether a term is an essential prime implicant or a secondary essential prime implicant or a prime implicant.

8) Consider the following minimal SOP expression : f(a, b, c, d) = bd + b d i) Draw the corresponding 2-level AND-OR gate network, assuming that single-rail inputs are available. Determine the TTL LS SSI chip usage for the case of developing a new PCB. That is, which TTL LS SSI chips are used, the number of chips used for each kind and the number of unused SSI gates. ii) Draw the corresponding 2-level NAND-NAND gate network, assuming that single-rail inputs are available. Determine the TTL LS SSI chip usage for the case of developing a new PCB. iii) The 2-level minimal AND-OR and NAND-NAND circuits require more than one chip each. However, a close analysis of the minimal circuit indicates that only one TTL SSI chip is enough to implement the minimal circuit. Draw that circuit by hand. To determine which chip it is, you can check TTL manuals, such as the On Semiconductor manual or the Motorola manual.

9) Consider Problem 1 on page 1 of this homework that analyzes a sequential circuit. Assuming that single-rail inputs are available, determine the TTL LS SSI chip usage for the case of developing a new PCB.

10) Consider the following combinational circuit that converts a Hexadecimal digit to the 7-Segment format : Hex digit

K (p, q, r, s)

4

Hex-to-7-Segment Converter

7

S (a, b, c, d, e, f, g)

The converter outputs (S) are active-low. Implement the circuit by using generic 16x4-bit ROM chips whose black-box view is as follows : NYU School of Engineering

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April 17, 2014

msb

A0 A1 A2 A3 E

Q0 Q1 Q2 Q3

msb

Note that this is what is implemented in Block 2 of the Term Project, except that the Xilinx ROMs do not have Enable inputs and have only one bit per location. Write down the minterm lists of the outputs. Draw the circuit containing ROM chips and clearly indicate what is connected to the inputs and outputs of the ROM chips. Then, show the content of each ROM in terms of bits as done in class. Finally, write down the number of unused ROM bits. 11) Solve Problem 9.1 of Chapter IX, by working on figure 6-37 only (not Exercise 6.31 nor figures 6.73, 6.93, X6.44). In addition, apply Problem 9.1 on the three minterm lists given on page 222 of the Wakerly book. The circuit has three inputs (X, Y, Z) and three outputs (F, G, H). Overall, Problem 9.1 wants you to assume that there is a generic matching ROM chip (not a commercial chip nor a Xilinx ROM) that exactly fits each implementation. Therefore, the number of unused bits is 0. For this problem, there are two circuits to work on and for each circuit : i) Draw the black box view of the circuit showing its inputs and outputs, ii) State the number of ROM address inputs, the number of ROM data outputs, the ROM size (specified as k x m-bit) and the total number of bits the ROM has and finally, iii) For the circuit on page 222, show how the ROM is programmed, i.e. show the ROM content as discussed in class.

12) Consider the 10-to-4 Encoder designed in Question 2 of Homework V where you obtain the minimal expressions for all five (5) outputs of the encoder. Now, implement this encoder by using a single PLS 100 PLA chip whose description handout is given in class. No external (offthe-chip) connections nor external gates (no other chip) can be used. In order to help grade your answer, write down the five expressions you implement.

13) Implement two independent Full-Adder circuits (not connected to each other) by using a single Monolithic Memories 12H6 PAL chip whose description handout is given in class. You may use off-the-chip (external) connections, but no external gate (no other chip) can be used.

NYU School of Engineering

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Handout No : 18

April 17, 2014

RELEVANT QUESTIONS AND ANSWERS Q1) Consider the following sequential circuit : x

x x

J

y0 seq. circuit

clock

z1

K

z1

Q

C

clock

z0

y1 Q

Most Significant FF

x y1 x

y0

D

y0 x

clock

y0

z0

Q Q

C

Analyze the sequential circuit in the style shown in class. Is this circuit is a Mealy or Moore circuit ? Why ? FF y1 is the most significant FF. The FF y1 output is sequential circuit output z1 and the FF y0 output is sequential circuit output z0.

A1) a) Flip-flop input and sequential circuit output equations : J1 = x y 0

D 0 = x y1 + x y 0 + x y0

z1 = y1

K 1 = x y0

z0 = y0

Since sequential circuit outputs z1 and z0 do not depend on x, this is a Moore circuit.

b) Next flip-flip output (next state) equations : y1 = J1y1 + K1y1 = (x y0)y1 + (x y0)y1

y0 = D0 = x y1 + x y0 + x y0

= x y1 y0 + [(x + y0)]y1

y1y0

y1 x=0

y0 x =1

z1 z0 x=0 x=1

00

01

00

00

00

01

10

01

01

01

10

11

10

10

10

11

01

11

11

11

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Page 5 of 60

d) The state table :

c) The excitation table :

= x y1 y0 + x y1 + y1 y0

CS2204

PS

NS

OUT

x=0

x=1

q0

q1

q0

0

q1

q2

q1

1

q2

q3

q2

2

q3

q1

q3

3

Handout No : 18

April 17, 2014

f) The functional description :

e) The state diagram :

(i) Timing analysis :

Reset state

q0/0

1

0

0

q3/3

1

Time x PS OUT

q1/1

0

1

t0 t1 t2 t3 t4 t5 1 0 0 0 1 0 q0 q0 q1 q2 q3 q3 0 0 1 2 3 3

t6 t7 t8 ... 0 0 0 .... q1 q2 q3 .... 1 2 3 ....

0

(ii) The Purpose : It is a 2-bit binary (modulo-3, divide-by-3) up counter. It starts with zero and then counts as 1, 2, 3, 1,...

1

It counts up by one when x is 0 : 0, 1, 2, 3, 1, 2, 3,..

q2/2

The count does not change when x is 1.

Q2) Consider the sequential circuit below with two inputs and one output.

Its transition table (excitation table) is also given. Continue the analysis. The labeling of FFs is the opposite of our convention, but, we will keep it :

x2

z

y1 y2

x1 seq circuit

z

clock

y1y2

x1x2=00

x1x2=01

x1x2=10

x1x2=11

x1x2=00

x1x2=01

x1x2=10

x1x2=11

00

00

01

10

11

1

0

0

1

01

00

01

10

11

0

0

0

0

10

00

01

10

11

0

0

0

0

11

00

01

10

11

1

0

0

1

A2) Note that the transition table indicates that this is a Mealy circuit, since output (z) columns are not identical, i.e. the output z depends on the values of inputs x1 and x2. Also, this is a finite-input memory circuit where the inputs one clock period earlier are remembered. d) The state table is obtained directly from the excitation table :

OUT

NS y1y2

x1x2=00

x1x2=01

x1x2=10

x1x2=11

x1x2=00

x1x2=01

x1x2=10

x1x2=11

a

a

b

c

d

1

0

0

1

b

a

b

c

d

0

0

0

0

c

a

b

c

d

0

0

0

0

d

a

b

c

d

1

0

0

1

e) The state diagram : NYU School of Engineering

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Handout No : 18

April 17, 2014

00/1 a 01/0 00/1 11/1

00/0

10/0

11/1

11/0

d

b

01/0 00/0 11/0

10/0

01/0

01/0 10/0

c 10/0 f) The functional description : (ii) The purpose : the circuit outputs a 1, if for two successive clock periods x1=x2. The output is 1 for one clock period when it detects that the inputs are equal to each other the second time.

(i) Timing analysis : assume that the following arbitrary input sequence is given to the sequential circuit :

10 00 11 01 10 11 00 00

x1x2

time

For example, on the left x1=x2=0 at t1 and x1=x2=1 at t2. Two consecutive clock periods they are equal to each other, thus output z is raised to 1 at t2, for one clock period. Overlapping of successive checkings is allowed. For example, at t5, t6 and t7 the inputs are equal to each other, thus, the output is 1 at t6 since x1=x2 at t5 and t6 and again 1 at t7, as x1=x2 at t6 and t7.

Assume also that the initial state is “a.” Then : Time x1x2 PS OUT

t0 t1 t2 t3 t4 t5 t6 t7..... 10 00 11 01 10 11 00 00..... a c a d b c d a ..... 0 0 1 0 0 0 1 1.....

Q3) Determine the purpose of the following sequential circuit which has one input and three outputs.

Its excitation

table is also shown below :

z2 x

seq. circuit

z1 z0

clock

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Page 7 of 60

d e f

d e f x=0 x=1

z2 z1 z0 x=0 x=1

0 0 0 0 1 1 1 1

010 011 100 101 110 111 000 001

000 001 010 011 100 101 110 111

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 CS2204

111 000 001 010 011 100 101 110

Handout No : 18

000 001 010 011 100 101 110 11 1 April 17, 2014

A3) The analysis of the sequential circuit in the question continues : first we obtain the state table, then state diagram and finally, the timing analysis is done.

The state diagram :

The state table : NS PS q0 q1 q2 q3 q4 q5 q6 q7

x= 0 q2 q3 q4 q5 q6 q7 q0 q1

OUT

x= 1 q7 q0 q1 q2 q3 q4 q5 q6

q0/0 0

0

x=0 x=1 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7

1

t3 0 q5 5

0

1

q2/2

q6/6

0

1 0

1

q5/5

q3/3

1 1

q4/4

0

0

Purpose :

The timing analysis : t2 1 q6 6

q1/1

1

Functional Description : t0 t1 1 1 q0 q7 0 7

1

q7/7

We observe that the output is independent of the input, which indicates that this is a Moore circuit.

time x PS OUT

0

t4 t5 t6 t7 t8 ... 0 0 0 1 1 ... q7 q1 q3 q5 q4 ... 7 1 3 5 4 ....

We realize that this is a modulo-8 counter that when the input is 1, the sequential circuit counts down by 1 and when the input is 0, it counts up by 2.

Q4) A sequential circuit has three flip-flops, named y2, y1 and y0. The black box view, flip-flop output equations (next state equations) and the sequential circuit output equation are shown below:

y2 = y2y0 + y2y1 + y1y0 + xy2 + xy1y0 x

z

y2, y1, y0

y1 = y1y0 + y1y0 y0 = y1y0 + y1y0 z = x y2y1y0

clock

Continue the analysis of the sequential circuit as shown in class to determine its purpose. Note that flip-flop y2 is the most significant flip-flop. Is this sequential circuit a Moore or Mealy circuit ? Why ? Explain in a single sentence.

A4) We continue with the analysis : NYU School of Engineering

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Handout No : 18

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c) The excitation table :

y2y1y0

d) The state table :

y2 y1 y0

z

PS

OUT

NS x=0

x=1

x=0

x=1

x=0

x=1

x=0

x=1

000

001

101

0

0

a

b

f

0

0

001

010

010

0

0

b

c

c

0

0

010

011

011

0

0

c

d

d

0

0

011

100

100

1

0

d

e

e

1

0

100

001

101

0

0

e

b

f

0

0

101

110

110

0

0

f

g

g

0

0

110

111

111

0

0

g

h

h

0

0

111

100

100

0

0

h

e

e

0

0

It is a Mealy circuit since the sequential circuit output z depends on input x. Also, it is a non-finite memory circuit since the state table is not the standard state table for three FFs. e) The state diagram : 0/0

a

0/0

b

0,1/0

c

0,1/0

d

0/1 1/0

e

1/0

1/0 0,1/0

Reset state

f 0,1/0

g 0,1/0

h

f) The purpose of the circuit :

(i) Timing analysis : time t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20....

x 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 1..... PS a b c d e b c d e b c d e b c d e b c d e..... OUT 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 10 0.....

(ii) The Purpose : it recognizes 4-bit distinct nonoverlapping sequences shown below and outputs a 1 for one clock period, when it receives the last bit of the correct sequence :

t 0000 0010 0100 0110

Q5) Consider the following 1-input, 1-output sequential circuit with three flip-flops : NYU School of Engineering

Page 9 of 60

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Handout No : 18

April 17, 2014

FF y2 is the most significant FF. The first two analysis steps are already completed. The following are the sequential circuit output equation and next flip-flip output (next state) equations :

x y1

y2

y0

z

clock y2 = x

z = x y2 y1 y0

y0 = y1

y1 = y2

Continue the analysis of the sequential circuit as shown in class. Is this circuit a Mealy or Moore circuit ? Explain why. Is this a non-finite memory or finite memory circuit ? Explain why.

A5) The analysis steps continue with the excitation table and state table steps below : c) The excitation table :

d) The state table : z

y2 y 1 y 0

y 2 y1 y0

x=0

x=1

x=0 x=1

a

000

000

100

0

0

b

001

000

100

0

0

c

010

001

101

0

0

d

011

001

101

0

0

e

100

010

110

0

0

f

101

010

110

0

0

g

110

011

111

1

0

h

111

011

111

0

0

e) The state diagram : 1/0

g

1/0

h 0/1

0/0 1/0

0/0

OUT

NS x=0

x=1

x=0

x=1

a

a

e

0

0

b

a

e

0

0

c

b

f

0

0

d

b

f

0

0

e

c

g

0

0

f

c

g

0

0

g

d

h

1

0

h

d

h

0

0

f) The functional description : (i) Timing analysis : Time t0 t1 t2 t3 x 0 1 1 0 PS a a e g OUT 0 0 0 1

0/0

0/0

a

PS

b

d

t4 t5 1 1 d f 0 0

t6 t7 t8 t9 t10 0 1 1 1 0 g d f g d 1 0 0 0 0

t11 1 f 0

t12... 1.... g.... 0 ...

0/0

(ii) The Purpose : It is a sequence detector that checks for every overlapping sequence that has 0/0 a 0 then 1 then a 1 and then a 0. It outputs a 1 for one clock period when it e c f receives the last bit of the correct sequence. It never stop checking : 1/0 0/0 1/0 Time 0110 This is a Mealy circuit : The sequential circuit output depends on input x. This a finite memory sequential circuit : It remembers the last three inputs which can be deduced from the state table : The standart state table for three FFs. 1/0

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0/0

1/0

Page 10 of 60

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Handout No : 18

April 17, 2014

Q6) Analyze the following sequential circuit as shown in class : Reset

J clock

Q

z1

J

1

C Q K Pr

z1

Seq. Circ.

1

0

Q

z0

C Q K Clr

z0 1

clock

Reset

0

A6) This is an unusual circuit, but, such circuits are used in real life. The circuit does not really have an input in the sense we are used to. Because, the Reset input is connected to the Direct Preset and Direct Clear inputs, not to the J and K inputs. The Reset input places the sequential circuit in a “reset state” when it is active (in this example, it is active-low) and keeps it there as long as it is active. Once, it becomes inactive (i.e. 1), the circuit is “on its own.” Therefore, our analysis will apply only when the Reset input is inactive, 1. When Reset is 0, we see that FF1 is 1 and FF0 is 0. Thus, the reset state is “10” and the sequential circuit stays at “10” as long as the Reset input is 0. When the Reset input is 1, then FFs can have other values, thus the state of the sequential circuit can change. a) FF input equations and sequential circuit output equations (when the Reset input is inactive, 1) :

b) Next state equations (when the Reset input is inactive, 1) :

J1 = Q0

J0 = 1

Q1 = J1Q1 + K1Q1 = Q0 Q1 + Q0 Q1 = Q0 Q1 + Q0 Q1

K1 = Q0

K0= Q1

Q0 = J0Q0 + K0Q0 = 1Q0 + Q1Q0 = Q0 + Q1Q0 = Q0 + Q1

z1 = Q1

z0 = Q0

The sequential circuit outputs are connected directly to the outputs of the FF’s. That is, the outputs are a function of the current state. This is a Moore circuit.... c) The state transition table :

Q1Q0

Q1 Reset = 0

d) The state table : Q0 Reset = 1

z1z0

PS

NS Reset = 0 Reset = 1

OUT

00

10

11

00

a

c

d

0

01

10

00

01

b

c

a

1

10

10

01

10

c

c

b

2

11

10

11

11

d

c

d

3

e) The state diagram is below. This is a non-finite memory circuit since it remembers an event that happens long time earlier. Also, the state table is not the standard state table for two FFs. NYU School of Engineering

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Handout No : 18

April 17, 2014

a/0

1

1

0 0

d/3

1

0

1

c/2 Holding state

b/1

Reset state

0

f) The functional description : (i) timing analysis : time Reset PS OUT

t0 t1 1 1 c b 2 1

t2 1 a 0

t3 1 d 3

t4 t5 t6 1 1 0 d d c 3 3 2

t7 t8 t9 1 1 1 b a d 1 0 3

t10 t11 t12 t13 ..... 1 1 1 1 ..... d d d d ..... 3 3 3 3 ....

(ii) The purpose : the circuit is a 2-bit down counter which counts down from 2 to 1 to 0 to 3. After reaching count 3, it stays at that count indefinitely. Therefore, state d is the “holding state.” If the Reset input is activated from any state, the counter immediately returns to the reset state (state c or state 10 or count 2) as the Reset input is an asynchronous input. After Reset goes to 1, the counter reaches count 3 again the same way.

Q7) Consider the 1-input, 3-output sequential circuit below with three flip-flops. FF y2 is the most significant FF. The first two analysis steps are already completed. The following are sequential circuit output equations and next flip-flip output (next state) equations : msb

x y2

y1

clock

y0

z2 z1 z0

y2 = x y2 y0 + x y2 y1 + y2 y1 + y2 y1 y0

z 2 = y2 z 1 = y1 z 0 = y0

y1 = x y1 + y1 y0 + x y1 y0 y0 = x y0 + x y0

Continue the analysis of the sequential circuit as shown in class. Is this circuit a Mealy or Moore circuit ? Explain why ?

A7) The analysis steps continue with the excitation table and state table steps below :

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Handout No : 18

April 17, 2014

c) The excitation table :

d) The state table : z2 z 1 z 0 x=0 x=1

y2 y 1 y 0 x=0 x=1

y 2 y1 y0 q0

000

111

110

000

000

q1

001

000

111

001

001

q2

010

001

000

010

010

q3

011

010

001

011

011

q4

100

011

010

100

100

q5

101

100

011

101

101

q6

110

101

100

110

110

q7

111

110

101

111

111

e) The state diagram : 1

q0/0

0

NS x=0

x=1

OUT

q0

q7

q6

0

q1

q0

q7

1

q2

q1

q0

2

q3

q2

q1

3

q4

q3

q2

4

q5

q4

q3

5

q6

q5

q4

6

q7

q6

q5

7

f) The functional description : (i) Timing analysis : 0

Time x PS OUT

1

q1/1

q7/3 1 0

t0 t1 t2 t3 t4 t5 1 1 1 1 1 1 q1 q7 q5 q3 q1 q7 1 7 5 3 1 7

t6 t7 t8 0 0 0 q5 q4 q3 5 4 3

t9 t10 t11 t12... 0 0 0 1.... q2 q1 q0 q7.... 2 1 0 7 ....

0 1

q6/2

(ii) The Purpose :

q2/2

1

0

It is a 3-bit counter that => counts down by 1 when input x is 0 => counts down 2 when x is 1

0

1

q5/1 1

PS

q3/3 0

q4/4

This is a Moore circuit since the sequential circuit outputs do not depend on input x. This can also be seen from the sequential circuit output equations which do not contain x.

1 0

Q8) Consider the following sequential circuit with one input and one output : x

seq. circuit

z

clock Its internal circuit is shown below : Analyze the sequential circuit as shown in class. NYU School of Engineering

Page 13 of 60

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Handout No : 18

April 17, 2014

3 Q

1

T

y3 y3

T

2 Q

y2

Q

y2

Q y3

clock

clock

y3

y1 y3

D

1 Q

y1

Q

y1

y2 x y2

z

y2 y1

x

clock

y3

A8) Note that output z is not a function of input x, thus, this is a Moore circuit. Also, this is a non-finite memory circuit since the state table below is not the standard state table for three FFs. a) The FF input equations and the sequential circuit output equation : T3 = 1 T2 = y3 D1 = xy3 y2 + (y3 + y2)(x + y1) = xy3 y2 + (y3 + y2)(xy1 + xy1) = xy3 y2 + xy3y1 + xy2y1 + xy3y1 + xy2y1 z = y3 y2 y1 c) The excitation table :

y3y2y1

b) Next state equations : y3 = T3y3 + T3y3 = 1y3 + 1y3 = y3 y2 = T2y2 + T2y2 = y3y2 + y3y2 y1 = D1 = xy3 y2 + xy3y1 + xy2y1 + xy3y1 + xy2y1 d) The state table :

y3 y2 y1 x=0 x=1

z x=0

x=1

PS

OUT

NS x=0

x=1

x=0

x=1

000

100

101

0

0

a

e

f

0

0

001

100

101

1

1

b

e

f

1

1

010

110

111

0

0

c

g

h

0

0

011

111

110

0

0

d

h

g

0

0

100

010

011

0

0

e

c

d

0

0

101

011

010

0

0

f

d

c

0

0

110

000

001

0

0

g

a

b

0

0

111

001

000

0

0

h

b

a

0

0

NYU School of Engineering

Page 14 of 60

CS2204

Handout No : 18

April 17, 2014

e) The state diagram :

a/0 0

Reset state

b/1 1

0

1

e/0

c/0 0

0

f/0

1

0

1

0

d/0 1

1

0

g/0

h/0

1

0

1

f) The purpose of the circuit : (i) The timing analysis : assume that the following input sequence is applied to the sequential circuit. Also assume that the initial state is “a.” Then :

1 0 1 1 0 1 0 1 1 0 0 0 0 1 ....

x time x PS OUT

t0 t1 t2 t3 t4 t5 t6 1 0 1 1 0 1 0 a f d g b e d 0 0 0 0 1 0 0

t7 t8 t9 1 1 0 h a f 0 0 0

t10 0 d 0

time t11 t12 t13 ..... 0 0 1 ..... h b e ..... 0 1 0 ....

(ii) The purpose : the circuit outputs a 1 one clock period after odd number of 1s are received on a nonoverlapping four-bit input sequence. States a and b are the starting and ending states to check for a new sequence of four bits. If a sequence ends with state “a” then the sequence did not have odd number of 1s. Otherwise, if the sequence ends with state “b” then it means the sequence had odd number of 1s. For example, above at t4 a new four-bit sequence starts with state b. The four-bit sequence is 0101 takes us to state a in t8 during which the output is 0. This is because, the sequence 0101 does not has odd number of 1s. The next four-bit sequence, starting at t8 is 1000, leading to state b in t12 and the output in t12 is 1 since the sequence 1000 has odd number of 1s.

Q9) Consider the following 1-input, 3-output sequential circuit with three flip-flops : msb

x y2 y1 y0 clock

z2 z1 z0

FF ”y2” is the most significant FF. The internal circuitry is shown below. Continue the analysis of the sequential circuit to determine its purpose as shown in class. Is this circuit a Mealy or Moore circuit ? Explain why. NYU School of Engineering

Page 15 of 60

CS2204

Handout No : 18

April 17, 2014

y2

y1 x

x

y2 x

2 Q

y0 D

y2

y1

y2

z2

T

z1

Q

y0

y1

Q

y0

y1

1 Q

clock y2

clock

x

y2 y1

J

x

K

y0

0 Q

z0

Q y0

clock A9) The analysis of the sequential circuit : a) The FF input equations :

b) Next state equations :

D2 = y2y1 + xy2y0 + y2y1y0 + xy2y1 T1 = x + y0 J0 = K0 = x

y2 = D2 = y2y1 + xy2y0 + y2y1y0 + xy2y1 y1 = T1y1 + T1y1 = (x + y0)y1 + (x + y0)y1

The sequential circuit output equations : z2 = y2 z1 = y1 z0 = y0

= xy1 + y1y0 + (x y0)y1 = xy1 + y1y0 + x y y0 y1 = J0y0 + K0y0 = x y0 + x y0 = x y0 + x y0

This is a Moore circuit : The sequential circuit outputs are independent of x : z2 = y2 & z1 = y1 & z0 = y0. c) The excitation table :

y2 y1 y0

d) The state table :

y2 y1 y0 x=0

x=1

z2 z1 z0 x=0 x=1

q0

000

001

010

000

000

q1

001

010

011

001

001

q2

010

011

100

010

010

q3

011

100

101

011

011

q4

100

101

110

100

100

q5

101

110

111

101

101

q6

110

111

000

110

110

q7

111

000

001

111

111

NYU School of Engineering

Page 16 of 60

PS

CS2204

OUT

NS x=0

x=1

q0

q1

q2

0

q1

q2

q3

1

q2

q3

q4

2

q3

q4

q5

3

q4

q5

q6

4

q5

q6

q7

5

q6

q7

q0

6

q7

q0

q1

7

Handout No : 18

April 17, 2014

e) The state diagram :

1

q0/0

1

0

f) The functional description :

0 1

q7/7

q1/1

1

0

1

0

q2/2

q6/6 0

0

1

1

q5/5

0

0 1

(i) Timing analysis : Time t0 t1 t2 t3 x 1 1 1 1 PS q7 q1 q3 q5 OUT 7 1 3 5

t4 0 q7 7

t5 0 q0 0

t6 t7 0 0 q1 q2 1 2

t8 0 q3 3

t9 t10 .... 1 1 .... q4 q6 .... 4 6 ....

(ii) The Purpose : This is a 3-bit Up counter that count up - by 1 when x is 0 : 3, 4, 5, 6, 7, 0, 1, 2,... - by 2 when x is 1 : 7, 1, 3, 5, 7, 1, 3, 5,....

q3/3

q4/4

Q10) Consider the following 1-input, 1-output sequential circuit : x y2

y1

y0

z

clock The sequential circuit contains three flip-flops. FF y2 is the most significant FF. The first two analysis steps are already completed. The following are next flip-flop output equations and the sequential circuit output equation :

y2 = y2y1 y0 + xy2 y1 + y2y1 y0 + x y2y1 y0 y1 = y2y1 y0 + xy1 y0 + y2y1 y0 + x y1y0

z = y2y1 y0 + y2 y1 y0

y0 = y2y1 y0 + x y0 Continue the analysis of the sequential circuit as shown in class. After doing the timing analysis, if you cannot figure out the purpose, just write “I cannot determine the purpose.” Is this circuit a Mealy or Moore circuit ? Explain why. Is this a non-finite memory or finite memory circuit ? Explain why.

NYU School of Engineering

Page 17 of 60

CS2204

Handout No : 18

April 17, 2014

A10) The following equations are given : y2 = y2y1 y0 + xy2 y1 + y2y1 y0 + x y2y1 y0

y0 = y2y1 y0 + x y0

y1 = y2y1 y0 + xy1 y0 + y2y1 y0 + x y1y0

z = y2y1 y0 + y2 y1 y0

This is a Moore circuit : The sequential circuit output, z, is independent of x. That is, the z equation does not contain “x” as one of the variables. The analysis of the sequential circuit is continued : c) The excitation table :

d) The state table : z2 z1 z0

y2 y 1 y 0

y2 y1 y0

x=0

x=1

x=0

000

000

001

0

0

b

001

000

010

0

0

c

010

000

011

0

0

011

000

100

0

0

e

100

000

101

0

0

f

101

110

110

1

1

110

111

111

1

1

111

000

000

0

0

a

d

g h

NS

PS

OUT

x=0

x=1

x=1

x=0 x=1

a

a

b

0

0

b

a

c

0

0

c

a

d

0

0

d

a

e

0

0

e

a

f

0

0

f

g

g

1

1

g

h

h

1

1

h

a

a

0

0

e) The state diagram : 0/0

0/0

0/0

a

1/0

b

1/0

c

1/0

0/0

d

e

1/0

f

1/0

0,1/1

g

0/0

0,1/1

h

0, 1/0

Reset state

f) The functional description :

(i) Timing analysis : Time t0 t1 t2 t3 x 0 1 1 1 PS a a b c OUT 0 0 0 0

t4 1 d 0

t5 1 e 0

t6 0 f 1

t7 1 g 1

t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 1 0 0 1 1 1 1 1 0 0 1 1 h a a a b c d e f g h a 0 0 0 0 0 0 0 0 1 1 0 0

(ii) Purpose : This is a sequence detector that checks for 5 (five) consecutive 1s :

x 11111XXX z 00000 1 10

Time

Thus, it has a cycle of eight (8) clock periods. Then, it starts checking again. If it receives an incorrect bit, it starts a new sequence. There are no overlapped sequences. This is a non-finite memory sequential circuit since it does not have standard state table for a finite input memory circuit with three flip-flops. NYU School of Engineering

Page 18 of 60

CS2204

Handout No : 18

April 17, 2014

Q11) Consider the following 1-input, 2-output sequential circuit with three flip-flops : x y2

y1

z1

y0

z0

clock

FF y2 is the most significant FF. The first two analysis steps are already completed. The following are sequential circuit output equations and next flip-flip output (next state) equations :

y2 = x y2 + y2 y0 + y2 y1 + x y1 y0

z1 = y1 z0 = y0

y1 = x y1 + y1 y0 + y2 y1 + x y2 y0

y0 = x y1 y0 + x y0 + x y2 y1 + x y2 y0 Continue the analysis of the sequential circuit as shown in class. Is this circuit is a Mealy or Moore circuit ? Explain why ?

A11) The analysis steps continue with the excitation table and state table steps below : c) The excitation table :

d) The state table :

y2 y1 y0

y 2 y 1 y0

x=0

x=1

z1 z 0 x=0 x=1

000

000

001

00

00

001

00 1

010

01

01

010

010

011

10

10

011

011

111

11

11

100

100

000

00

00

101

101

100

01

01

110

110

101

10

10

111

111

110

11

11

PS

NS x=0

x=1

OUT

q0

q0

q1

0

q1

q1

q2

1

q2

q2

q3

2

q3

q3

q7

3

q4

q4

q0

0

q5

q5

q4

1

q6

q6

q5

2

q7

q7

q6

3

This is a Moore circuit since the sequential circuit outputs do not depend on input x. This can also be seen from the sequential circuit output equations which do not contain x.

NYU School of Engineering

Page 19 of 60

CS2204

Handout No : 18

April 17, 2014

e) The state diagram :

f) The functional description : We see that there are state changes if the input is 1. Therefore, we apply 1s to determine the purpose.

0

q0/0

(i) Timing analysis : Time t0 t1 t2 t3 t4 t5 x 1 1 1 1 1 1 PS q1 q2 q3 q7 q6 q5 OUT 1 2 3 3 2 1

0

1

0

q1/1

q7/3 1

1

1

t6 t7 t8 1 1 1 q4 q0 q1 0 0 1

t9 t10... 0 1 .... q2 q2.... 2 2 ....

1

0

q2/2

q6/2 1

0

(ii) The Purpose : It is a modified 2-bit binary up and down counter.that counts when input x is 1. It counts as 1, 2, 3, 3, 2, 1, 0, 0, 1, 2, 3, 3, 2,...

1

q5/1

q3/3

1

The count does not change when x is 0.

0

q4/0 0 0

Q12) Consider the following 1-input, 1-output sequential circuit and its textual input/output relationship : The sequential circuit checks every nonoverlapping 4-bit sequence. If a 4-bit sequence has odd number of 1s, it outputs a 1 for one clock period when it receives the last bit of the current sequence.

x z

clock

Obtain the state diagram of this sequential circuit as discussed in class. Is this a Mealy or Moore circuit ? Why ? Is this a finite memory or non-finite memory sequential circuit ? Why ?

A12) The state diagram is below. 0/0

b

Reset state

0/0

d

f

1/1 0/0

g

1/0

0/0 1/0

a

1/0

1/0 1/0

1/0

c 0/0

e

0/0

0/1

This is a Mealy circuit since the output depends on the input as seen when the state changes from “f” or “g” to “a.” This is a non-finite memory circuit since it does not have the standard state table and state diagram.

NYU School of Engineering

Page 20 of 60

CS2204

Handout No : 18

April 17, 2014

Q13) Consider the following minterm list : f(a,b,c,d)

=

m 0 2 5 7 8 10 13 14 15

Obtain the minimal 2-level NAND-NAND circuit by using the Karnaugh-map method. State whether a term is an essential prime implicant or a secondary essential prime implicant or a prime implicant. Assume that double-rail inputs are available.

A13) The Karnaugh map of this function is : f(a,b,c,d)

a

2

1

1 1

1

1 d

1

1

3

c 1

1 b

=

m 0 2 5 7 8 10 13 14 15

3 abc f(a, b, c, d) = bd + b d + or 1 2 acd 4

1

epi 5 7

4

13

pi pi

epi 0

2

8

Either circuit is minimal. We choose the one with combinations 1, 2 and 3 : A two-level NAND-NAND circuit is directly obtained from a two-level AND-OR network which is in turn directly obtained from a 2-level SOP expression. Note that double-rail inputs eliminate the need for extra NAND gates for inversion.

b d b

f(a, b, c, d)

d a

b c

Q14) Consider the following minterm list for a function : f(a,b,c,d) =

m(1,2,4,5,6,7,10,11,13) + d(8,9)

a) By using the Karnaugh-Map method, obtain the minimal SOP expression as shown in class. State whether a term is an essential prime implicant or a secondary essential prime implicant or a prime implicant. b) Determine the minimal implementation of the expression obtained in part (a) by using only TTL LS NAND-gate chips, as shown in class. Assume that only single-rail inputs are available.

A14) a)Combinations 1, 2 and 3 are essential prime implicants, covering all the minterms except minterm 2. Combinations 4 and 5 are prime implicants. To cover minterm 2, we have two choices either 4 or 5. NYU School of Engineering

Page 21 of 60

CS2204

Handout No : 18

April 17, 2014

m(1,2,4,5,6,7,10,11,13) + d(8,9)

f(a,b,c,d) = a

1 1

2 1 c 1

3

x 1

1

5

4

bcd f(a, b, c, d) = a b + c d + a b + or 1 3 2 acd

x

1

1

1

1

pi pi

5

d 4

epi 4 7

epi 1

13

epi 11

b b) We choose combinations 1, 2, 3 and 4 to implement. We know that any 2-level SOP expression can be directly converted to a 2-level NAND/NAND network. The NAND-only circuit is shown below. Based on that circuit, TTLSSI chip utilization is as follows : 2 74LS00, each with 4 2-input NAND-gates, one NAND gate unused 1 74LS20, with 2 4-input NAND-gates. Zero gates unused 3 chips used. One gate unused. a

a b c

c d

f(a, b, c, d) a

b

b

d

c

d

3-input NAND gate implemented by a 4-input NAND gate

b

Q15) Consider the following switching function whose minterm list is given below : f(a,b,c,d) =

m(0, 1, 6, 7, 10, 11, 14, 15)

i) Obtain the minimal SOP expression by using the K-map method as done in class. ii) Based on part (i), draw the 2-level AND-OR gate network, assuming single-rail inputs. Then, determine the TTL LS SSI chip usage of this 2-level AND-OR gate network as done in class.

NYU School of Engineering

Page 22 of 60

CS2204

Handout No : 18

April 17, 2014

A15) a

i)

f(a,b,c,d) =

1

1

f(a, b, c, d) = a b c + b c + a c

1 c

m(0, 1, 6, 7, 10, 11, 14, 15)

1

1

1

1

1

1

2

1 epi

d

0

3

1

b

2 epi

3 epi

6

10

7

11

ii) The 2-level AND-OR gate network with single-rail inputs and the TTL LS SSI chip usage : a b c b c

a

abc

We need 3 inverters 2 2-input AND gates 1 3-input AND gate 1 3-input OR gate

b c

a c

bc

f(a, b, c, d)

1 74LS04 w/ 6 inverters, 3 inverters unused 1 74LS11 w/ 3 3-input AND gates, 0 gates unused 1 74LS32 w/ 4 2-input OR gates, 2 gates unused 3 chips used. 5 gates unused

ac

Q16) Design a digital circuit with four inputs, a, b, c and d. There are four outputs, p, q, r and s. Inputs (a, b, c, d) represent a 4-bit 2’s complement number, K, where “a” is the most significant bit. Outputs, (p, q, r, s) represent a 4-bit 2’s complement number, M, where “p” is the most significant bit. The relationship between K and M is that the combinational circuit takes the 2’s complement of input K as shown below: a

M=K

2

K

msb

msb

b c d

p(a, b, c, d) q(a, b, c, d) r(a, b, c, d)

M

s(a, b, c, d)

Design the circuit by showing the following steps : - the truth table of the four output functions, - the minterm lists of the four output functions, - the Karnaugh-map for only output function r(a, b, c, d), - the minimal 2-level SOP expression for only output function r(a, b, c, d). In the Karnaugh-map step, specify distinguished-1 cells of output function r(a, b, c, d). Also, specify for each term of the minimal expression, if it is an epi or an sepi or a pi.

NYU School of Engineering

Page 23 of 60

CS2204

Handout No : 18

April 17, 2014

A16) The truth table of the four functions based on the given input-output relationship is below. abcd

p

q

r

s

0000

0

0

0

0

0001

1

1

1

1

0010

1

1

1

0

0011

1

1

0

1

0100

1

1

0

0

0101

1

0

1

1

0110

1

0

1

0

0111

1

0

0

1

1000

1

0

0

0

1001

0

1

1

1

1010

0

1

1

0

1011

0

1

0

1

1100

0

1

0

0

1101

0

0

1

1

1110

0

0

1

0

1111

0

0

0

1

m(1, 2, 3, 4, 5, 6, 7, 8) q(a, b, c, d) = m(1, 2, 3, 4, 9, 10, 11, 12) r(a, b, c, d) = m(1, 2, 5, 6, 9, 10, 13, 14) s(a, b, c, d) = m(1, 3, 5, 7, 9, 11, 13, 15) p(a, b, c, d) =

a 1

c

1

1

1

1

1

1

1

1

d

2

b

r(a, b, c, d) = cd + cd 1 2 1

5 9

epi 13

epi 2 6 10 14

Q17) Design a digital “voting” circuit with four inputs, A, B, C and D. Each input is assigned a “vote weight” as follows : A

msb

B C

Input

Vote Weight

y

voting circuit z

D

A

3

B

4

C

2

D

3

A decision is approved when the “y” output is 1 and the z output is 0, which happens if i) the sum of vote weights is 9 or more, OR, ii) the sum is 7 or 8 and member B has voted for it, i.e. input B is 1. A new vote is asked for if the sum is 5 or 6 during which the “y” output is don’t care and the “z” output is 1. Implement the circuit by using a minimum number of TTL LS SSI chips. Indicate the TTL LS SSI chip usage. Note that double-rail inputs are available. NYU School of Engineering

Page 24 of 60

CS2204

Handout No : 18

April 17, 2014

A17) All possible sums of weights and corresponding “y” and “z” outputs are listed below : ABCD

Vote sum

y

0000

0

0

0

0001

3

0

0

0010

2

0

0

0011

5

X

1

0100

4

0

0

0101

7

1

0

0110

6

X

1

0111

9

1

0

1000

3

0

0

1001

6

X

1

1010

5

X

1

1011

8

0

0

1100

7

1

0

1101

10

1

0

1110

9

1

0

1111

12

1

0

=

y(A,B,C,D)

z

m(5,7,12,13,14,15) + d(3,6,9,10)

A

2

y(A, B, C, D) = A B + B D 1 2

1

X

C

1

1

1

1

X

1

X

epi

12 14

5 7

X 1

B z(A,B,C,D)

epi

D

=

A

m(3, 6, 9, 10)

3

1

1 C

D

1 1

1

2

4

B z(A, B, C, D) = A B C D + A B C D + A B C D + A B C D 1 3 2 4

epi

epi

epi

epi

3

6

9

10

The circuit for the “y” output is a 2-level SOP circuit that can be directly implemented by a 2-level NAND- NAND network. It is the same for the “z” output : C

D

A

B

A B B

y(A, B, C, D)

D

C

B

D

A

z(A, B, C, D)

A D

B

C

A B D

C

We use the following chips : 3 74LS20 with 2 4-input NAND-gate chips, one 4-input NAND gate unused 1 74LS00 with 4 2-input NAND-gate chip, one 2-input NAND gate unused 4 chips used. Two gates unused. NYU School of Engineering

Page 25 of 60

CS2204

Handout No : 18

April 17, 2014

Q18) Consider the following the maxterm list : f(a,b,c,d) =

M(0,2,3,4,6,7,8,12,15)

i) Obtain the minimal SOP expression by using the K-map method as done in class. You will point out the distinguished-1 cell(s). Do that by giving their minterm numbers. Remember also to state whether a term is an essential prime implicant or a secondary essential prime implicant or a prime implicant. ii) Based on part (i), draw the 2-level AND-OR gate network, assuming single-rail inputs. Then, determine the TTL LS SSI chip usage of this 2-level AND-OR gate network as done in class.

A18) We need to get the minterm list from the maxterm list for the minimal 2-level AND-OR gate network. One can immediately obtain the minterm list from a maxterm list :

f(a,b,c,d) =

M(0,2,3,4,6,7,8,12,15) =

m 1,5,9,10,11,13,14

Then, the Karnaugh map of this function is : a

3 abd f(a, b, c, d) = cd + acd + or 1 2 abc 4

3

1 1

1

1

1

d

1

epi

c 1

1

1

4

5

13

pi pi

epi 14

2

b

Either circuit is minimal. We choose the one with combinations 1, 2 and 3 :

c

c

cd d

d

b

d

a

acd

a

abd

c

b

f(a, b, c, d) f(a, b, c, d)

d

1 74LS04 w/ 6 inverters, 3 inverters unused 1 74LS11 w/ 3 3-input AND gates, 0 gates unused 1 74LS32 w/ 4 2-input OR gates, 2 gates unused 3 chips used. 5 gates unused

NYU School of Engineering

Page 26 of 60

CS2204

Handout No : 18

April 17, 2014

Q19) A switching function has been simplified and the following minimal expression is obtained : f(A, B, C, D) = A C + A C Implement the minimal expression, by using as few TTL LS SSI chips as possible as shown in class. Assume that double-rail inputs are available.

A19) There are three solutions each of which uses only one (1) chip : i) The minimal SOP expression results in a 2-level AND/OR gate network. We know that any 2-level AND/OR gate network can be directly converted to a 2-level NAND/NAND network. Thus, we have the following 2-level NAND/ NAND gate network : A C f(A, B, C, D) A C We need three 2-input NAND gates !!! 1 74LS00, with 4 2-input NAND-gates, 1 NAND gate unused 1 chip used. 1 gate unused.

ii) We see that the circuit outputs a 1, if the two inputs (a and b) are different. Thus, this is the EX-OR function : f(A, B, C, D) = A C + A C = A We need one 2-input XOR gate :

A

C

f(A, B, C, D)

C

1 74LS86, with 4 2-input EX-OR-gates, 3 EX-OR gates unused 1 chip used. 3 gates unused.

iii) We realize by using DeMorgan’s theorems that f(A, B, C, D) =A C + A C = A C + A C = (AC)(AC) = (A + C)(A + C) = AC + A C We realize that this is an AOI function implemented by the 74LS51 dual-AOI chip :

:

A C

f(A, B, C, D)

1 74LS51, with 2 AOI networks, one AOI network unused 1 chip used. ine AOI network unused.

A C The cheapest solution is the first one.... NYU School of Engineering

Page 27 of 60

CS2204

Handout No : 18

April 17, 2014

Q20) Consider the following sequential circuit : x

x x

J

y0 seq. circuit

z1

y1 Q

K clock

Q

C

z0

Most Significant FF

x

clock

z1

y1 x

y0

D

y0 x

clock

y0

C

Q

z0

Q

Assuming that single-rail inputs are available, determine the TTL LS SSI chip usage for the case of developing a new PCB.

A20) We need : 1 inverter 4 2-input AND gates 1 3-input OR gate 1 positive-edge triggered J-K FF 1 positive-edge triggered D FF

We realize that there is no positive-edge triggered J-K FF chip. Thus we need an inverter to invert the clock : two inverters are needed. In addition there is no 3-input OR gate TTL chip. We implement it by using two 2-input OR gates as follows :

Then, we need : 2 inverters 4 2-input AND gates 2 2-input OR gates 1 negative-edge triggered J-K FF 1 positive-edge triggered D FF

The TTL LS SSI chip usage is then as follows : 1 74LS04, with 6 inverters, four inverters unused 1 74LS08, with 4 2-input AND gates, zero gate unused 1 74LS32, with 4 2-input OR gates, two gates unused 1 74LS74, with 2 positive edge-triggered D FFs, one FF unused 1 74LS112, with 2 negative-edge triggered FFs, one FF unused 5 chips used. Six gates unused, two FFs unused

Q21) Consider the following minterm list : f(a, b, c, d) = m(1, 4, 5, 6, 9, 11) + d(7, 10, 13) NYU School of Engineering

Page 28 of 60

CS2204

Handout No : 18

April 17, 2014

a) Obtain the minimal SOP expression of the function by using the K-map method as done in class. b) Implement the function by using a single chip : just one 74LS151 MUX chip as done in class. Assume that there are only single-rail inputs. Use no other chips/components.

A21) a) The minimal SOP expression is obtained by using the K-map method is as follows : a

1

f(a, b, c, d) =

2

1 1

1

f(a, b, c, d) = a b + c d + a b d 1 2 3

1

X

m(1, 4, 5, 6, 9, 11) + d(7, 10, 13)

d 1

X c

epi

epi

6

1

11

4

3

X

1

epi

b

b) The MUX implementation is as follows : f(a, b, c, d) =

m(1, 4, 5, 6, 9, 11) + d(7, 10, 13) a

d 0 1 1 d 1 0 0

1 1 c

1

X

1 d

X

1

1

X

I0 I1 I2 I3 I4 I5 I6 I7

74LS151 f(a, b, c, d)

1 74LS151 8-to-1 MUX Total : 1 chip used

Z E 0

b

Chip Usage :

Z

S2 S1 S0

a

b

c

Q22) Consider the following function in the SOP form (not necessarily minimized) : F(A, B, C, D) = A B C + A D + A C Assuming that only single-rail inputs are available, implement the function using the following approaches and indicate the number of chips used : - A generic 4-to-16 DCD-based - A generic 8-to-1 MUX-based - A generic matching ROM-based - A generic matching PLA-based All other chips used are TTL LS chips.

NYU School of Engineering

Page 29 of 60

CS2204

Handout No : 18

April 17, 2014

A22) We need to obtain the minterms of the function from the above expression for the first three implementations. The method we have been using for that is by expanding the subexpressions to make them canonical from which it is easy to obtain the minterms : F(A, B, C, D) = A B C (D + D) + A D(B + B)(C + C) + A C(B + B)(D + D) =ABCD +ABCD + ABCD +ABCD +ABCD + ABCD + ABCD +ABCD +ABCD + ABCD =ABCD +ABCD + ABCD +ABCD +ABCD + ABCD + ABCD +ABCD 0 1 1 1 01 1 0 1 1 1 1 10 1 1 11 0 1 1 0 0 1 11 1 0 1 0 1 0 7

6

15

11

F(A,B,C,D) =

13

9

14

10

m(6,7,9,10,11,13,14,15)

i) A generic 4-to-16 DCD-based :

m(6,7,9,10,11,13,14,15)

F(A,B,C,D) =

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15

4-to-16 DCD

msb

A B

I3 I2 I1 I0

C D

0

E

We need : 1 4-to-16 generic DCD 7 2-input OR gates

F(A, B, C, D)

1 4-to-16 generic DCD 2 74LS32 4 2-input OR gate chip, 1 gate unused 3 chips used, 1 gate unused

ii) A generic 8-to 1 MUX-based : A First, we get the K-map of the function : If (A,B,C) are used as select signals, the D input can be used without any complement operation :

C

1

1

1

1

1

1

1

1

D

B The MUX circuit implementing the gate network : NYU School of Engineering

Page 30 of 60

CS2204

Handout No : 18

April 17, 2014

0 0 0 1 D 1 D 1

I0 I1 I2 I3 I4 I5 I6 I7

0

E

1 8-to-1 generic MUX

Y F(A, B, C, D)

1 chip used

S2 S1 S0 A B C iii) A generic matching ROM-based :

D C

A0 A1

B A 0

16x1-bit ROM

A2 msb

Location

D0

A3

F(A, B, C, D)

EN

1 16 x 1-bit generic matching ROM 1 chip used

Address A B C D A3 A2 A1 A0

Content F(A, B, C, D) D0

0

0

0

0

0

0

1

0

0

0

1

0

2

0

0

1

0

0

3

0

0

1

1

0

4

0

1

0

0

0

5

0

1

0

1

0

6

0

1

1

0

1

7

0

1

1

1

1

8

1

0

0

0

0

9

1

0

0

1

1

A

1

0

1

0

1

B

1

0

1

1

1

C

1

1

0

0

0

D

1

1

0

1

1

E

1

1

1

0

1

F

1

1

1

0

1

iv) A generic matching PLA-based : NYU School of Engineering

Page 31 of 60

CS2204

Handout No : 18

April 17, 2014

=> We first minimize the function to get a minimal expression : A 2 1

C

1

1

1

1

1

1

1

1

F(A, B, C, D) = BC + AD + AC 2 3 1 epi epi epi

D 3

6

7

9 13

10

B => Then, we program the PLA-based on the minimal SOP expression : A

B

C

D 1 generic matching PLA 1 chip used BC AD AC

F

Q23) A digital “voting” circuit with four inputs, A, B, C and D has been designed, where each input is assigned a “vote weight” as follows : A B C

y

voting circuit

D

z

Input

Vote Weight

A

3

B

4

C

2

D

3

y

z

Result

0

0

Decision not approved

X

1

Revote

1

0

Decision approved

As the operation table of the circuit above shows, a decision is approved, that is the “y” output is 1 and the z output is 0, if i) the sum of vote weights is 9 or more, OR, ii) the sum is 7 or 8 and member B has voted for it, i.e. input B is 1. A new vote is asked for if the sum is 5 or 6 during which the “y” output is don’t care and the z output is 1. The minimal expressions have been developed and by using them the TTL LS SSI implementation of the circuit with double-rail inputs and only NAND gates has resulted in four chips with two gates unused : NYU School of Engineering

Page 32 of 60

CS2204

Handout No : 18

April 17, 2014

z(A, B, C, D) = A B C D + A B C D + A B C D + A B C D

y(A, B, C, D) = A B + B D

For this problem, show the implementation with a generic matching PLA chip and then a generic matching PAL chip. Finally, indicate which chip is more appropriate for implementation.

A23) The circuit with a generic matching PLA chip is as follows : A

B

C

D

AB BD A BCD ABCD AB CD ABCD

y(A, B, C, D)

z(A, B, C, D)

The circuit with a generic matching PAL chip is as follows : A

B

C

D

AB BD A BCD ABCD AB CD ABCD

y(A, B, C, D)

z(A, B, C, D)

The product terms of the two expressions are not the same : There is no sharing among the functions. Thus, a PAL is more appropriate for implementation. NYU School of Engineering

Page 33 of 60

CS2204

Handout No : 18

April 17, 2014

Q24) By using a generic matching PLA, implement a digital circuit with five inputs and one output. Inputs A and B are data inputs and C2, C1 and C0 are control inputs. The output is named F. The digital circuit performs eight different operations based on the control signals : Control signals C2 C1 C0

Function F

0 0 0

1

0 0 1

A v B (Or)

A Digital F(C2,C1,C0,A,B)

circuit

B

C2 C1

C0

0 1 0

AB

0 1 1

A xor B (Xor)

1 0 0

A xnor B (Xnor)

(Nand)

1 0 1

AB

(And)

1 1 0

A + B (Nor)

1 1 1

0

This digital circuit is a 1-bit Logic Unit (LU) as it performs only logical operations and has only a 1-bit output. If it performed also arithmetic operations, it would be called Arithmetic Logic Unit (ALU). Every computer has an ALU which is typically a 32-bit or a 64-bit ALU.

A24) The generic matching PLA has 5 inputs : C2, C1, C0, A and B. The operation table is as follows : C2

C1

C0

F

F is 1 if

0

0

0

1

C0 C1 C21 = C0 C1 C2(A B + A B + A B + A B)

0

0

1

A+B

C0 C 1C2 (A+B) = C0 C 1C2 (AB + AB + AB)

0

1

0

AB

C0 C1 C2(A + B) = C0 C1 C2(A B + AB + AB)

0

1

1

A XOR B

C0 C1 C2(AB + AB)

1

0

0

A XNOR B

C0 C1 C2(A B + A B)

1

0

1

A.B

1

1

0

A+B

1

1

1

0

C0 C 1C2(AB) C0 C1 C2(A B)

C2 AB + AB+ AB + AB + AB + AB AB

C0

AB + AB + AB

AB + AB

AB

AB+ AB

F(C2, C1, C0, A, B) = C0A B + C2AB + C2AB + C1AB

AB

C1 NYU School of Engineering

Page 34 of 60

CS2204

Handout No : 18

April 17, 2014

C2

C1

A

C0

B

PLA

C0A B C2AB C2AB C1AB

The output of the 1-bit LU

F

K

a b c d

L3 L2 L1

combinational circuit

Address

msb

msb

L

L0

D0 D1

A2 32x8-bit A3 ROM

D2 D3

A4 (msb)

L = (K+(25)10)mod16 K is a 4-bit 2’s Complement number

A0 A1

Enable

EN

D4 D5 D6

Data

Q25) Design a combinational circuit that has four inputs and four outputs :

D7

(msb)

L is a 4-bit unsigned number

The combinational circuit computes (K + (25)10)modulo16. For example, if K is (-6)10, the L output of the combinational circuit is ((-6)10 + (25)10)mod16 = (19)10mod16 = (3)10. A ROM-based implementation is decided for the combinational circuit where a generic 32x8-bit ROM as shown above is used. No other chip or gate can be used. Draw the circuit. Show how the ROM is programmed as discussed in class. Indicate how many ROM content bits are unused. Note again, your circuit must contain only one chip.

A25) The truth table of the combinational circuit and ROM connections are shown below :

NYU School of Engineering

Page 35 of 60

CS2204

Handout No : 18

April 17, 2014

a b c d

L3

L2

L1

L0

0000

1

0

0

1

0001

1

0

1

0

0010

1

0

1

1

0011

1

1

0

0

0100

1

1

0

1

0101

1

1

1

0

0110

1

1

1

1

0111

0

0

0

0

1000

0

0

0

1

1001

0

0

1

0

1010

0

0

1

1

1011

0

1

0

0

1100

0

1

0

1

1101

0

1

1

0

1110

0

1

1

1

1111

1

0

0

0

(0 + 25)mod16 = 25mod16 = (9)10 = (1001)2 unsigned

d c b a 0

A0 A1 A2 32x8-bit A3 ROM A4 (msb)

0

D0 D1 D2 D3

L0 L1 L2 L3

D4 D5 D6 D7

EN

(msb)

(-1 + 25)mod16 = 24mod16 = (8)10 = (1000)2 unsigned

The ROM content is as follows :

Loc 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 ... 1F

Address 0 a b c d A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

NYU School of Engineering

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

Data D7 D6

D5

D4

L3 L2 L1 L0 D3 D2 D1 D0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Page 36 of 60

0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0

CS2204

0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

Number of unused bits : (16*4) + (16*8) = 64 + 128 = 192 bits The ROM has 32 locations but we do not use “bottom” 16 locations : locations 10 through 1F. Therefore, we do not use 16 * 8 = 128 bits. In addition, in the 16 locations used (locations 0 through F), most significant (leftmost) four bits are not used. Thus, we do not use 16 * 4 = 64 bits. Overall then, 192 bits are unused.

Handout No : 18

April 17, 2014

Q26) Consider the following 4-input, 3-output combinational circuit and its operation table : 3 Combinational

Situation Operation

3

R

Circuit

a

K, (K2, K1, K0) and R, (R2, R1, R0) are 3-bit 2’s Complement Binary numbers

a=0

R=K+1

a=1

R=K

Implement the above circuit by using 16x2-bit ROM chips shown on the right side and as done in class. That is, show the following implementation steps :

If K is the max value (3)10, then R = K + 1 is the min value (-4)10

2

A3 A2

D1

Use these

K

A1 i) The truth table (a is the most significant input) ii) The ROM circuit, iii) The ROM content, and iv) The number of unused bits.

A0

D0

E

16X2-bit ROM

Assume that only single-rail inputs are available.

A26) i) The truth table : a

K2

K1

K0

R2

R1

R0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

1

0

0

1

1

0

0

1

1

1

0

0

0

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

0

1

1

1

0

1

1

1

0

0

0

1

0

0

0

0

0

0

1

0

0

1

1

1

1

1

0

1

0

1

1

0

1

0

1

1

1

0

1

1

1

0

0

1

0

0

1

1

0

1

0

1

1

1

1

1

0

0

1

0

1

1

1

1

0

0

1

NYU School of Engineering

Page 37 of 60

ii) The ROM circuit

a

A3

a

A2

D1

K2 A1 K1 A0 K0 0

R2

D0 R1

E

A2

K2 A1 K1 A0 K0 0

D1 D0 R0

E

ROM1

CS2204

A3

ROM0

Handout No : 18

April 17, 2014

iii) The ROM tables a

K2

K1

K0

R0

Y0

D1

D0

a

K2

K1

K0

R2

R1

A3

A2

A1

A0

D1

D0

A3

A2

A1

A0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

1

0

0

0

1

0

0

1

0

0

1

0

1

0

0

1

1

1

0

0

0

1

1

0

0

1

0

0

1

0

0

1

0

0

1

0

1

0

1

1

1

0

1

0

1

0

0

1

1

0

1

1

0

1

1

0

1

0

1

1

1

0

0

0

1

1

1

0

1

0

0

0

0

0

1

0

0

0

0

1

0

0

1

1

1

1

0

0

1

1

1

0

1

0

1

1

1

0

1

0

0

1

0

1

1

1

0

1

0

1

1

1

1

1

0

0

1

0

1

1

0

0

0

1

1

0

1

0

1

1

1

0

1

1

1

1

1

0

0

1

1

1

1

0

0

1

1

1

1

0

0

1

1

1

1

1

iv) The number of unused bits : - ROM1 uses all of its bits. - ROM0 does not use 16 bits. Therefore, the number of unused bits is 16

ROM0 Table

ROM1 Table

Q27) Consider the following three functions : w(a, b, c, d) = c d + c d + a b

y(a, b, c, d) = a c + a c + b d

z(a, b, c, d) = a d + b c + a c

Implement the three functions by using a single Monolithic Memories 12H6 PAL chip whose description handout is given in class. You may use off-chip (external) connections, but no external gate (no other chip) can be used. Assume that only single-rail inputs are available.

A27) We implement the three functions by using a single Monolithic Memories 12H6 PAL chip : w(a, b, c, d) = c d + c d + a b

NYU School of Engineering

y(a, b, c, d) = a c + a c + b d

Page 38 of 60

CS2204

z(a, b, c, d) = a d + b c + a c

Handout No : 18

April 17, 2014

a

b I1

I0

c I2

d I3

I5

I4

..... I11

cd F0

cd

w

ab ac F1

ac bd

y

ad

F2

bc ad+bc

F3

ab

. . .

.. .

z

F5

Q28) Consider the following 4-input, 4-output combinational circuit and its operation table :

K M

a b

msb

c d

msb

Operation Combinational

4

Circuit

R

R is equal to the multiplication of K and M

R=K*M

K (a, b), M (c, d) and R (R3, R2, R1, R0) are Unsigned Binary numbers Implement the above circuit by using a single generic matching ROM chip and as done in class. That is, show the following implementation steps : i) The truth table (a is the most significant input) ii) The size of the generic matching ROM iii) The ROM circuit iv) The ROM content v) The number of unused bits

A28) The implementation is shown below :

NYU School of Engineering

Page 39 of 60

CS2204

Handout No : 18

April 17, 2014

i) The truth table : K

iii) The ROM table R

M

a

b

c

d

R3

R2

R1

R0

A3

A2

A1

A0

D3

D2

D1

D0

0

0

0

0

0

0

0

0

K

M

a

b

c

d

R3

R2

R1

R0

R

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

2

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

3

0

0

1

1

0

0

0

0

0

0

0

1

1

0

0

0

0

1

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

1

0

1

0

1

0

0

0

1

1

0

1

0

1

0

0

0

1

1

2

0

1

1

0

0

0

1

0

2

0

1

1

0

0

0

1

0

1

3

0

1

1

1

0

0

1

1

3

0

1

1

1

0

0

1

1

2

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

2

1

1

0

0

1

0

0

1

0

2

1

0

0

1

0

0

1

0

2

2

1

0

1

0

0

1

0

0

4

1

0

1

0

0

1

0

0

2

3

1

0

1

1

0

1

1

0

6

1

0

1

1

0

1

1

0

3

0

1

1

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

3

1

1

1

0

1

0

0

1

1

3

1

1

0

1

0

0

1

1

3

2

1

1

1

0

0

1

1

0

6

1

1

1

0

0

1

1

0

3

3

1

1

1

1

1

0

0

1

9

1

1

1

1

1

0

0

1

ii) The ROM size and circuit

iv) The number of unused bits : The ROM uses all of its bits, since it is a matching ROM

The matching ROM size is 16 x 4-bit since the circuit has 4 inputs and 4 outputs A3 D3 a R3 b A2 D2 16 x 4-bit R2 c A1 D1 ROM A0 R1 d E D0 0 R0

Therefore, the number of unused bits is 0

Q29) Design a digital circuit with four inputs, a, b, c and d. There are four outputs, p, q, r and s. The black-box view of the combinational circuit and the minimal SOP expressions for the four functions are shown below : a msb

p(a, b, c, d)

b c

q(a, b, c, d) r(a, b, c, d)

d

s(a, b, c, d) NYU School of Engineering

p(a, b, c, d) = a b + a d + a c + a b c d

r(a, b, c, d) = c d + c d

q(a, b, c, d) = b c + b d + b c d

s(a, b, c, d) = d

Page 40 of 60

CS2204

Handout No : 18

April 17, 2014

Implement the four functions by using a single Monolithic Memories 12H6 PAL chip whose description handout is given in class. No off-chip (external) connections nor external gates (no other chip) can be used.

A29) We implement the three functions by using a single Monolithic Memories 12H6 PAL chip : p(a, b, c, d) = a b + a d + a c + a b c d

r(a, b, c, d) = c d + c d

q(a, b, c, d) = b c + b d + b c d

s(a, b, c, d) = d

The programming of the PAL chip is as follows : I0

a

I1

b

I2

c

I3

d

I4

I4

..... I11

ab F0

ad ac

p

abcd bc F1

bd bcd

q

cd

F2

cd d

r

F3

. . .

.. .

s

F5

Q30) Consider the following 4-input, 2-output combinational circuit and its operation table : a b c

msb

msb

y(a, b, c, d) z(a, b, c, d)

d

a b c d

y z

0 1 0 0 0

x 1 1 0 0

0 x 1 0 0

0 x x 1 0

0 x x x 1

x 1 0 1 0

a) Obtain the truth table of the combinational circuit. b) Obtain the minimal SOP expressions of the two functions by using the K-map method as done in class. c) Implement the two outputs by using minimum number of smallest generic ROMs. You may use other compoNYU School of Engineering

Page 41 of 60

CS2204

Handout No : 18

April 17, 2014

nents but a minimum number of them. You must use at least one ROM. Show the ROM implementation as done in class.

A30) The ROM implementation by using the K-map method is as follows : 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

abcd

y

z

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

x 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

x 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1

y(a, b, c, d) =

The Minterm lists :

z(a, b, c, d) =

m(4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) + d(0) m(2, 3, 8, 9, 10, 11, 12, 13, 14, 15) + d(0)

a

1

a 2

x

1

1

1

1

1

1

1

x

1

1

1

1

c

d

1 c

1

1

1

1

1

1

1

1

1

b

b

f(a, b, c, d) = b + a 1 2 epi 5

4

6

7

f(a, b, c, d) = b c + a 1 2

epi

epi 9

8

10

11

2

Since both outputs are independent of input “d,” and are 1 when “a” is 1, we can use a ROM of size 4x2-bit to output the values :

a

1

d 1

2

3

epi 8

9

12 13 14 15

ROM Table

b

A1

D1

b

c

y

c

A0

D0

A1

A0

D1

D0

0

0

0

0

0

1

0

1

1

0

1

0

1

1

1

0

E

a

4x2-bit ROM

E

1

I

Y

z

a

z

E

1

I

Y

y

The number of unused bits is 0.

Q31) Consider a sequential circuit with a clock input and four outputs. The black-box view, the implementation of the black box with a 74LS169 counter and a generic 8x4-bit ROM and the content of the ROM are shown below. Determine what this sequential circuit does by continuing with the following table and showing the values for 12 clock periods : NYU School of Engineering

Page 42 of 60

CS2204

Handout No : 18

April 17, 2014

msb

cnt3

Q0 cnt0 cnt1 Q1

A0

P2

Q2 cnt2

A2

P3

a

Q3

PE CEP

TC

CET

D0

A1

D1 D2

msb

cnt3

D3

msb

msb

0

74LS169

clock

d c b a

P0 P1

d c b a

8x4-bit ROM

EN

0 cnt3

cnt3

CP

clock The ROM content : ROM

Location

U/D

Continue with the table below :

cnt2 cnt1 cnt0

a

b

c

d

Time

cnt3 cnt2 cnt1 cnt0

a b c d

A0

D3 D2 D1 D0

0

0

0

0

0

0

t0

0

0

0

0

0 0 0 0

0

0

1

0

0

0

1

t1

0

0

0

1

....

2

0

1

0

0

0

1

1

....

....

....

3

0

1

1

0

1

1

1

t11

....

....

4

1

0

0

1

1

1

1

5

1

0

1

0

0

0

1

6

1

1

0

0

0

1

1

7

1

1

1

0

1

1

1

A2

A1

0

0

1

A31) We determine what this sequential circuit does, by completing the table for 12 clock periods below. We see that the counter counts in a cycle as follows : It counts from 0 4. Then, it loads 15 and counts down 12 and loads 0 to count up again. The ROM outputs follow the rightmost three bits of the counter in such a way that when counting up at each count more ROM outputs become 1 : 0000-0001-0011-0111-1111. When counting down at each count more ROM outputs become 0, except when the counting down reaches 12 : 01110011-0001-1111.

NYU School of Engineering

Page 43 of 60

CS2204

Handout No : 18

April 17, 2014

Time

cnt3 cnt2 cnt1 cnt0

a b c d

t0

0

0

0

0

0 0 0 0

t1

0

0

0

1

0 0 0 1

t2

0

0

1

0

0 0 1 1

t3

0

0

1

1

0 1 1 1

t4

0

1

0

0

1 1 1 1

t5

1

1

1

1

0 1 1 1

t6

1

1

1

0

0 0 1 1

t7

1

1

0

1

0 0 0 1

t8

1

1

0

0

1 1 1 1

t9

0

0

0

0

0 0 0 0

t10

0

0

0

1

0 0 0 1

t11

0

0

1

0

0 0 1 1

Q32) Consider Macro 3, M3, of the term project studied in class and designed in the lab. It is the “Rightmost Zero Display” circuit that outputs the position number of the rightmost display that has a zero. The black box view below shows its inputs and outputs with shorter names :

a b c Pos0zero ==> d Pos3zero ==> Pos2zero ==> Pos1zero ==>

msb msb

y(a, b, c, d) P2PT

Y

N

Play on the rightmost largest reward points position. If direct playing and adding give the same largest reward points, select direct playing.

Play on the rightmost largest adjacency position. If direct playing and adding give the same largest adjacency, select direct playing.

a) Assume that the code is F1. The table below shows the random digit, position displays before and after the machine player plays, if the machine player is behind, whether the random digit is played directly or added, the number of adjacencies, the points earned by the machine player and if the machine player plays again. Complete the rows of the table. You will circle the position played. A large portion of the datapath of the circuit that implements Block 6 for the above specific playing strategy (two rectangles and one oval) is designed below : NYU School of Engineering

Page 51 of 60

CS2204

Handout No : 18

April 17, 2014

RD

Displays before play PD3 PD2 PD1 PD0

Displays after play PD3 PD2 PD1 PD0

Player 2 is behind

5

F

A

A

F

Yes

2

A

E

8

7

No

3

9

C

9

3

No

6

9

F

6

6

Yes

1

F

C

A

8

No

Adjacency Position Circuit

APOS0

APOS2

RPOS0 B0

APOS3

APOS1

APOSAdd

RPOS1

B1

APOS2

A2

2

.....

Gta

A1

Y0

LRGADJ RPOS2 B2 RPOS0

Rightmost . . . . .

Largest

RPOS1

Reward

RPOS2

Points Circuit

P1PT P2PT

8

P2SEL0

Y1

Test0

Y2

Test1

P2SEL1 P2SEL2

Test2

Y3

P2SEL3 Test3 Play

0

P2skip

P2behind Sel

APOSAdd

A

2-to-1

8

LRGRWD 8

Plays Again ?

RPOS3 B3

RPOSAdd

.....

Gtr

APOS3

A3

RPOS3

Position

Reward Points (Decimal)

Sel

A0

APOS1

4-bit 2-to-1 MUX

Rightmost Largest

Adjacency

P2behind

APOS0 . . . . .

D/A

RPOSAdd

B

Y

P2add

MUX Play

TestAdd

A

B

8-bit Unsigned Binary Comparator

AGtB

Play P2sturn

P2behind

P2played

Play is 1 in the last Player 2 state. P2sturn is equivalent to S4 which means it is Player 2 that has the turn to play. NYU School of Engineering

Page 52 of 60

CS2204

Handout No : 18

April 17, 2014

b) Assume that the strategy is changed as follows (three rectangles and two ovals) : P1PT > P2PT

Y

N Any Adjacency ?

Play on the rightmost largest reward points position. If direct playing and adding give the same largest reward points, select direct playing.

Y

N Play on the rightmost largest display position directly.

Play on the rightmost largest adjacency position. If direct playing and adding give the same largest adjacency, select direct playing. Complete the rows of the table below. You will circle the position played :

RD

Displays before play PD3 PD2 PD1 PD0

Displays after play PD3 PD2 PD1 PD0

Player 2 is behind

5

F

A

A

F

Yes

2

A

E

8

7

No

3

9

C

9

3

No

6

9

F

6

6

Yes

1

F

C

A

8

No

D/A

Adjacency

Reward Points (Decimal)

Plays Again ?

c) Modify the above circuit to implement the new strategy (three rectangles and two ovals). Use Macro 2, M2, which is the “Rightmost Largest Display” circuit as a black box with outputs (y, z) in your modified circuit. You can just show the modified portion of the circuit, not the whole circuit.

A36) a) The table is completed as follows : RD

Displays before play PD3 PD2 PD1 PD0

Displays after play PD3 PD2 PD1 PD0

Player 2 is behind

D/A

Adjacency

Reward Points (Decimal)

Plays Again ?

5

F

A

A

F

F

A

F

F

Yes

A

1

150

Yes

2

A

E

8

7

A

E

8

2

No

D

0

2

No

3

9

C

9

3

9

C

3

3

No

D

1

6

Yes

6

9

F

6

6

F

F

6

6

Yes

A

1

30

Yes

1

F

C

A

8

F

C

A

1

No

D

0

9

No

c) The modified portion of the datapath is as follows : NYU School of Engineering

Page 53 of 60

CS2204

Handout No : 18

April 17, 2014

LRGADJ1

Rightmost . . . . .

Y0

y

Largest

I1

Display z

DCD I0

B0

DPOS0

C0

APOS1

Sel1

B1

DPOS1

C1 A2

APOS2 RPOS2

B2

DPOS2

C2

DPOS3

Select0

Sel0

Y0

A1

RPOS1

P2behind

Select0

4-bit 4-to-1 MUX

RPOS0

Select1

P2behind

Select1 A0

Noadj

Y2 DPOS2 Y3

Circuit

APOS0

LRGADJ0

2-to-4 Y1 DPOS1

msb

Position

Noadj

DPOS0

P2SEL0

Y1

Test0

Y2

Test1

P2SEL1 P2SEL2

Test2

Y3

P2SEL3 Test3 Play

Select0 Sel

APOSAdd

A

2-to-1 RPOSAdd A3

APOS3

B3

C3

RPOS3

DPOS3

B

Y

MUX Select1 Play

TestAdd

P2add

b) The table is completed as follows : RD

Displays before play PD3 PD2 PD1 PD0

Displays after play PD3 PD2 PD1 PD0

Player 2 is behind

D/A

Adjacency

Reward Points (Decimal)

Plays Again ?

5

F

A

A

F

F

A

F

F

Yes

A

1

150

Yes

2

A

E

8

7

A

2

8

7

No

D

0

2

No

3

9

C

9

3

9

C

3

3

No

D

1

6

Yes

6

9

F

6

6

F

F

6

6

Yes

A

1

30

Yes

1

F

C

A

8

1

C

A

8

No

D

0

1

No

NYU School of Engineering

Page 54 of 60

CS2204

Handout No : 18

April 17, 2014

Q37) Consider Block 6, the Machine Play Block, of the term project. Assume that the machine player has the following playing strategy : Play on the (rightmost) largest adjacency position (directly if equal)

a) Based on the discussions in the lab, how many clock periods does the machine player take to play ? Explain. b) Assume that the above machine player is modified to have the new strategy shown below : The adjacency < 1 ? N

Y

Play on the position to the right of the position that has just been played by the human player or machine player (because the machine player had an adjacency). If the last play was on position 0, play on position 2. Always play with an addition.

Play on the (rightmost) largest adjacency position (directly if equal)

The table below shows the random digit, position displays before and after the machine player plays, the position the human/machine player has just played, whether the random digit is played directly or added, the number of adjacencies, the points earned by the machine player and if the machine player plays again. Note that each row is independent. Assume that the code is E9. Complete the rows of the table. You will circle the position played :

RD 2

Displays before play PD3 PD2 PD1 PD0 E

Last Play

C

C

C

2

7

1

8

7

0

1

3

6

9

9

6

0

8

4

C

4

8

1

1

B

C

D

8

3

Displays after play PD3 PD2 PD1 PD0

D/A

Adjacency

Reward Points (Decimal)

Plays Again ?

c) i) Design the datapath of the machine player to implement the new strategy. In order to do that work on the figure below that shows portions of the datapath. In the figure, LRGADJPOS indicates the rightmost largest adjacency position, Adjadd indicates whether the largest adjacency is with direct playing or with an addition. LRGADJ indicates the amount of the largest adjacency. If you use other signals, describe what they are.

NYU School of Engineering

Page 55 of 60

CS2204

Handout No : 18

April 17, 2014

2

Rightmost Largest

. . . . .

P2SEL0 P2SEL1

LRGADJPOS

Adjacency

P2SEL2

Adjadd

P2SEL3

Position

2

Circuit

P2add

LRGADJ

P2played

P2skip

ii) How many clock periods does the machine player take to play now ? Explain. A37) a) It takes nine clock periods for the machine player to play since we have to collect all eight adjacencies in eight clock periods and then in the nineth clock periods we play. That is, it tests directly and with additions to collect eight adjacencies to determine the largest adjacency position, taking eight clock periods. Then it takes one clock period to play. b) The table is completed as shown below. RD 2

Displays before play PD3 PD2 PD1 PD0 E

Last Play

Displays after play PD3 PD2 PD1 PD0

D/A

Adjacency

Reward Points (Decimal)

Plays Again ?

C

C

C

2

E

C

E

C

A

0

126

N

7

1

8

7

0

1

1

8

7

7

A

1

14

Y

3

6

9

9

6

0

6

9

9

9

A

2

108

Y

8

4

C

4

8

1

4

4

4

8

A

2

16

Y

1

B

C

D

8

3

B

D

D

8

A

1

26

Y

The strategy does not check for code digits and so misses to earn code reward points when RD is 7 and 1. However, by chance it earns code reward points when RD is 2 and 3.

c) i) The modified Datapath is shown below.

NYU School of Engineering

Page 56 of 60

CS2204

Handout No : 18

April 17, 2014

LRGADJ1

Largest

. . . . .

LRGADJPOS

B0

APOS0

Adjacency

Adjadd 2

Circuit

APOS1

B1

LASTPOS2

A2

APOS2

B2

LRGADJPOS1 I0 LRGADJPOS0 I1 E

Play

2-to-4 DCD

LRGADJ

Y3

APOS3

Y2

APOS2

Y1

APOS1

Y0

APOS0

LASTPOS3

Test0

P2SEL0

Test1

P2SEL1

Test2

P2SEL2

Test3

P2SEL3

Y0

A1

LASTPOS1

Position

Sel

A0

LASTPOS0

Y1

4-bit 2-to-1 MUX

2

Rightmost

A3

Y2

Y3

B3

APOS3

Enable

Play

Play

Testadd

P2add

LRGADJ1 Adjadd Play 0 LASTPOS3

PSEL3 D3 PSEL2 D2

4-bit Register

PSEL1 D1

Q3 Q2

LRGADJ1

LASTPOS2

P2played

Play Q1

PSEL0 D0

LASTPOS1

Q0

P2sturn

Storepos CE

P2skip

LASTPOS0 P2clk

0

C

ii) The machine player still takes nine clock periods to play since we have to collect the adjacency information taking 8 clock periods. Then, the next clock period we play. The new signals used are as follows : Play is 1 in the last clock period. P2sturn is 1 when it is machine player’s turn. That is when it is state 4 of the ppm operation diagram. Testadd is 1 when it is states 4 through 7 of the machine player operation diagram. Test0, Test1, Test2 and Test3 are active when we test positions 0, 1, 2 and 3, respectively. Storepos is 1 the clock period after the human player or machine player plays. That is it is 1 when it is state 2 or state 5 of the ppm operation diagram.

NYU School of Engineering

Page 57 of 60

CS2204

Handout No : 18

April 17, 2014

Q38) Consider Block 6, the Machine Play Block, of the term project. Assume that the digital system in Past Exam Question Q3 of Homework IV is used for the machine player as follows :

K

Z0

4

RWD 8

P2sturn

P2SEL0

Y1

P2SEL1

Z1

Y

Z2

Go

4

P2SEL2

Y2 Z3

Z

P2SEL3

Y3

Clr

Clearp2ffs

Y0

Valid

1 Valid

clock

P2clk

P2add

Valid P2sturn

P2played P2skip

0 a) Assume that the machine player uses the strategy implemented by the circuit above. Assume also that the code is EC. Complete the rows of the table below. You will circle the position played

RD

Displays before play PD3 PD2 PD1 PD0

7

5

E

5

5

4

4

9

A

4

2

C

8

4

A

9

A

6

5

3

3

6

3

6

9

Displays after play PD3 PD2 PD1 PD0

D/A

Adjacency

Reward Points (Decimal)

Plays Again ?

b) Assume that the above machine player is modified to have a new strategy shown below : RD = 0 ? Y Play on the (rightmost) largest display with an addition NYU School of Engineering

Page 58 of 60

N Play on the (rightmost) largest regular reward points with an addition CS2204

Handout No : 18

April 17, 2014

Design the modified machine player to implement the new strategy. Use the circuit in Question 3 and the Rightmost Largest Display Position circuit designed in Experiment 4 as well as other circuits. Describe the new signals you use. Draw your design below.

K

P2SEL0

4

8

Y

Go

P2SEL1 P2SEL2

4 Z

P2SEL3

Clr

P2add

Valid

clock

P2played Rightmost DISP

Largest

z

I1

Display

16

Position

y

Y0

DPOS0

2-to-4 Y1

DPOS1

I0

DCD

DPOS2

Y3

DPOS3

msb

Circuit

P2skip

Y2

How many clock periods does the machine player take to play ? Explain.

A38) a) The table is completed as shown below : RD

Displays before play PD3 PD2 PD1 PD0

Displays after play PD3 PD2 PD1 PD0

D/A

Adjacency

Reward Points (Decimal)

Plays Again ?

7

5

E

5

5

5

5

5

5

A

3

40

Y

4

4

9

A

4

4

9

E

4

A

0

126

N

2

C

8

4

A

E

8

4

A

A

0

14

N

9

A

6

5

3

A

F

5

3

A

0

15

N

3

6

3

6

9

6

6

6

9

A

2

24

Y

NYU School of Engineering

Page 59 of 60

CS2204

Handout No : 18

April 17, 2014

The strategy does not check for code digits and so misses to earn code reward points when RD is 7, 2 and 9. However, by chance it earns code reward points when RD is 4.

b) The modified machine player is shown below. DPOS0

K

B0

Z0 8

Y DPOS1

Go

P2sturn

Y0

4

Z

DPOS2 A2

Clearp2ffs Clr B2

Z2 DPOS3

Valid

P2clk clock

Z3

Y1

A1 B1

Z1

4

A3

P2SEL0

Y0

4-bit 2-to-1 MUX

RWD

A0

P2SEL1

Y1 Y2

P2SEL2

Y2 Y3

P2SEL3

Y3

B3

P2add 1

Sel RDisnotzero RD3 E

RD2 RD1

RDisnotzero

P2played

Valid P2sturn

Valid

RD0

P2skip Rightmost DISP 16

Largest

z

I1

Display Position

y

Y0

DPOS0

2-to-4 Y1

DPOS1

I0

DCD

Y2

DPOS2

Y3

DPOS3

msb

Circuit

0

The new signals used are as follows : RD is random digit. The machine player takes five clock periods to play since the Question 3 digital system takes 4 clock periods to collect information and and one clock period to play. NYU School of Engineering

Page 60 of 60

CS2204

Handout No : 18

April 17, 2014