DIGITAL LOGIC & STATE MACHINE DESIGN

SPRING 2014

HOMEWORK II DUE : February 27, 2014 READ : Related portions of Chapters III, IV and VI. ASSIGNMENT : There are eight questions two of which are from the textbook. Solve all homework and exam problems as shown in class and past exam solutions.

1) Consider the following combinational circuit with four inputs and three outputs : a b

K c

msb

Operation Table

z2(a, b, c, d) z1(a, b, c, d)

msb

a 0 0 1 1

Z

z0(a, b, c, d)

d

K is a 2-bit 2’s Complement Binary number Z is a 3-bit 2’s Complement Binary number

b Operation 0 Z=K 2 1 Z=K 0 Z=K+1 1 Z=K-1

(i) Obtain the truth table of the combinational circuit based on the operation table. In a single sentence can you describe what this circuit does, i.e. its purpose ? In order for K to have three bits so that it has the same bits as Z, assume that K has an invisible third (leftmost) bit whose value is obtained via a sign extension on K. Then perform the necessary operation on K. Name this invisible leftmost bit as “e” and show it on your truth table. (ii) Then, obtain the minterm lists of the outputs from the truth table.

2) Consider the combinational circuit below with 8 inputs and 3 sets of outputs. 4

4

K

Combinational Circuit

4

y

K

4-bit ADDer

S

M

A>B A=B AQ outputs. While it can compare 8 bits, it cannot compare 2’s Complement numbers. For example, when K is negative, the comparator interprets it a number between 128 and 255 in decimal. However, checking if the number is negative and bypassing the comparator chip is simple by using an OR gate. The gate output would be the G99 output. The gate would output 1 if K7 is 1 (K is negative), otherwise, its output would depend on the comparator output : K6 K7

K0 K4 K2 K5 K3 K1 0 1 1

P7 P6 P5 P4 P3 P2 P1 P0

0 0 0

1

1

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

74LS682 P=Q

P>Q

G99 NYU School of Engineering

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February 13, 2014

Q2) Consider the following 5-input, 4-output circuit : 4

K

Combinational Circuit

4

K is a 4-bit 2’s Complement Binary number

R

j Its block partitioning is shown below : 4

Increment Circuit

4

0

K 4

Taking 2’s Complement Circuit

Select Circuit (4-bit 2-to-1 Select

4

1

4

R

Circuit)

select

j

Analyze the circuit to obtain its purpose. In order to do that first, obtain the operation table based on the given blocks above. For each block, there is a major operation on the operation table. Based on the major operations derive the textual input-output relationship and then the purpose of the circuit.

A2) The operation table and the blocks are as follows : Input

Operation

j=0

R = (K + 1)

j=1

R=K

2

From the operation table we see that the major operations are (1) incrementing K 2 (that is, K + 1), (2) taking the 2’s complement of K (K) and (3) selecting the output of one of these two operations. Hence, we have one block for each major operation

This circuit is an Arithmetic Unit that increments or negates a 4-bit number input.

Q3) Consider the following 5-input, 4-output circuit and its operation table : K

4

j

Combinational 4 Circuit

K and R are 4-bit 2’s Complement Binary numbers

R

Situation

Operation

j=0

R=K+1

j=1

R=K

2

If K is the max value (7)10 , then R = K + 1 is the min value (-8)10

The following block partitioning is suggested based on the operation table :

NYU School of Engineering

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Handout No : 6

February 13, 2014

4

4

Invert Circuit

Select Circuit

1

K

4

(4-bit 2-to-1 Select

4

Circuit)

0

4-bit ADDer Circuit

4

1

4

R

select

j i) Prove that this partitioning with three blocks is correct. That is, prove that the three blocks implement the operation table. ii) Then, implement the three blocks by using minimum number of high-density TTL LS chips. and generic gates Draw the full circuit by showing all the connections. By using dotted lines, outline the three blocks in your circuit. iii) Mention the high-density TTL chip usage.

A3) i) We know that taking the 2’s complement of a number is the same as complementing it and adding 1. Thus the operation table becomes as follows :

Situation

Operation

j=0

R=K+1

j=1

R=K = K+1

2

a) When j is 0, the MUX selects K which is added 1 by the 4-bit ADDer to generate K + 1 b) When j is 1, the MUX selects K, generated by the invert circuit and a 1 is added by the 4-bit ADDer to generate the other output value K + 1 Thus, the partitioning is correct, it implements the operation table. Note that there is another partitioning given in Past Exam Question 2 above. ii) The implementation of the combinational circuit by using TTL chips is shown below. We use a TTL MUX chip 74LS157 and a TTL ADDer chip 74LS83. The 74LS83 chip is a 4-bit chip with the same functionality as the 74LS283 chip. In addition, we use four generic gates. K3 K2 K1 K0 K3 K2 K1 K0

j NYU School of Engineering

I1d I1c I1b I1a I0d I0c I0b I0a

4-bit 2-to-1 MUX

cin

0

Yd Yc Yb Ya S

0 0 0 1

E

4-bit ADDer

A3 A2 A1 A0

S3 S2 S1 S0

B3 B2 B1 B0

cout

R3 R2 R1 R0

0 Page 6 of 20

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Handout No : 6

February 13, 2014

iii) The chip usage is as follows :

1 74LS157 4-bit 2-to-1 MUX 1 74LS83 4-bit ADDer 4 generic gates 2 TTL chips used. 4 generic gates used

Q4) A combinational circuit compares two 3-bit 2’s complement numbers, K and M. Number K is represented by bits a, b and c. Number M is represented by bits d, e and f. The two active-high outputs, z1 and z0 are for “=” and “