SpW-10X ASIC (AT7910E) Characterisation

Gerald Kempf SpaceWire Presentation Days ESTEC

25th September 2008

Outline Overall Goals Parameters Measured / Analysed Analysis Results Characterisation Board /Measurement Set-up Measurement Results Conclusion

Goals of the Characterisation • Board implementation with SpW-10X • Basic functional test over full operating condition range • Test of PLL over full operating condition range • Characterisation of electrical parameters • Long time test of SpW LVDS links • LVDS modes testing

Parameters Measured • • • • • • •

Power Consumption SpW Link Speed Clock Input Pulse Width and Jitter PLL Function PLL Cold Start SpW D/S Skew and Eye Diagrams LVDS modes and long term function

Parameters Analysed • • • • •

SpW Input D/S Separation Reset Signal Pulse Width and Recovery Time External Port Timing Timecode Interface Timing Error / Status Interface Timing

Results of Analysis (1) •

SpW Rx front-end D – S edge separation: min. 2.06ns -> 3ns for users manual • Reset pulse width: min. 0.71ns -> 5ns for users manual • Reset release till operation: min. 18.67ns -> 20ns for users manual • External port timing for users manual: input setup time: min. 5ns; hold time: min. 5ns output delay from clock: min. 5ns, max. 18ns

Results of Analysis (2) •

Time Code port timing for users manual: input setup time: min. 5ns; hold time: min. 5ns EXTTIMEOUT delay relatively to EXTTICKOUT: ±5ns EXTTICKIN, TIMECTRRST min. high/low time: 1 CLK period + 5ns EXTTICKOUT low time: 3 CLK periods ± 5ns; min. high time: 4 CLK periods ± 5ns • Error / Status interface timing for users manual: output delay from clock: min. 5ns, max. 25ns output delay from STATMUXADDR: min. 3ns, max. 20ns STATMUXOUT input stable for reset: inputs need to be stable from end of reset till 4 CLK periods after end of reset

Characterisation Board

Power Measurement / Connection

Supply

DIP Sw Meas point

DIP Sw

Meas point

Meas point Meas point

TiCode SpW Conn

SpW1

SpW Conn

SpW2

SpW Conn

SpW3

SpW Conn

SpW4

Supply

StMux

TiCode

SpW5

Meas point

SpW6

UUT2 SpW_10X

Meas point

SpW7

Meas point

Supply

StMux

SpW1

SpW5

SpW2

SpW6

UUT1 SpW_10X

SpW3

SpW7

Meas point Meas point Meas point

Jumper SpW8 PLL

EX0

SpW4 Meas point

EX1

SpW8 EX0

Meas point

Setting

PLL

Setting

DIP Sw

30 MHz Clock IF

Meas point

SpW Conn SpW Conn SpW Conn SpW Conn

EX1 Meas point DIP Sw

to all SpW_10X ASICs and FPGA DIP Sw

TiCode SpW Conn

SpW1

SpW Conn

SpW2

SpW Conn

SpW3

SpW Conn

SpW4

Supply

StMux SpW5 Jumper

UUT3 SpW_10X (socket)

Jumper

SpW6

SpW7

PLL

Setting

SpW Conn SpW Conn

SpW8 EX0

Support FPGA

EX1

Reset

to all SpW_10X ASICs and FPGA

SpW Validation SW

DMMs Voltage/Current

Measurement Set-up

Temperature Measurment

Power Supply

USB

Desktop

Test setting / PLL meas.

TiCode

StMux

SpW1

TiCode

SpW5

SpW1

SpW6

SpW2

SpW7

SpW3

SpW8

SpW4

Supply

StMux SpW5 SpW

SpW1

Supply

SpW USB Brick SpW2

SpW2

UUT2 SpW_10X

Sine Wave Generator (30MHz)

SpW4 EX0

adder

Noise

PLL

EX1

SpW8 EX0

PLL/ CLK

EX1

Clock IF

TiCode

Supply

StMux

SpW1

SpW2

High Speed Oscilloscope

SpW7 SpW

SpW3

SpW6

UUT1 SpW_10X

SpW3

SpW5

UUT3 SpW_10X (unpowered)

Support FPGA (not mounted)

SpW6

SpW7

SpW8

SpW4 EX0

PLL

EX1

SpW_10X Char Board

Power Measurements • • • • • • • • •

All measurements are done at -55°C (ambient), 25°C and 125°C All measurements are done at 3.0V and 3.6V supply voltage Dependency on # of active SpW links Dependency on packet transfer Dependency on bit rate of SpW links Static power without clock active Reset active and clock active SpW LVDS driver deactivation Dependency on SpW Tx clock divison (TXDIV)

bitrate [Mbps]

8 SpW ports are active

7 SpW ports are active

6 SpW ports are active

5 SpW ports are active

4 SpW ports are active

3 SpW ports are active

2 SpW ports are active

1 SpW port is active

SpW_10X is idle (no port is active)

total power consumption [W]

P vs. bit rate and # of active SpW 3V6, port offset, active flow, +25°C

3

2.8

2.6

2.4

2.2 200Mbps 100Mbps 10Mbps 2Mbps

2

1.8

1.6

P vs. # of active SpW, packet flow and T 3V6, all ports active

3.1

2.9

total power consumption [W]

2.7

+25°C, no flow +125°C, no flow -55°C, no flow +25°C, active flow +125°C, active flow -55°C, active flow

2.5

2.3

2.1

1.9

1.7 2

10

100 bitrate [Mbps]

200

Power Results • All measurements are done at -55°C (ambient), 25°C and 125°C • Static power without clock active: max. 0.82W • Reset active and clock active: max. 1.32W • SpW LVDS driver deactivation: max. 0.06W / SpW link reduction • Dependency on SpW Tx clock divison (TXDIV): max. 0.3W reduction for 1 to ½ division @ 200MHz PLL max. 0.2W reduction for ½ to ¼ division @ 200MHz PLL • Dependency on supply voltage: measured P at 3.0V was always below 69.4% (resistive model) of measured P at 3.6V

Power Model has been made and included in SpW-10X Users Manual

Link Speed Measurements • • •

All measurements are done at -55°C (ambient), 25°C and 125°C All measurements are done at 3.6V supply voltage All measurements are done for 200Mbps, 100Mbps, 10Mbps and 2Mbps • Period of SpW bits are measured and checked for length • One Packet is looping and it is checked that another packet at another SpW link does not influence the looping packet

Link Speed Results •

Periods at all data rates are OK • Packets are not influenced by packets at other SpW links Example (200Mbps, 25°C): SpW1(Rx) to SpW2(Tx) looping packet, start of a packet transmitted from SpW1

Clock Input Measurements • • •

All measurements are done at -55°C (ambient), 25°C and 125°C All measurements are done at 3.0V and 3.6V supply voltage Noise is added to sinusodial clock signal, which converts to jitter at the comparator on the board • DC offset is added to sinusodial clock signal, which converts to pulse width changes at the comparator on the board • 30MHz clock from signal generator was used as trigger (reference)

Clock Input Pulse Width Results •

PLL is the limitting device for clock pulse width • Oscilloscope Waveforms: SYN1 sync signal Clk30 (UUT1) PLL_FB (UUT1) PLL_LCK (UUT1) • Measurements show limit at pulse width of 3.5ns • 5ns for users manual

Clock Input Jitter Results •

PLL is very robust to clock jitter • Functional interruption due to to short clock periods before PLL fails to lock • Oscilloscope Waveforms: SYN1 sync signal Clk30 (UUT1) SpW1 Din+ (UUT1) SpW2 Dout+ (UUT1) • Measurements show limit at jitter of 3.8ns • 2ns for users manual

Clock Input Jitter Results • •

•

PLL is very robust to clock jitter Single missing clock pulses are only causing short distortions in PLL Oscilloscope Waveforms: SYN1 sync signal Clk30 (UUT1) PLL_FB (UUT1) PLL_LCK (UUT1)

PLL Locking Time Results •

Measured at all PLL frequencies • Measured from PLL Reset till PLL lock • Oscilloscope Waveforms: PLL_LCK (UUT1) PLL:RST (UUT1) • Max. lock time measured 10.4µs (20 measurements for each setting) • Users manual value max. 20µs

SpW Tx D / S Skew and Eye Diagrams • • • •

• • •

All measurements are done at -55°C (ambient), 25°C and 125°C All measurements are done at 3.0V and 3.6V supply voltage All measurements are done for 200Mbps, 100Mbps, 10Mbps and 2Mbps D / S at SpW-10X outputs are connected to oscilloscope with coaxial cables (21:1 probe bouilt onto the board) and differential signal computed with oscilloscope 30MHz clock from signal generator was used as trigger (reference) 2 different data patterns (packets) were sent for each measurement to cover all D / S edge combinations Persistant mode of oscilloscope with a duration of >10s for each pattern

SpW Tx D / S Skew Results •

•

•

SpW standards has an example for 200Mbps: budget assumes SpW Tx skew and jitter max. 1.22ns Measurements show total skew and jitter of SpW Tx: max. 1.19ns 1.2ns for users manual

SpW Tx D / S Eye Diagrams •

Big variation in the eye diagrams depending on the structure of the SpW LVDS connection (straight PCB connection, Via SpW connector and SpW cable, with jumpers and ‚dead ends‘) • Example: SpW2, 3.6V, 25°C, 200Mbps

SpW Tx D / S Eye Diagrams •

•

•

Worst case: SpW1, 3.6V, -55°C, 200Mbps There is negative margin (signal crossing 0V line) at one measurement No error occured at SpW link during this measurement Additional long term measurement added to check function

SpW LVDS Long Term Measurements • • •

All measurements are done at -55°C (ambient) / 3.6V and 125°C / 3.0V All measurements lasts for at least 24 hours Two scenarios are measured: ¾ 1. Full operation of SpW-10X with packets flowing through all SpW links at 200Mbps ¾ 2. SpW-10X SpW link with failsave resistors connected to a SpW-10X SpW LVDS output at deactivated mode

•

Success criteria: ¾ 1. No error occurs at any SpW LVDS link of UUT1 ¾ 2. No wrong NULL is detected at the SpW receiver of the link connected to deactivated SpW LVDS drivers

•

Results: ¾ 1. No error has occured at any measurement ¾ 2. No wring NULL has been detected

SpW LVDS Modes • •

All measurements are done at 25°C (ambient) / 3.3V Test the Function of all LVDS driver modes: ¾ Active driver ¾ Deactivated driver ¾ Unpowered driver (cold sparing)

• •

Each mode was measured at a LVDS link with and an LVDS link without failsave resistors Results: ¾ All operarational modes are as expected (current/voltage measurements) ¾ Both with and without failsave resistors ¾ Deactivated mode has a special behaviour, where both LVDS outputs are connected to positive supply via resistors (~2850 Ω)

Conclusion • All Parameters wanted from Analysis / Measurement could be obtained • No Problem / malfunction has been found during the activity • Board design with the SpW-10X ASIC has no particular difficulties • Information has been included into the SpW-10X documentation