ALLAH

SHAHED University Faculty of Engineering

Advanced Logic Design Class project report

ASIC Design of SAYEH processor

Student:

Alireza Haghdoost 832161014

Professor:

Dr. Bijan Alizadeh

Spring 2008 Page 1

Table of Contents 1. Introduction

2

2. SAYEH Architecture

2

3. SAYEH HDL Design

4

4. SAYEH Simulation

22

5. SAYEH ASIC Synthesis

26

6. References

36

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1. Introduction In this project I try to redesign SAYEH processor and synthesis it using TSMC 0.25um ASIC technology after design simulation. This document comes with brief introduction into SAYEH architecture then I have describe designing basic blocks of processor using Verilog HDL, in Section 4 simulation phase discussed and in section 5 synthesis phase described, at the end I could achieve into 64MHz clock frequency after four times of timing optimization.

2. SAYEH Architecture The SAYEH is a simple CPU that has been designed for educational and benchmarking purpose. Relying on the material of the computer architecture course provide the necessary background for understanding details of the hardware of SAYEH in this work. SAYEH has a register file that is used for data processing instructions. The CPU has a 16-bit data bus and a 16-bit address bus also 16-bit instruction set architecture. Figure 2.1 shows SAYEH interface signals.

Figure 2.1: SAYEH Interface

When the memory instructions executed the processor issues ReadMem or WriteMem signals to the memory. SAYEH components that are used by its instructions include the standard registers such as the Program Counter, Instruction Register, the Arithmetic Logic Unit, and Status Register. In addition, this processor has a register file forming registers R0, R1, R2 and R3 as well as a Window Pointer that defines R0, R1, R2 and R3 within the register file. CPU components and a brief description of each are shown below. PC: Program Counter, 16 bits R0, R1, R2, and R3: General purpose registers, 16 bits, the general purpose registers form a window of 4 in a register file of 64 registers WP: Window pointer, 6 bits IR: Instruction register, 16 bits ALU: The ALU that can add, subtract and multiply its inputs. Z flag: Becomes 1 when the ALU output is 0. C flag: Becomes 1 when the ALU has a carry output. DR: Data register for holding intermediate or temporary values, 16 bits

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2.1. SAYEH Instructions

The general format of 16-bit SAYEH instructions is shown in Figure 2.2, instructions have 8-bit Immediate field. The OPCODE filed is a 4-bit code that specifies the type of instruction. The Left and Right fields are two bit codes selecting R0 through R3 for source and/or destination of an instruction. Usually, Left is used for destination and Right for source. The Immediate filed is used for immediate data, or is used for the second instruction OPCODE extension.

Figure 2.2: SAYEH Instruction Format

Our processor has a total of 18 instructions as shown in Figure 2.3. Instructions that use the Destination and Source fields (designated by D and S in the table of instruction set) have an opcode that is limited to 4 bits. Instructions that do not require specification of source and destination registers use these fields as opcode extensions. In the instruction set, addressed locations in the memory are indicated by enclosing the address in a set of parenthesis.

Figure 2.3: Instruction Set of SAYEH

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2.2. SAYEH Datapath The datapath of SAYEH is shown in figure 2.4

Figure 2.4: SAYEH Datapath

3. SAYEH HDL Design In this section I will describe all the detail in HDL design of SAYEH processor in RTL level. SAYEH was developed in University of Tehran under maintained of Prof.Navabi and its HDL codes (Verilog and VHDL) is available in Prof.Navabi’s books [1] and Dr.Afshar book [2], the codes which is published in Dr.Navabi’s book used newer architecture with extra features but the code which is published in Dr.Afshar’s book describe the first release architecture of SAYEH as we mentioned in section 2. by the way because the codes published in Dr.Afshar’s book uses different design strategy and have errors in the first release of SAYEH, I couldn’t use it. So I try to design SAYEH from scratch but using the design strategy which is mentioned in Dr.Navabi’s book. [1] Zein Navabi, “Digital Design and Implementation with Field programmable Arrays”, Springer 2004. [2] Hadi Parandeh Afshar “ Verilog, Digital Circuit Design” Spring 1383, Nass publisher [Farsi]

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Addressing Unit The addressing unit showed in figure 2.4 consist of the Program Counter (Listing 2) and Address Logic (Listing 3), the program counter is a simple register and the Addressing Logic is a small arithmetic unit that perform adding and incrementing for calculating PC or memory address. Addressing unit code shows in Listing 1. 3.1.

module Addressingunit( Rside, Iside, clk , PCplusI , PCplus1, R0plusI , ResetPC , Address); input [15:0] Rside; input [7:0] Iside; input clk; input PCplusI, PCplus1, R0plusI, ResetPC; // Controlling signals output [15:0] Address; wire [15:0] PCout; wire [15:0] Address_feedback; assign Address = Address_feedback; PC pc_ins ( .clk(clk), .in(Address_feedback), .out(PCout) ); Addresslogic al ( .R0side(Rside), .PCside(PCout), .Iside(Iside), .PCplusI(PCplusI), .PCplus1(PCplus1), .R0plusI(R0plusI), .ALout(Address_feedback), .ResetPC(ResetPC)); endmodule

Listing 1: HDL description of Addressing Unit

`timescale 10ns/1ns module PC( in, clk, out); input clk; input [15:0] in; output [15:0] out; reg [15:0] out; always@( posedge clk ) out