Review: Computer Organization The Processor: Datapath and Control

Chansu Yu

Implementation of the MIPS


We're ready to look at an implementation of the MIPS
Simplified to contain only:


memory-reference instructions: lw, sw
arithmetic-logical instructions: add, sub,
control flow instructions: beq, j

and, or, slt


Generic Implementation:


use the program counter (PC) to supply instruction address
get the instruction from memory
read registers
use the instruction to decide exactly what to do 2 [email protected]

1

Datapath of a Processor


Datapath


All necessary data connection among the building blocks Registers Number (input)

Memory (4GB) A L U

Data (output)

Data (input)

Address (input) Data (input)

Data (output)


How many bits for each connection ? 3 [email protected]

Register File, ALU and Memory MemWrite 5 Register numbers

5 5

Data

3

Read register 1

Read data 1 Read register 2 Registers Write register Read data 2 Write data

ALU control

Read data

Address ALU

Data

Zero ALU result

Write data

Data memory

MemRead

RegWrite a. Registers

  

b. ALU

a. Data memory unit

Why register block has three inputs for register number and two outputs for register data ? ALU output can be fed into





Register block as a data input : Why ? And why not register number input ? Memory block as an address : Why ? And why not data input ?

What if it is not load/store architecture




add $s0, $s1, 96($t0)

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2

Ex: lw $16, 100($8)

8

Registers read reg. no. 1 read reg. no. 2 write reg. no.

16

reg. data 1

reg. data 2

Memory (4GB) A L U

write reg. data

Address

Writing Data

Read Data

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Ex: sw $16, 100($8)

8

16

Registers read reg. no. 1 read reg. no. 2 write reg. no.

reg. data 1

reg. data 2

Memory (4GB) A L U

write reg. data

Address

Writing Data

Read Data

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3

Ex: add $16, $17, $18

17 18 16

Registers read reg. no. 1 read reg. no. 2 write reg. no.

reg. data 1

reg. data 2

Memory (4GB) A L U

write reg. data

Address

Writing Data

Read Data

⇒

Memory is “not” used at all !!! Load/store architecture: memory access is allowed only on load/store instruction

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Ex: add $16, $17, 100($18)

Registers read reg. no. 1 read reg. no. 2 write reg. no.

reg. data 1

reg. data 2

Memory (4GB) A L U

write reg. data

Address

Writing Data

Read Data

If the above instruction is a legitimate one, how to connect the blocks to implement it?

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4

Input/Output for the Blocks


Consider instructions: “previous four slides”
lw $s0, 96($t0)
sw $t3, 4($s2)
add $s0, $s1, $s2


MIPS addressing: “next slide”


96($t0) = 96 + $t0
new $pc = old $pc + 4
new $pc = old $pc + immediate (PC-relative addressing)


All instructions use the ALU after reading the registers

Why? memory-reference? arithmetic? control flow?

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Instruction Memory, PC, Adder

PC

Instruction address Instruction Instruction memory

b. Program counter a. Instruction memory

Add Sum

4 or 16-bit offset if branch c. Adder instruction

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5

Implementation Details


Abstract / Simplified View: Data Register # PC

Address

Instruction

Registers

ALU

Address

Register #

Instruction memory

Data memory

Register # Data


Two types of functional units:


elements that operate on data values (combinational)
elements that contain state (sequential) 11 [email protected]

Register File

 Built using D flip-flops (read)

(write) Write

Read register number 1

0 Register 0 Register 1 Register n – 1

M u x

Register number

Read data 1

Register 0 D

n-to-1 decoder

C

n– 1

Register n

C

1

Register 1 D

n Read register number 2

M u x

C Register n – 1 D

Read data 2

C Register n Register data

D

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6

Register File

Read register number 1

Read data 1

Read register number 2 Write register

Register file

Write data

Read data 2

Write

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All Functional Units

Instruction address

MemWrite

Instruction

PC

Add Sum

Address

c. Adder

Write data

Read data 16

Instruction memory a. Instruction memory

b. Program counter

Data memory

Sign extend

32

MemRead a. Data memory unit

5

Register numbers

5 5

Data

Read register 1

4

ALU operation

Read data 1

Read register 2 Write register

b. Sign-extension unit

Data

Registers

Zero ALU ALU result

Read data 2

Write Data

RegWrite a. Registers

b. ALU

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7

Datapath with Multiplexers PCSrc M u x

Add Add ALU result

4 Shift left 2

PC

Read address Instruction Instruction memory

Registers Read register 1 Read Read data 1 register 2 Write register Write data RegWrite 16

ALUSrc

Read data 2

Sign extend

M u x

3 ALU operation Zero ALU ALU result

MemWrite MemtoReg

Address

Read data

Data Write memory data

M u x

32 MemRead

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The Big Picture


The Five Classic Components of a Computer Processor Input Control Memory Datapath

Output


Datapath & Control 16 [email protected]

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Datapath and Control  Datapath

 Between memory, ALU, register file  When a 32-bit instruction is ready    

It is decoded to obtain opcode, register numbers, … Register numbers go to register file and the register values become ready Immediate value becomes ready Memory data is read and ready

 Control

 Need to decide which inputs should be used (multiplexors)  ALU control such as operation, binvert, carryIn, …  Write signal (register write, memory write) 17 [email protected]

Generation of Control Signals 32-bit instruction

6-bit opcode

Control Logic

9 control signals

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9

Multiplexer Selector add $8, $17, $18 000000 op

10001 10010 rs

01000

rt

Register file

rd

lw $1, 100($2) 00000 100000 shamt

110101 00010

funct

op

00001

rs

rt

0000 0000 0110 0100 16 bit offset

Register file

Register file

ALU

ALUSrc ALU

Memory

RegDst

Register file

Register file

MemtoReg

In case of “sw” 1

⇒ ⇒X (don’t care) ⇒X (don’t care)

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One More Multiplexor Selector

0 PC ADD

4

ADD

1

S.E.(16-bit) need some time to be stabilized => this will be the longest path (critical path) => determines the clock cycle for the CPU 25 [email protected]

ALU Control


What should the ALU do with this instruction ?


Information comes from the 32 bits of the instruction
ALU's operation based on instruction type and function code


Multi-level control (for simplifying control logic)
Instruction’s opcode (bit31-bit26)

=> ALUOp1 & ALUOp0 (with instruction’s funct (bit4-bit0)) => ALU inputs: binvert (= carryin), operation 26 [email protected]

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Control Signals (9) 0 M u x ALU Add result Add 4 Instruction [31– 26]

Control

Instruction [25– 21] Instruction [20– 16] Instruction [31– 0] Instruction memory

Instruction [15– 11]

ALUOp MemWrite ALUSrc RegWrite Read register 1

Read address

PC

1

Shift left 2

RegDst Branch MemRead MemtoReg

0 M u x 1

Read data 1 Read register 2 Registers Read Write data 2 register

0 M u x 1

Write data

Zero ALU ALU result

Write data 16

Instruction [15– 0]

Sign extend

Read data

Address

Data memory

1 M u x 0

32 ALU control

Instruction [5– 0]

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Single Cycle Implementation


Single Cycle Problems:


what if we had a more complicated instruction like floating


point? wasteful of area (duplicated function blocks)


One Solution:


use a “smaller” cycle time
have different instructions take different numbers of cycles
a “multicycle” datapath 28 [email protected]

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Multicycle Approach


Break up the instructions into steps, each step takes a cycle
balance the amount of work to be done
restrict each cycle to use only one major functional unit


At the end of a cycle


store values for use in later cycles (easiest thing to do)
introduce additional “internal” registers

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Breaking down an instruction


ISA definition of arithmetic: Reg[Memory[PC][15:11]]