Very Simple MIPS Implementation
mips-hw-1
mips-hw-1
mips-hw-1
Very Simple (VS) MIPS Implementation Goal is to share as much hardware as possible. Goal is to be simple. Good for illustrating datapath and control hardware. With relatively minor changes VS MIPS can be made into a practical design.
EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
mips-hw-1
mips-hw-2
mips-hw-2
Very Simple Implementation opcode 31:26 enpc
epc
en
en
NPC
mips-hw-2
omem xma
func 5:0
op
Mem Port
PC
addr
data
eir
rs 25:21 en
md
data in
IR
rt 20:16
xrwr
xalu1 to control logic
Reg File addr addr
data data
oalu op
rsv
alu
rtv
rd 15:11 5d0
5d31
addr data in 32d4
imm 15:0
prepare imm
xrws
xalu2
uimm simm limm bimm
Datapath components in black. Control signals in blue. Control signals set by control logic. Warning: This implementation impractically slow.
EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
mips-hw-2
mips-hw-3
mips-hw-3
Control for add Instruction opcode 31:26 enpc
epc
en
NPC
mips-hw-3
en
omem xma
PC
func 5:0
op
Mem Port addr
data
eir
rs 25:21 en
md
xrwr
Reg File addr
rt 20:16
IR
xalu1 oalu
to control logic
addr
data data
op
rsv
alu
rtv
rd 15:11
data in
5d0
addr
5d31
data in 32d4 uimm simm limm bimm
prepare imm
imm 15:0 xrws
State SubSt IF ID add NI
xma pc
omem rd32
eir 1
xalu1
xalu2
oalu
xrwr xrws
rsv npc
rtv 4
add add
rd
enpc epc
alu
EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
xalu2
1
1
Next ID NI IF
mips-hw-3
mips-hw-4
mips-hw-4
Control for sub Instruction opcode 31:26 enpc
epc
en
NPC
mips-hw-4
en
omem xma
PC
func 5:0
op
Mem Port addr
data
eir
rs 25:21 en
md
xrwr
Reg File addr
rt 20:16
IR
xalu1 oalu
to control logic
addr
data data
op
rsv
alu
rtv
rd 15:11
data in
5d0
addr
5d31
data in 32d4 uimm simm limm bimm
prepare imm
imm 15:0 xrws
State SubSt IF ID sub NI
xma pc
omem rd32
eir 1
xalu1
xalu2
oalu
xrwr xrws
rsv npc
rtv 4
sub add
rd
enpc epc
alu
EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
xalu2
1
1
Next ID NI IF
mips-hw-4
mips-hw-5
mips-hw-5
Control for addi Instruction opcode 31:26 enpc
epc
en
NPC
mips-hw-5
en
omem xma
PC
func 5:0
op
Mem Port addr
data
eir
rs 25:21 en
md
xrwr
Reg File addr
rt 20:16
IR
xalu1 oalu
to control logic
addr
data data
op
rsv
alu
rtv
rd 15:11
data in
5d0
addr
5d31
data in 32d4 uimm simm limm bimm
prepare imm
imm 15:0 xrws
State SubSt IF ID addi NI
xma pc
omem rd32
eir 1
xalu1
xalu2
oalu
xrwr xrws
rsv npc
simm 4
add add
rt
enpc epc
alu
EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
xalu2
1
1
Next ID NI IF
mips-hw-5
mips-hw-6
mips-hw-6
Control for lw Instruction opcode 31:26 enpc
epc
en
en
NPC
mips-hw-6
omem xma
PC
func 5:0
op
Mem Port addr
data
eir
rs 25:21 en
md
xrwr
Reg File addr
rt 20:16
IR
xalu1 oalu
to control logic
addr
data data
op
rsv
alu
rtv
rd 15:11
data in
5d0
addr
5d31
data in 32d4 uimm simm limm bimm
prepare imm
imm 15:0 xrws
State SubSt IF ID lw NI
xma pc alu
omem rd32 rd32
eir 1
xalu1
xalu2
oalu
xrwr xrws
rsv npc
simm 4
add add
rt
xalu2
enpc epc
md 1
1
Next ID NI IF
The lw instruction reveals a weakness in this design. . . . . . ID takes much longer for lw than for add and other instructions. . . . . . forcing the clock frequency to be slower than it has to be. (Nevermind for now.)
EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
mips-hw-6
mips-hw-7
mips-hw-7
Control for lb Instruction opcode 31:26 enpc
epc
en
en
NPC
mips-hw-7
omem xma
PC
func 5:0
op
Mem Port addr
data
eir
rs 25:21 en
md
xrwr
Reg File addr
rt 20:16
IR
xalu1 oalu
to control logic
addr
data data
op
rsv
alu
rtv
rd 15:11
data in
5d0
addr
5d31
data in 32d4 uimm simm limm bimm
prepare imm
imm 15:0 xrws
State SubSt IF ID lb NI
xma pc alu
omem rd32 rd8s
eir 1
xalu1
xalu2
oalu
xrwr xrws
rsv npc
simm 4
add add
rt
xalu2
enpc epc
md 1
1
Next ID NI IF
The work of sign-extending or padding the loaded value is done by the memory port.
EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
mips-hw-7
mips-hw-8
mips-hw-8
Control for sb Instruction opcode 31:26 enpc
epc
en
NPC
mips-hw-8
en
omem xma
PC
func 5:0
op
Mem Port addr
data
eir
rs 25:21 en
md
rt 20:16
IR
xrwr
xalu1 oalu
to control logic
Reg File addr addr
data data
op
rsv
alu
rtv
rd 15:11
data in
5d0
5d31
addr data in 32d4
imm 15:0
uimm simm limm bimm
prepare imm
xrws
State SubSt IF ID sb NI
xma pc alu
omem rd32 wr8s
eir 1
xalu1
xalu2
oalu
rsv npc
simm 4
add add
xrwr xrws
EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
xalu2
enpc epc
1
1
Next ID NI IF
mips-hw-8
mips-hw-9
mips-hw-9
Control for beq Instruction opcode 31:26 enpc
epc
en
NPC
mips-hw-9
en
omem xma
PC
func 5:0
op
Mem Port addr
data
eir
rs 25:21 en
md
rt 20:16
IR
xrwr
xalu1 to control logic
Reg File addr addr
data data
oalu op
rsv
alu
rtv
rd 15:11
data in
5d0
5d31
addr data in 32d4
imm 15:0
uimm simm limm bimm
prepare imm
xrws
State SubSt IF ID beq BT beq NI
xma pc
omem rd32
eir 1
xalu1
xalu2
oalu
rsv npc npc
rtv bimm 4
seq add add
xrwr xrws
EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
xalu2
enpc epc
1 1
1 1
Next ID NI or BT IF IF
mips-hw-9
ips-hw-10
ips-hw-10
mips-hw-1
Control Logic Design Lets collect the control signals we’ve decided so far: State IF BT NI ID ID ID ID ID ID ID
SubSt
add sub addi lw lb sb beq
xma pc
alu alu alu
omem rd32
rd32 rd8s wr8s
eir 1
xalu1
xalu2
oalu
npc npc rsv rsv rsv rsv rsv rsv rsv
bimm 4 rtv rtv simm simm simm simm rtv
add add add sub add add add add seq
xrwr xrws
enpc epc 1 1
rd rd rt rt rt
alu alu alu md md
1 1
Next ID IF IF NI NI NI NI NI NI NI
Notice that IF, BT, and NI states were all identical . . . . . . but ID varies depending on the instruction.
EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
mips-hw-1
ips-hw-11
ips-hw-11
mips-hw-1
Control Logic Design The State Register We’ll need a register to hold the current state. Since there are four states we can use a two-bit register. Possible state encoding: IF = 0, ID = 1, . . .. In diagrams we will use names, such as IF, instead of encoded values, such as 0. Next-State Logic There will be combinational logic to determine the next state. Next state is computed in terms of. . . . . . current state, opcode, and for branches the ALU output.
EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
mips-hw-1
ips-hw-12
state
ips-hw-12
mips-hw-1
Control Logic for State IF
ID NI
ID
BT
BT
IF opcode
Magic Cloud
next_state
Some Control Logic
NI
IF
alu
IF
0
ID
0
enpc
BT
1
NI
1
xalu1
opcode 31:26 enpc
epc
en
en
NPC
PC
omem xma
func 5:0
op
Mem Port addr data in
data
eir
rs 25:21 en
md
IR
rt 20:16
xrwr
oalu
Reg File addr
data
addr
data
op
rsv
alu
rtv
rd 15:11 5d0
5d31
addr data in 32d4
imm 15:0 xrws
prepare imm
xalu2
uimm simm limm bimm
Note: Magic Cloud checks for a taken branch. EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
mips-hw-1
Control Logic Design
ips-hw-13
ips-hw-13
mips-hw-1
Logic for the enpc signal. State IF BT NI ID ID ID ID ID ID ID
SubSt
add sub addi lw lb sb beq
xma pc
alu alu alu
omem rd32
rd32 rd8s wr8s
eir 1
xalu1
xalu2
oalu
npc npc rsv rsv rsv rsv rsv rsv rsv
bimm 4 rtv rtv simm simm simm simm rtv
add add add sub add add add add seq
xrwr xrws
enpc epc 1 1
rd rd rt rt rt
alu alu alu md md
1 1
Next ID IF IF NI NI NI NI NI NI NI
Notice that enpc is 1 in BT and NI and 0 in the other states. So we need logic with an output of 1 for those two states. An easy way to do that is a mux, we’ll rely on the synthesis program to streamline the logic.
EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
mips-hw-1
ips-hw-14
Some Control Logic
state
ips-hw-14
mips-hw-1
IF
ID NI
ID
BT
BT
IF opcode
Magic Cloud
next_state
Some Control Logic
NI
IF
alu
IF
0
ID
0
enpc
BT
1
NI
1
xalu1
opcode 31:26 enpc
epc
en
en
NPC
PC
omem xma
func 5:0
op
Mem Port addr data in
data
eir
rs 25:21 en
md
IR
rt 20:16
xrwr
oalu
Reg File addr addr
op
rsv
data
alu
rtv
data
rd 15:11 5d0
5d31
addr data in 32d4
imm 15:0 xrws
prepare imm
xalu2
uimm simm limm bimm
EE 3755 Lecture Transparency. Formatted 8:19, 4 December 2013 from mips-hw.
mips-hw-1
