Computer Architecture and Organization

Chapter 5 - Datapath and Control 5-1 Computer Architecture and Organization Miles Murdocca and Vincent Heuring Chapter 5 – Datapath and Control Co...
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Chapter 5 - Datapath and Control

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Computer Architecture and Organization Miles Murdocca and Vincent Heuring

Chapter 5 – Datapath and Control

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Chapter Contents 5.1 Basics of the Microarchitecture 5.2 The Datapath 5.3 The Control Section – Microprogrammed 5.4 The Control Section – Hardwired 5.5 Case Study: The VHDL Hardware Description Language 5.6 Case Study: What Happens when a Computer Boots Up?

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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The Fetch-Execute Cycle • The steps that the control unit carries out in executing a program are: (1) Fetch the next instruction to be executed from memory. (2) Decode the opcode. (3) Read operand(s) from main memory, if any. (4) Execute the instruction and store results, if any. (5) Go to step 1.

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

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Chapter 5 - Datapath and Control

High Level View of Microarchitecture • The microarchitecture consists of the control unit and the programmer-visible registers, functional units such as the ALU, and any additional registers that may be required by the control unit.

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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A More Detailed View

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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ARC Instruction Subset

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

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ARC Instruction Formats

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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ARC Datapath

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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ARC ALU Operations

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Block Diagram of ALU

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Gate-Level Layout of Barrel Shifter

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

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Chapter 5 - Datapath and Control

Truth Table for (Most of the) ALU LUTs

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Design of Register %r1

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Outputs to Control Unit from Register %ir

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

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Chapter 5 - Datapath and Control

Microarchitecture of the ARC

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Microword Format

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Settings for the COND Field of the Microword

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

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Chapter 5 - Datapath and Control

DECODE Format for Microinstruction Address

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

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Chapter 5 - Datapath and Control

Timing Relationships for the Registers

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

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Chapter 5 - Datapath and Control

Partial ARC Microprogram

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

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Chapter 5 - Datapath and Control

Partial ARC Microprogram (cont’)

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Translating the Microprogram 0: R[ir] ← AND(R[pc],R[pc]); READ;

1: DECODE; /256-way jump according to opcode

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Branch Decoding • Decoding tree for branch instructions shows corresponding microprogram lines:

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

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Chapter 5 - Datapath and Control

Assembled ARC Microprogram

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

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Chapter 5 - Datapath and Control

Assembled ARC Microprogram (cont’)

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

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Chapter 5 - Datapath and Control

Example: Add the subcc Instruction • Consider adding instruction subcc (subtract) to the ARC instruction set. subcc uses the Arithmetic format and op3 = 001100.

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Branch Table • A branch table for trap handlers and interrupt service routines:

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Microprogramming vs. Nanoprogramming

(a) Microprogramming, (b) nanoprogramming.

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Hardware Description Language • HDL sequence for a resettable modulo 4 counter.

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Circuit Derived from HDL • Logic design for a modulo 4 counter described in HDL.

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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HDL for ARC • HDL description of the ARC control unit.

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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HDL for ARC (cont’)

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

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Chapter 5 - Datapath and Control

HDL ARC Circuit • The hardwired control section of the ARC: generation of the control signals.

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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HDL ARC Circuit (cont’) • Hardwired control section of the ARC: signals from the data section of the control unit to the datapath.

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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Case Study: The VHDL Hardware Description Language • The majority function. a) truth table, b) AND-OR implementation, c) black box representation.

Computer Architecture and Organization by M. Murdocca and V. Heuring

© 2007 M. Murdocca and V. Heuring

Chapter 5 - Datapath and Control

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VHDL Specification Interface specification for the majority component -- Interface entity MAJORITY is port (A_IN, B_IN, C_IN: in BIT F_OUT: out BIT); end MAJORITY; Behavioral model for the majority component -- Body architecture LOGIC_SPEC of MAJORITY is begin -- compute the output using a Boolean expression F_OUT

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