Outline Low-Noise and Low-Voltage Circuit Techniques for CMOS Analog Design

1. Introduction 2. Basic concept ・Low-voltage technique ・Low-noise technique 3. Low-noise amplifier 4. Low-voltage SA ADC 5. Summary

Takeshi Yoshida, Yoshihiro Masui, Mamoru Sasaki, Atsushi Iwata

Hiroshima University 1

2

Introduction

Issues of CMOS analog design CMOS analog switch

CMOS technology innovation

Disadvantage ・Power supply voltage reduction -Analog switch issue -S/N deterioration ・Vth variation ・1/f noise

2.0 1.5

2005

1.0 0.5

Vthn

ITRS2005: Low operating power Low standby power 2007 2005

Vout Load

Vthp

Power supply 2010

2014

2017

voltage 0.0 Threshold 2 10 Process technology [nm]

Vg time

Vss

2010 2014 2017 2007

MOSFET operating in the saturation region Ibias+Inoise

Vin

1

10

3

Switch conductance [A.U.]

・High-speed operation ・Lower power consumption ・Shrinking chip area

Power supply, Threshold voltage [V]

Advantage

1/f noise

Vdd

NMOS ‘ON’

PMOS ‘ON’

Large 1/f-noise

‘OFF’ OFF’ gds_nmos

Vss

Vdd-Vthn

G

gds_pmos

Vss-Vthp

Vdd

S Vin

Input voltage Vin [V]

Objectives

n+

trap de-trap D n+

channel

4

Outline

Proposals for low-voltage and low-noise circuit techniques to realize a CMOS analog design in a state of the art process technology. •Noise reduction

•Autozeroing •Chopper stabilization

•Low voltage

•Switched op-amp •Grounded switch •Rail-to-rail signal swing5

1. Introduction 2. Basic concept ・Low-voltage technique ・Low-noise technique 3. Low-noise amplifier 4. Low-voltage SA ADC 5. Summary 6

Grounded switch

Outline Grounded switch

Vdd

Vgs=Vdd

Op-amp

Vout

Vin

1. Introduction 2. Basic concept ・Low-voltage technique ・Low-noise technique 3. Low-noise amplifier 4. Low-voltage SA ADC 5. Summary

Gnd

Vdd

φ

Vgs=Vdd Gnd Vdd

Cload

φ

Output of switched op-amp is implemented using grounded switches.

Vss

Op-amp output stage

Grounded switch can function properly when Vdd