ECE 520 Class Notes
Introduction to CMOS Design Dr. Paul D. Franzon Outline 1. CMOS Transistors 2. CMOS cell design 3. Transistor Sizing 4. Low Power Design References l Smith and Franzon, Chapter 11 l Weste and Eshraghian, Principles of CMOS VLSI Design, A Systems Perspective 1
© 2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
ECE 520 Class Notes
CMOS Transistors Gate
1. nMOS Transistor
Polysilicon Conductor Silicon Oxide Gate
Drain Source n
W
n p substrate
Gate
Drain
Gate
L
Source
Drain
Source
substrate
© 2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Transistors Gate
2. pMOS transistor:
Silicon Oxide Gate Drain Source p
W
p n substrate
Gate
Drain
Gate
L
Source
Drain
Source
substrate
© 2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
MOS Transistor Theory Transistor States: 1. Cutoff Region Ids = 0 when Vgs < Vt Vt = Threshold Voltage (typically 1 V for nMOS, - 1V for pMOS) 2. Linear Region Ids = Β ((Vgs - Vt)Vds - Vds2/2) when 0 < Vds < Vgs - Vt Β=(µε/tox)(W/L) W = channel width L = channel length µ = electron (n) / hole (p) mobility ε = permittivity of gate insulator tox = gate insulator (oxide) thickness © 2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
... nMOS Transistor Theory .... Transistor States 3. Saturatation Region Ids = Β (Vgs - Vt)2 when 0 < Vgs - Vt < Vds Q: Draw a large signal equivalent model for transistor in Linear and Saturation States:
Transistor Characteristics:
5
© 2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
ECE 520 Class Notes
Transistor Characteristics V-I Characteristics: |Ids| |Vgs|
|Vds| © 2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
CMOS Inverter Static CMOS Inverter:
5V Vin
Vout 0V
What are the transistor states when: Vin = 0 V Vin = 2 V Vin = 3 V Vin = 5 V given |Vt| = 1 V © 2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Transistor Speed is determined by SIZE CMOS circuit speeds can be modeled to a first approximation as RC delays: 1. What does the input of a CMOS gate `look like’? C in = 2. What does the `output’ of a CMOS gate `look like’ during switching? Rn = Rp = 3. Usually hole mobility is half of electron mobility. So what must you do to make the pull up and pull down delays about the same? 4. If a gate is heavilly loaded what must you do to speed up the delay?
© 2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Other Gate Designs Refer to data sheets in CMOSX library: l NAND gate l NOR gate l D Flip Flop Analyse the circuits to determine `how these gates work’. Exercise in transistor sizing:
© 2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Power Consumption Why is power consumption important? l Battery powered devices
l Maximize battery life
l Minimize cost of wall-powered systems
l Plastic packaging is 10x cheaper than ceramic packaging but can only dissipate 1 - 2 W u What happens if the chip gets too hot?
l Need a fan to cool somewhere above 10 W l Difficult to air cool at all somewhere above 50 W l Cost of power supply
l `Green’ systems
l Minimize pollution by reducing demand from power stations
© 2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Power Consumption in Digital Electronics Bipolar Circuits:
l Always draw DC current l Average current per gate high l Gate layout area larger than CMOS CMOS Circuits:
l Static CMOS draws current only when it changes state u u u u
l
When input = Vcc, nMOS transistor off When input = GND, pMOS transistor off Gate load = capacitor, no current load Reverse current through backbiased pn junction to substrate is small unless Vcc is very small u `through’ current small during switching Derive power consumption for CMOS:
© 2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Minimizing Power Consumption Power consumption in a CMOS module: Power = Σ Nswitch f Vcc2 Cload
l l l l
Sum over all nodes in circuit f = clock frequency Nswitch = average % of clock periods in which node switches Cload = capacitance of node
Approaches to minimizing power consumption
l Reduce Supply Voltage l Reduce clock frequency u Only useful when performance can be satisfied with slower clock u Can induce `sleep’ mode by turning off clock, or `idle’ mode by slowing clock down a lot l Reduce Nswitch through clever design
© 2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Reducing Power Consumption Reduce the power consumption in this circuit: Specification lCalculates memory address by adding busA and busB lOnly 15% of bus transactions contain memory address always@(posedge clock) address
