7/26/01
CMOS Analog IC Design
10 - CMOS DIGITAL-ANALOG AND ANALOG-DIGITAL CONVERTERS Section 10.0 - Introduction Section 10.1 - Characterization of Digital-Analog Converters Section 10.2 - Parallel Digital-Analog Converters Section 10.3 - Extending the Resolution of Parallel Digital-Analog Converters Section 10.4 - Serial Digital-Analog Converters Section 10.5 - Characterization of Analog-Digital Converters Section 10.6 - Serial Analog-Digital Converters Section 10.7 - Medium Speed Analog-Digital Converters Section 10.8 - High Speed Analog-Digital Converters Section 10.9 - Oversampling Converters Section 10.10 - Summary
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.0-1
CMOS Analog IC Design - Chapter 10
10.0 - INTRODUCTION ORGANIZATION
;;; ;;;; ;;; ;;;; ;;;;;;; ;;;; ;;; ;;;; ;;;; ;;;; ;;; ;;;;;;; ;;;;;;; ;;;; ;;;;;;; ;;;; Chapter 9 Switched Capacitor Circuits Systems
Chapter 10 D/A and A/D Converters
New Topics in CMOS Analog IC Design
Chapter 6 Simple CMOS & BiCMOS OTA's Complex
Chapter 7 High Performance OTA's
Chapter 8 CMOS/BiCMOS Comparators
Simple
Chapter 4 CMOS/BiCMOS Subcircuits
Chapter 5 CMOS/BiCMOS Amplifiers
Circuits
Chapter10 1 Chapter Introduction D/ to Analog CMOS Design Devices
Chapter 10 - DA and AD Converters (6/4/01)
Chapter Chapter11 2 Analog CMOS Technology Systems
Chapter 3 CMOS Modeling
© P.E. Allen, 2001
Page 10.0-2
CMOS Analog IC Design - Chapter 10
IMPORTANCE OF DATA CONVERTERS IN SIGNAL PROCESSING
ANALOG SIGNAL (Speech, sensors, radar, etc.)
DIGITAL PROCESSOR (Microprocessor)
PRE-PROCESSING (Filtering and analog to digital conversion)
POST-PROCESSING (Digital to analog conversion and filtering)
ANALOG OUTPUT SIGNAL
CONTROL ANALOG
A/D
DIGITAL
D/A
ANALOG
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.0-3
CMOS Analog IC Design - Chapter 10
DIGITAL-ANALOG CONVERTERS IN SIGNAL PROCESSING APPLICATIONS Digital Signal Processing System Microprocessors Compact disks Read only memory Random access memory Digital transmission Disk outputs Digital sensors
DIGITALANALOG CONVERTER
Reference
Chapter 10 - DA and AD Converters (6/4/01)
Filter
Amplifier
Analog Output
Fig. 10.1-01
© P.E. Allen, 2001
Page 10.0-4
CMOS Analog IC Design - Chapter 10
ASYNCHRONOUS VERSUS SYNCHRONOUS DIGITAL-ANALOG CONVERTERS VREF
VREF b1 b2 b3 bN
DigitalAnalog Converter
vOUT
b1 b2 b3
Latch
DigitalAnalog Converter
Sample and Hold
VOUT*
bN Clock
Asynchronous
Synchronous
Fig. 10.1-02
(Asterisk represents a sample and held signal.)
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.0-5
CMOS Analog IC Design - Chapter 10
BLOCK DIAGRAM OF A DIGITAL-ANALOG CONVERTER
Voltage Reference
VREF
DVREF
Scaling Network
Output Amplifier
vOUT = KDVREF
Binary Switches b1 b2 b3
bN
Figure 10.1-3
b1 is the most significant bit (MSB) The MSB is the bit that has the most (largest) influence on the analog output bN is the least significant bit (LSB) The LSB is the bit that has the least (smallest) influence on the analog output
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.1-1
CMOS Analog IC Design
10.1 - CHARACTERIZATION OF DIGITAL-ANALOG CONVERTERS STATIC CHARACTERISTICS OUTPUT-INPUT CHARACTERISTICS Ideal input-output characteristics of a 3-bit DAC 1.000
Analog Output Value Normalized to VREF
0.875
Infinite Resolution Characteristic
0.750 0.625
1 LSB
0.500 Vertical Shifted Characteristic
0.375 0.250 0.125 0.000 000
001
010
011 100 101 Digital Input Code
110
111 Fig. 10.1-4
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.1-2
CMOS Analog IC Design
DEFINITIONS • Resolution of the DAC is equal to the number of bits in the applied digital input word. • The full scale (FS): FS = Analog output when all bits are 1 - Analog output all bits are 0 VREF 1 FS = (VREF - 2 N ) - 0 = VREF1 - 2 N • Full scale range (FSR) is defined as lim
FSR = N→∞FS = VREF • Quantization Noise is the inherent uncertainty in digitizing an analog value with a finite resolution converter. Quantization Noise 1LSB 0.5LSB 0LSB
000
001
-0.5LSB
Chapter 10 - DA and AD Converters (6/4/01)
010
011
100
101
110
111
Digital Input Code
Fig. 10.1-5
© P.E. Allen, 2001
Page 10.1-3
CMOS Analog IC Design
MORE DEFINITIONS • Dynamic Range (DR) of a DAC is the ratio of the FSR to the smallest difference that can be resolved (i.e. an LSB) FSR FSR DR = LSB change = (FSR/2N) = 2N or in terms of decibels DR(dB) = 6.02N (dB) • Signal-to-noise ratio (SNR) for the DAC is the ratio of the full scale value to the rms value of the quantization noise. T
LSB FSR 1⌠ t 2 2 T ⌡LSB T - 0.5 dt = 12 = 2N 12 0
rms(quantization noise) = ∴
SNR =
vOUT(rms)
(FSR/ 12 2N) • Maximum SNR (SNRmax) is defined as (rms)
vOUT SNRmax =
max
(FSR/ 12 2N) or in terms of decibels
=
FSR/(2 2) 6 2N = 2 FSR/( 12 2N)
6˚2N = 10 log10(6) + 20 log10 (2N) - 20 log10(2) 2
SNRmax(dB) = 20 log10
= 7.78 dB - 6.02 dB + 6.02N dB = 1.76 dB + 6.02N dB
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design
© P.E. Allen, 2001 Page 10.1-4
EVEN MORE DEFINITIONS ¥ Effective number of bits (ENOB) can be defined from the above as ENOB =
SNRActual - 1.76 6.02
where SNRActual is the actual SNR of the converter. Comment: The DR is the amplitude range necessary to resolve N bits regardless of the amplitude of the output voltage. However, when referenced to a given output analog signal amplitude, the DR required must include 1.76 dB more to acount for the presence of quantization noise. Thus, for a 10-bit DAC, the DR is 60.2dB and for a full-scale, rms output voltage, the signal must be approximately 62dB above whatever noise floor is present in the output of the DAC.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.1-5
CMOS Analog IC Design
1 7/8
Actual Characteristic
Gain Error 6/8 Actual Characteristic 5/8
5/8 Offset Error
Infinite Resolution Characteristic
3/8 2/8
Ideal 3-bit Resolution Characteristic
1/8 0
1
7/8
6/8
4/8
Analog Output Value Normalized to VREF
Analog Output Value Normalized to VREF
OFFSET AND GAIN ERRORS An offset error is a constant difference between the actual finite resolution characteristic and the infinite resolution characteristic measured at any vertical jump. A gain error is the difference between the slope of an actual finite resolution and an infinite resolution characteristic measured at the right-most vertical jump.
000 001 010 011 100 101 110 111 Digital Input Code
4/8
Infinite Resolution Characteristic
3/8 2/8
Ideal 3-bit Resolution Characteristic
1/8 0
000 001 010 011 100 101 110 111 Digital Input Code
Offset Error in a 3-bit DAC
Gain Error in a 3-bit DAC Fig. 10.1-6
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.1-6
CMOS Analog IC Design
INTEGRAL AND DIFFERENTIAL NONLINEARITY • Integral Nonlinearity (INL) is the maximum difference between the actual finite resolution characteristic and the ideal finite resolution characteristic measured vertically (% or LSB). • Differential Nonlinearity (DNL) is a measure of the separation between adjacent levels measured at each vertical jump (% or LSB). V cx V cx - V s Vs x 100% = V s - 1 LSBs
DNL =
where Vcx is the actual voltage change on a bit-to-bit basis and Vs is the ideal change (VFSR/2N)
Analog Output Voltage
Example of a 3-bit DAC: 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 8 000
Infinite Resolution Characteristic +1.5 LSB DNL Nonmonotonicity
+1.5 LSB INL
-1 LSB INL A -1.5 LSB DNL Ideal 3-bit Characteristic Actual 3-bit Characteristic
001
Chapter 10 - DA and AD Converters (6/4/01)
010
011 100 101 Digital Input Code
110
111 Fig. 10.1-7
© P.E. Allen, 2001
Page 10.1-7
CMOS Analog IC Design
EXAMPLE OF INL AND DNL OF A NONIDEAL 4-BIT DAC Find the ±INL and ±DNL for the 4-bit DAC shown. 15/16 14/16
Analog Output (Normalized to Full Scale)
13.16 12/16 -2 LSB DNL
11/16
-1.5 LSB INL
Ideal 4-bit DAC Characteristic
10/16 9/16
+1.5 LSB DNL
8/16
-2 LSB DNL
7/16 6/16
+1.5 LSB INL
Actual 4-bit DAC Characteristic
5/16 4/16 3/16 2/16 1/16 0/16 b1 b2 b3 b4
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design
0 1 0 0
0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 Digital Input Code
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Fig. 10.1-8
© P.E. Allen, 2001 Page 10.1-8
DYNAMIC CHARACTERISTICS OF DIGITAL-ANALOG CONVERTERS Dynamic characteristics include the influence of time. DEFINITIONS • Conversion speed is the time it takes for the DAC to provide an analog output when the digital input word is changed. Factor that influence the conversion speed: Parasitic capacitors (would like all nodes to be low impedance) Op amp gainbandwidth Op amp slew rate • Gain error of an op amp is the difference between the desired and actual output voltage of the op amp (can have both a static and dynamic influence) Loop Gain Actual Gain = Ideal Gain x 1 + Loop Gain Ideal Gain - Actual Gain 1 Gain error = Ideal Output - Actual Output = = 1 + Loop Gain Ideal Gain
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.1-9
CMOS Analog IC Design
EXAMPLE OF INFLUENCE OF OP AMP GAIN ERROR ON DAC PERFORMANCE Assume that a DAC using an op amp in the inverting configuration with C1 = C2 and A vd(0) = 1000. Find the largest resolution of the DAC if VREF is 1V and assuming worst case conditions. Solution C2 A (0) = 0.5⋅1000 = 500. The gain error C1+C2 vd is therefore 1/501 ¯ 0.002. The gain error should be less than the quantization noise of ±0.5LSB which is expressed as The loop gain of the inverting configuration is LG =
V REF 1 ≈ 0.002 ≤ N+1 501 2 Therefore the largest value of N that satisfies this equation is N = 7. Gain error =
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.1-10
CMOS Analog IC Design
INFLUENCE OF THE OP AMP GAINBANDWIDTH Single-pole response: vout(t) = ACL[1 - e-ωAt]vin(t) where ACL = closed-loop gain GB ω A = A (0) vd To avoid errors in DACs (and ADCs), vout(t) must be within ±0.5LSB of the final value by the end of the conversion time. Multiple-pole response: Typically the response is underdamped like the following (see Appendix C of text). vOUT(t) Upper Tolerance
Final Value + ε vIN
+
vOUT
ε
Final Value
ε
Final Value - ε
Lower Tolerance
Settling Time 0
Chapter 10 - DA and AD Converters (6/4/01)
0
Ts
t Fig. 6.1-7
© P.E. Allen, 2001
Page 10.1-11
CMOS Analog IC Design
EXAMPLE OF THE INFLUENCE OF GB AND SETTLING TIME ON DAC PERFORMANCE Assume that a DAC uses a switched capacitor noninverting amplifier with C1 = C2 and GB = 1MHz. Find the conversion time of an 8-bit DAC if VREF is 1V. Solution From the analysis in Secs. 9.2 and 9.3, we know that C2 ω H = C +C GB = (2π)(0.5)(106) = 3.141x106 1 2
and ACL = 1. Assume that the ideal output is equal to V REF . Therefore the value of the output voltage which is 0.5LSB of VREF is 1 1 - N+1 = 1 - e-ω H T 2 or 2N+1 = eωH T Solving for T gives N+1 N+1 9 T = ω ln(2) = 0.693 ω = 3.141 0.693 = 1.986µs H H
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.1-12
CMOS Analog IC Design
TESTING OF DACs INPUT-OUTPUT TEST Test setup: Digital Word Input (N+2 bits)
N-bit DAC under test
Vout
ADC ADC with Output Digital more resolution Subtractor than DAC (N+2 bits) (N+2 bits)
Digital Error Output (N+2 bits)
Fig. 10.1-9
Comments: Sweep the digital input word from 000...0 to 111...1. The ADC should have more resolution by at least 2 bits and be more accurate than the errors of the DAC INL will show up in the output as the presence of 1’s in any bit. If there is a 1 in the Nth bit, the INL is greater than ±0.5LSB DNL will show up as a change between each successive digital error output. The bits which are greater than N in the digital error output can be used to resolve the errors to less than ±0.5LSB
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.1-13
CMOS Analog IC Design
SPECTRAL TEST Test setup: 1 0 0 1
1 1 1 1
0 1 1
1
1 0 0 0
1 0 0 0
Digital Pattern Generator (N bits)
|Vout(jω)|
Vout
t VREF N-bit DAC under test
Noise floor due to nonlinearities ω
fsig Vout
Distortion Analyzer
Spectral Output
Fig. 10.1-10
Clock
Comments: Digital input pattern is selected to have a fundamental frequency which has a magnitude of at least 6N dB above its harmonics. Length of the digital sequence determines the spectral purity of the fundamental frequency. All nonlinearities of the DAC (i.e. INL and DNL) will cause harmonics of the fundamental frequency The THD can be used to determine the SNR dB range between the magnitude of the fundamental and the THD. This SNR should be at least 6N dB to have an INL of less than ±0.5LSB for an ENOB of N-bits. Note that the noise contribution of VREF must be less than the noise floor due to nonlinearities. If the period of the digital pattern is increased, the frequency dependence of INL can be measured.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.2-1
CMOS Analog IC Design
10.2 - PARALLEL DIGITAL-ANALOG CONVERTERS CLASSIFICATION OF DIGITAL-ANALOG CONVERTERS Digital-Analog Converters Parallel
Serial Charge
Current
Voltage
Charge
Voltage and Charge Slow
Chapter 10 - DA and AD Converters (6/4/01)
Fast
Fig. 10.2-1
© P.E. Allen, 2001
Page 10.2-2
CMOS Analog IC Design
CURRENT SCALING DIGITAL-ANALOG CONVERTERS GENERAL CURRENT SCALING DACS Digital Input Word I1 I2 Current Scaling Network
VREF
RF
I3
-
IN
+
vOUT
Fig. 10.2-2
The output voltage can be expressed as VOUT = -RF(I1 + I2 + I3 + ··· + IN) where the currents I1, I2, I3, ... are binary weighted currents.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.2-3
CMOS Analog IC Design
BINARY-WEIGHTED RESISTOR DAC Circuit: VREF RF = K(R/2)
S1
S2 I1
R
S3
SN
I2 2R
I3
IN
2N-1R
4R
RLSB
RMSB
+
+
vOUT -
IO Fig. 10.2-3
Comments: 1.) RF can be used to scale the gain of the DAC. If RF = KR/2, then bN bN -KR b1 b2 b3 b1 b 2 b 3 vOUT = - RFIO = 2 R + 2R + 4R + ··· + N-1 VREF ⇒ vOUT = -K 2 + 4 + 8 + ··· + N V REF 2 R 2 where bi is 1 if switch Si is connected toVREF or 0 if switch Si is connected to ground. RMSB = 2.) Component spread value = R LSB
R 2N-1R
=
1 2N-1
3.) Positive attributes: Insensitive to parasitics ⇒ fast 4.) Negative attributes: Large component spread value Trimming required for large values of N Nonmonotonic
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.2-4
CMOS Analog IC Design
R-2R LADDER IMPLEMENTATION OF THE BINARY WEIGHTED RESISTOR DAC Use of the R-2R concept to avoid large element spreads:
VREF
2R
R
R
2R
I1 2R
I2 2R
S1
S2
S3
2R
I3
IN
SN
RF = KR +
-
IO
vOUT
+
-
Fig. 10.2-4
How does the R-2R ladder work? “The resistance seen to the right of any of the vertical 2R resistors is 2R.” 4I
2I
R 4I
R 2I
8I
I
VREF 2R
2R
2R I 2R Fig. 10.2-4(2R-R)
Attributes: • Not sensitive to parasitics (the currents through the resistors never changes as Si is varied) • Small element spread • Resistors made from the same unit (2R consist of two in series or R consists of two in parallel) • Not monotonic
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.2-5
CMOS Analog IC Design
CURRENT SCALING USING BINARY WEIGHTED MOSFET CURRENT SINKS Circuit: VDD IREF =I
S1 N-1 b1 2 I
-
+
SN-2
bN-2
SN-1 4I
bN-1
SN 2I bN
Transistor Array
A2
I
+
R2
+
A1 vOUT
+
+ V - A
-
VA -
2N-1 matched FETs
4 matched FETs 2 matched FETs
Fig. 10.2-5
Operation: vOUT = R2(bN·I + bN-1·2I + bN-2·4I + ··· + b1·2N-1·I) VREF bN-1 b1 b 2 b 3 N-2 If IREF = N , then vOUT = 2 + 4 + 8 + ··· + N-2 + N-1 + 2 2 2 R 2
bN 2 N VREF
= (bN + 2bN-1 + 4bN-2 + ··· + 2N-1b1)IREF Attributes: Fast (no floating nodes) and not monotonic
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.2-6
CMOS Analog IC Design
VOLTAGE SCALING DIGITAL-ANALOG CONVERTERS GENERAL VOLTAGE SCALING DIGITAL ANALOG CONVERTER
Digital Input Word V1 Voltage Scaling Network
VREF
V2 Decoder Logic
V3
vOUT
V2N Fig. 10.2-6
Operation: Creates all possible values of the analog output then uses a decoding network to determine which voltage to select based on the digital input word.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.2-7
CMOS Analog IC Design
3-BIT VOLTAGE SCALING DIGITAL-ANALOG CONVERTER
R/2 8 R 7 R 11 V 16 REF 6 R 5 R 4 R 3 R 2 R 1 R/2
b 3 b3
Input = 101 b 2 b2 b 1 b1
VREF
vOUT
VREF
vOUT
7VREF 8 6VREF 8 5VREF 8 4VREF 8 3VREF 8 2VREF 8 VREF 8 0 000 001 010 011 100 101 110 111
(a.)
Digital Input Code (b.)
Figure 10.2-7 - (a.) Implementation of a 3-bit voltage scaling DAC. (b.) Input-output characteristics of Fig. 10.2-7(a.)
VREF VREF The voltage at any tap can be expressed as: vOUT = 8 (n − 0.5) = 16 (2n − 1) Attributes: Guaranteed monotonic, compatible with CMOS technology, large area if N is large, sensitive to parasitics, requires a buffer, large current can flow through the resistor string.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.2-8
CMOS Analog IC Design
ALTERNATE REALIZATION OF THE 3-BIT VOLTAGE SCALING DAC VREF R/2 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 R/2
b3
b2
b1
3-to-8 Decoder
vOUT
Fig. 10.2-8
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.2-9
CMOS Analog IC Design
INL AND DNL OF THE VOLTAGE SCALING DAC Uses a worst-case approach. For an n-bit voltage scaling DAC, assume there are 2n resistors between VREF and ground. Also assume that the resistors are numbered from 1 to 2n beginning with the resistor connected to VREF and ending with the resistor connected to ground. Integral Nonlinearity The voltage at the i-th resistor from the top is, vi =
(2n-i)R V + iR REF
(2n-i)R
where there are i resistors above vi and 2n-1 resistors below vi. For worst case, assume that i = 2n-1 (midpoint). Define Rmax = R + ∆R and Rmin = R - ∆R. The worst case INL is INL = v2n-1(actual) - v2n-1(ideal) Therefore, INL =
Differential Nonlinearity The worst case DNL can be found as DNL = vstep(actual) - vstep(ideal) Substituting the actual and ideal steps gives, (R±∆R)VREF R VREF - n = 2 nR 2R V R± ∆ R R REF ± ∆ R V REF = R - R n = R 2 2n Therefore, ±∆R DNL = R LSBs
VREF ∆ R 2n-1(R+∆R)VREF - 2 = 2R V REF 2n-1(R+∆R) + 2n-1(R-∆R)
or INL=
2n ∆ R ∆R V =2n-1 R 2n 2R REF
VREF n-1 ∆ R =2 R LSBs 2n
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.2-10
CMOS Analog IC Design
EXAMPLE 10.2-1 Accuracy Requirements of a Voltage-Scaling digital-analog Converter If the resistor string of a voltage scaling digital-analog converter is a 5 µm wide polysilicon strip having a relative accuracy of ±1%, what is the largest number of bits that can be resolved and keep the worst case INL within ±0.5 LSB? For this number of bits, what is the worst case DNL? Solution From the previous page, we can write that ∆R 1 1 = 2n-1 ≤ R 100 2
2 n-1
This inequality can be simplified 2n ≤ 100 which has a solution of n = 6. The value of the DNL for n = 6 is found from the previous page as ±1 DNL = 100 LSBs = ±0.01LSBs (This is the reason the resistor string is monotonic.)
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.2-11
CMOS Analog IC Design
CHARGE SCALING DIGITAL-ANALOG CONVERTERS GENERAL CHARGE SCALING DIGITAL-ANALOG CONVERTER Digital Input Word
VREF
Charge Scaling Network
vOUT Fig. 10.2-9
General principle is to capacitively attenuate the reference voltage. Capacitive attenuation is simply: C1 + VREF
C2
Vout Fig. 10.2-9b
Calculate as if the capacitors were resistors. For example, 1 C2 C1 V = Vout = 1 REF 1 C1 + C2 VREF C1 + C2
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.2-12
CMOS Analog IC Design
BINARY-WEIGHTED, CHARGE SCALING DAC Circuit: + C 2
C φ1
C 4
S1
S2
φ2
C 2N-2
S3 φ2
φ2
C 2N-1
C 2N-1
SN-1 φ2
SN φ2
VREF
vOUT
Terminating Capacitor Fig. 10.2-10
Operation: 1.) All switches connected to ground during φ1. 2.) Switch Si closes to VREF if bi = 1 or to ground if bi = 0. Equating the charge in the capacitors gives, b 2C b 3 C bNC VREFCeq = VREF b1C + 2 + 22 + ... + N−1 = Ctot vOUT = 2C vOUT 2 which gives vOUT = [b12-1 + b22-2 + b32-3 + ... + bN2-N]VREF Equivalent circuit of the binary-weighted, charge scaling DAC is: Ceq. +
VREF
2C - Ceq.
vOUT -
Fig. 10.2-11
Attributes: • Accurate • Sensitive to parasitics • Not monotonic • Charge feedthrough occurs at turn on of switches
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design
© P.E. Allen, 2001 Page 10.2-13
INTEGRAL NONLINEARITY OF THE CHARGE SCALING DAC Again, we use a worst case approach. Assume an n-bit charge scaling DAC with the MSB capacitor of C and the LSB capacitor of C/2n-1 and the capacitors have a tolerance of ∆C/C. The ideal output when the i-th capacitor only is connected to VREF is V REF 2n 2n C/2i-1 vOUT (ideal) = 2C V REF = i n = i LSBs 2 2 2 The maximum and minimum capacitance is Cmax = C + ∆C and Cmin = C - ∆C. Therefore, the actual worst case output for the i-th capacitor is V REF ∆C·VREF 2n 2n∆C (C±∆C)/2i-1 V = ± = i ± i LSBs vOUT(actual) = REF 2C 2C 2i 2iC 2 Now, the INL for the i-th bit is given as ±2n∆C 2n-i∆C = C LSBs 2iC Typically, the worst case value of i occurs for i = 1. Therefore, the worst case INL is INL(i) = vOUT(actual) - vOUT(ideal) =
∆C INL = ± 2n-1 C LSBs
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.2-14
CMOS Analog IC Design
DIFFERENTIAL NONLINEARITY OF THE CHARGE SCALING DAC The worst case DNL for the binary weighted capacitor array is found when the MSB changes. The output voltage of the binary weighted capacitor array can be written as Ceq. vOUT = (2C-C ) + C V REF eq. eq. where Ceq represents capacitors whose bits are 1 and (2C - Ceq) represents capacitors whose bits are 0. The worst case DNL can be expressed as DNL = vstep(worst case) -vstep(ideal) = [(vOUT(1000....) - vOUT(0111....)) - 1] LSBs The worst case choice for the capacitors is, 1 1 1 1 1 C1 =C+∆C, C2 = 2(C-∆C), C3 = 4(C-∆C),...,Cn-1 = 2n-2(C-∆C), Cn = 2n-1(C-∆C), and Cterm = 2n-1(C-∆C) n
Note that ΣCi + Cterm = C2+ C3+···+ Cn-1+ Cn+ Cterm = C-∆C i=2
C+∆C C+∆C ∴ (vOUT(1000...) = (C+∆C)+(C-∆C)V REF = 2C V REF and 1 (C-∆C) - n-1(C-∆C) (C-∆C) -Cterm 2 2 C-∆C vOUT(0111...) = (C+∆C)+(C-∆C)VREF = (C+∆C)+(C-∆C) V REF = 2C 1 - nV REF 2 2 ∆C C+∆C C-∆C ∴ [(vOUT(1000....) - vOUT(0111....)) - 1] LSBs = = 2n 2C - 2n 2C 1 - n - 1 = (2n - 1) C LSBs 2
∆C DNL = (2n - 1) C LSBs
Therefore,
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design
© P.E. Allen, 2001 Page 10.2-15
EXAMPLE 10.2-2 DNL and INL of a Binary Weighted Capacitor Array DAC If the tolerance of the capacitors in an 8-bit, binary weighted, charge scaling DAC are –0.5%, find the worst case INL and DNL. Solution For the worst case INL, we get from above that INL = (27)(±0.005) = ±0.64 LSBs For the worst case DNL, we can write that DNL = (28-1)(±0.005) = ±1.275 LSBs
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.2-16
CMOS Analog IC Design
EXAMPLE 10.2-3 Influence of Capacitor Ratio Accuracy on Number of Bits Use the data of Fig. 2.4-2 to estimate the number of bits possible for a charge scaling DAC assuming a worst case approach for INL and that the worst conditions occur at the midscale (1 MSB). Solution Assuming an INL of –0.5 LSB, we can write that INL = ±2n-1
1 ∆C ≤± 2 C
→
1 ∆C = . C 2n
From the data presented in Fig. 2.4-2, it is reasonable to assume that the relative accuracy of the capacitor ratios will decrease with the number of bits. Let us assume a unit capacitor of 50 µm by 50 µm and a relative accuracy of approximately –0.1%. Solving for N in the above equation gives approximately 10 bits. However, the –0.1% figure corresponds to ratios of 16:1 or 4 bits. In order to get a solution, we estimate the relative accuracy of capacitor ratios as ∆C ≅ 0.001 + 0.0001N C Using this approximate relationship, a 9-bit digital-analog converter should be realizable.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.2-17
CMOS Analog IC Design
BINARY WEIGHTED, CHARGE AMPLIFIER DAC + -
φ1 VREF
CF = 2NC/K
φ 1 b 1 b 1 φ 1 b2 b 2 φ 1 b3 b3 2N-1C
2N-2C
2N-3C
φ1 bN-1 bN-1 φ1 bN bN 2C
C
+
+
vOUT -
Fig. 10.2-12
Attributes: • No floating nodes which implies insensitive to parasitics and fast • No terminating capacitor required • With the above configuration, charge feedthrough will be ∆Verror ≈ -(COL/2CN)∆V • Can totally eliminate parasitics with parasitic-insensitive switched capacitor circuitry but not the charge feedthrough
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.2-18
CMOS Analog IC Design
SUMMARY OF THE PARALLEL DAC PERFORMANCE DAC Type Current Scaling Voltage Scaling
Advantage Fast, insensitive to switch parasitics Monotonic, equal resistors
Charge Scaling
Fast, good accuracy
Disadvantage Large element spread, nonmonotonic Large area, sensitive to parasitic capacitance Large element spread, nonmonotonic
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design
© P.E. Allen, 2001 Page 10.3-1
10.3 - EXTENDING THE RESOLUTION OF PARALLEL DIGITALANALOG CONVERTERS TECHNIQUE: N Divide the total resolution N into k smaller sub-DACs each with a resolution of k . Result: Smaller total area. More resolution because of reduced largest to smallest component spread. APPROACHES: • Combination of similarly scaled subDACs Divider approach (scale the analog output of the subDACs) Subranging approach (scale the reference voltage of the subDACs) • Combination of differently scaled subDACs
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.3-2
CMOS Analog IC Design
COMBINATION OF SIMILARLY SCALED SUBDACs ANALOG SCALING - DIVIDER APPROACH Example of combining a m-bit and k-bit subDAC to form a m+k-bit DAC. VREF m-MSB bits
m-bit MSB DAC
+ Σ +
vOUT
VREF k-LSB bits
k-bit LSB DAC
÷ 2m Fig. 10.3-1
bm bm+k b1 b 2 1 bm+1 b m+2 vOUT = 2 + 4 + ··· + mV REF + m 2 + 4 + ··· + k V REF 2 2 2 bm b m+1 bm+2 bm+k b1 b 2 vOUT = 2 + 4 + ··· + m + m+1 + m+2 + ··· + m+kV REF 2 2 2 2 Accuracy? VREF 2n Weighting factor of the i-th bit = i n = 2n-i LSBs 2 2 ±0.5 LSB 1 100 Accuracy of the i-th bit = n-i = n-i+1 = n-i+1 % 2 LSB 2 2
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design
© P.E. Allen, 2001 Page 10.3-3
EXAMPLE 10.3-1 Illustration of the Influence of the Scaling Factor Assume that m = 2 and k = 2 in Fig. 10.3-1 and find the transfer characteristic of this DAC if the scaling factor for the LSB DAC is 3/8 instead of 1/4. Assume that V REF = 1V. What is the –INL and –DNL for this DAC? Is this DAC monotonic or not? Solution The ideal DAC output is given as vOUT =
b1 b2 1b3 b4 b1 b2 b3 b4 + + ˚+˚ = + + + . 2 4 4 2 4 2 4 8 16
The actual DAC output can be written as vOUT(act.) =
b1 b2 3b3 3b4 16b1 8b2 6b3 3b4 + + + = + + + 2 4 16 32 32 32 32 32
The results are tabulated in Table 10.3-1 for this example.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.3-4
CMOS Analog IC Design
EXAMPLE 10.3-1 - CONTINUED Table 10.3-1 Ideal and Actual Analog Output for the DAC in Ex. 10.3-1, Input Digital vOUT(act.) Word 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0/32 3/32 6/32 9/32 8/32 11/32 14/32 17/32 16/32 19/32 22/32 25/32 24/32 27/32 30/32 33/32
vOUT 0/32 2/32 4/32 6/32 8/32 10/32 12/32 14/32 16/32 18/32 20/32 22/32 24/32 26/32 28/32 30/32
vOUT(act.) - vOUT
Change in vOUT(act) - 2/32
0/32 1/32 2/32 3/32 0/32 1/32 2/32 3/32 0/32 1/32 2/32 3/32 0/32 1/32 2/32 3/32
1/32 1/32 1/32 -3/32 1/32 1/32 1/32 -3/32 1/32 1/32 1/32 -3/32 1/32 1/32 1/32
Table 10.3-1contains all the information we are seeking. An LSB for this example is 1/16 or 2/32. The fourth column gives the +INL as 1.5LSB and the -INL as 0LSB. The fifth column gives the +DNL as 0.5LSB and the -DNL as -1.5LSB. Because the -DNL is greater than -1LSB, this DAC is not monotonic.
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design
© P.E. Allen, 2001 Page 10.3-5
EXAMPLE 10.3-2 Finding the Tolerance of the Scaling Factor to Prevent Conversion Errors Find the worst case tolerance of the scaling factor (x = 1/2m = 1/4) in the above example that will not cause a conversion error in the DAC. Solution Because the scaling factor only affects the LSB DAC, we need only consider the two LSB bits. The worst case requirement for the ideal scaling factor of 1/4 is given as b4 xb3 xb4 1 b3 2 ( x ±˚∆x) + 4 ( x ± ∆x) ≤ 2 + 4 ± 32 or b4 1 b3 b4 b3 ∆x + ∆ x = ∆ x ˚+˚ ≤ . 32 2 4 2 4 The worst case value of ∆x occurs when both b3 and b4 are 1. Therefore, we get 1 1 3 ∆x4 ≤ 32 → ∆ x ≤ 24 . The scaling factor, x, can be expressed as 1 1 6 1 x ± ∆x = 4 ± 24 = 24 ± 24 Therefore, the tolerance required for the scaling factor x is 5/24 to 7/24. This corresponds to an accuracy of ±16.7% which is less than the ±25% (±100%/2k) because of the influence of the LSB bits. It can be shown that the INL will be equal to ±0.5LSB or less (see Problem 10.3-6 of text).
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.3-6
CMOS Analog IC Design
REFERENCE SCALING - SUBRANGING APPROACH Example of combining a m-bit and k-bit subDAC to form a m+k-bit DAC. VREF m-bit MSB DAC
m-MSB bits
+ Σ +
vOUT
VREF/2m k-bit LSB DAC
k-LSB bits
Fig. 10.3-2
bm bm+kV REF b1 b 2 bm+1 bm+2 vOUT = 2 + 4 + ··· + 2mV REF + 2 + 4 + ··· + 2k 2m bm bm+1 bm+2 bm+k b1 b 2 vOUT = 2 + 4 + ··· + 2m + 2m+1 + 2m+2 + ··· + 2m+kV REF Accuracy considerations of this method are similar to the analog scaling approach.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.3-7
CMOS Analog IC Design
CURRENT SCALING DAC USING TWO SUBDACs Implementation: i1 b8
b7
b6
b5
15R
i2
io
R
b4
b3
I 16
MSB I 8
I 4
Current I Divider 2
LSB subDAC
I 16
I 8
I 4
MSB subDAC
vOUT
-
b1
b2
LSB
RF
+
I 2 Fig. 10.3-3
b 1 b 2 b 3 b4 1 b 5 b 6 b 7 b8 vOUT = RFI 2 + 4 + 8 + 16 + 16 2 + 4 + 8 + 16
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.3-8
CMOS Analog IC Design
CHARGE SCALING DAC USING TWO SUBDACs Implementation: Terminating Capacitor
MSB Array
Cs
+ C 2
C 4
C 8 b8 φ2
b7
C
b6 φ2
Scaling Capacitor
φ1
C 8
LSB Array
φ2
b5
C 8
C 4
b4
b3
φ2
φ2
C 2
φ2
-
C
b2
vOUT
b1 φ2
φ2
VREF
Fig. 10.3-4
Design of the scaling capacitor, Cs: The series combination of Cs and the LSB array must terminate the MSB array or equal C/8. Therefore, we can write 1 1 8 1 16 1 15 C or C = C - 2C = 2C - 2C = 2C . 1 8= 1 s Cs + 2C
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.3-9
CMOS Analog IC Design
EQUIVALENT CIRCUIT OF THE CHARGE SCALING DAC USING TWO SUBDACs Simplified equivalent circuit: Cs = 2C/15 2C V2
C + 7C/8 = 15C/8
+ vOUT
-
V1 Fig. 10.3-5
where the Thevenin equivalent voltage of the MSB array is 16 b1 b2 b3 b4 1 1/2 1/4 1/8 V 1 = 15/8 b1V REF + 15/8 b2V REF + 15/8 b 3V REF + 15/8 b4VREF = 15 2 + 4 + 8 + 16 V REF and the Thevenin equivalent voltage of the LSB array is b 5 b 6 b 7 b8 1/1 1/2 1/4 1/8 V 2 = 2 b5V REF + 2 b6V REF + 2 b7V REF + 2 b 8V REF = 2 + 4 + 8 + 16 V REF
Combining the elements of the simplified equivalent circuit above gives 15 1 8 2C + 2C 15C 15 1 16 15+15·15 V + vOUT = 1 + 15 + 8 1 1 + 15 + 8 V 2 = 15+15·15+16V 1+ 15+15·15+16V2 = 16 V 1 + 16 V 2 2C 2C 15C 2C 2C 15C 8
b7 b8 b 1 b 2 b 3 b4 b5 b6 vOUT = 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256VREF =
∑
biVREF 2i
i=0
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.3-10
CMOS Analog IC Design
CHARGE AMPLIFIER DAC USING TWO BINARY WEIGHTED CHARGE AMPLIFIER SUBDACs Implementation: C/8 b5 b5 b6 b6 + VREF -
b7
C φ1 C/2
C/4
b7 b8 b8
C/8
b1
φ1 vO1
b1 b2
2C -
φ1
+ φ1
b2 A1
VREF
b3
-
C C/2
b4
φ1
b4
C/4
C/8
vOUT
-
φ1
+
-
A2
φ1 φ1 Fig. 10.3-6
MSB Array
LSB Array
+
2C
b3
+
φ1
φ1
Attributes: • • • •
MSB subDAC is not dependent upon the accuracy of the scaling factor for the LSB subDAC. Insensitive to parasitics, fast Limited to op amp dynamics No ICMR problems with the op amp
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.3-11
CMOS Analog IC Design
COMBINATION OF DIFFERENTLY SCALED SUBDACs VOLTAGE SCALING MSB SUBDAC AND CHARGE SCALING LSB SUBDAC Implementation: m-MSB bits m-bit, MSB voltage scaling subDAC
vOUT
m-to-2m Decoder A R1 VREF
R 2 R3
R2m-2 R2m-1
SF Ck = 2k-1C Bus A Sk,A R2m Sk,B
m-to-2m Decoder
B
Ck-1 = 2k-2C
m-MSB bits
C1 =C
Sk-1,A
S2A
S1A
Sk-1,B
S2B
S1B
Bus B
SF
C2 =2C
C
k-bit, LSB charge scaling subDAC Fig. 10.3-7
Operation: 1.) Switches SF and S1B through Sk,B discharge all capacitors. 2.) Decoders A and B connect Bus A and Bus B to the top and bottom, respectively, of the appropriate resistor as determined by the m-bits. 3.) The charge scaling subDAC divides the voltage across this resistor by capacitive division determined by the k-bits. Attributes: • MSB’s are monotonic but the accuracy is poor • Accuracy of LSBs is good
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.3-12
CMOS Analog IC Design
VOLTAGE SCALING MSB SUBDAC AND CHARGE SCALING LSB SUBDAC - CONTD. Equivalent circuit of the voltage scaling (MSB) and charge scaling (LSB) DAC: Ck = Bus A 2k-1C
Ck-1 = 2k-2C
C2 =2C
C1 =C
Bus A Ceq.
C vOUT
2-mVREF
Sk,A
Sk-1,A
S2A
S1A
Sk,B
Sk,B
S2B
S1B
2-mVREF
2kC - Ceq. Bus B
v'OUT vOUT
V'REF
Bus B V'REF
Fig. 10.3-8
where,
bm-1 b m b1 b 2 + + ··· + m-1 + m 21 22 2 2
V’REF = V REF and v’OUT =
VREF bm+1 bm+2 bm+k-1 bm+k bm+k-1 bm+k bm+1 b m+2 = V REF m+1 + m+2 + ··· + m+k-1 + m+k + + ··· + + m 2 k-1 k 2 2 2 2 2 2 2 2 2
Adding V’REF of Eq. (13) to v’OUT of Eq. (12) gives the DAC output voltage as bm-1 bm bm+1 bm+2 bm+k-1 bm+k b1 b 2 vOUT = V’REF + v’OUT = VREF 21 + 22 + ··· + 2m-1 + 2m + 2m+1 + 2m+2 + ··· + 2m+k-1 + 2m+k which is equivalent to an m+k bit DAC.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.3-13
CMOS Analog IC Design
CHARGE SCALING MSB SUBDAC AND VOLTAGE SCALING LSB SUBDAC C1 = 2mC
C2 = 2m-1C
Cm-1 =21C
Cm =C
R1
Cm =C
R2
vOUT VREF
S1,A S1,B
S2,A S2,B
Sm-2A
Sm-1A
Sm-2B
Sm-1B
m-bit, MSB charge scaling subDAC
vk
kto2k Decoder
R3
VREF
R2k-2 R2k-1
Fig. 10.3-9A
k-LSB bits
k-bit, R2k LSB voltage scaling subDAC
bm-1 b m vk b1 b 2 + 2 + ··· + m-1 + m V REF + m 1 2 2 2 2 2
vOUT = where
bm+k-1 b m+k bm+1 b m+2 + 2 + ··· + k-1 + k V REF 21 2 2 2
vk = Therefore,
bm-1 b m bm+1 bm+2 bm+k-1 b m+k b1 b 2 + 2 + ··· + m-1 + m + m+1 + m+2 + ··· + m+k-1 + m+k V REF 1 2 2 2 2 2 2 2 2
vOUT =
Attributes: • MSBs have good accuracy • LSBs are monotonic, have poor accuracy - require trimming for good accuracy
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.3-14
CMOS Analog IC Design
TRADEOFFS IN SUBDAC SELECTION TO ENHANCE LINEARITY PERFORMANCE The use of two different types of scaling subDACs to implement a DAC permits tradeoffs in regard to the INL and DNL performance of the DAC. Assume a m-bit MSB subDAC and a k-bit LSB subDAC. MSB Voltage Scaling SubDAC and LSB Charge Scaling SubDAC (n = m+k) INL and DNL of the m-bit MSB voltage-scaling subDAC: ± ∆ R 2n ±∆R 2n ∆ R ∆R and DNL(R) = R m = 2k R LSBs INL(R) = 2m-1 m R = 2n-1 R LSBs 2 2 INL and DNL of the k-bit LSB charge-scaling subDAC: ∆C ∆C INL(C) = 2k-1 C LSBs and DNL(C) = (2k-1) C LSBs Combining these relationships:
∆R ∆C INL = INL(R) + INL(C) = 2 n-1 R + 2k-1 C LSBs and
∆C ∆R DNL = DNL(R) + DNL(C) = 2 k R + (2k-1) C LSBs MSB Charge Scaling SubDAC and LSB Voltage Scaling SubDAC
∆R ∆C INL = INL(R) + INL(C) = 2k-1 R + 2n-1 C LSBs and
∆C ∆R DNL = DNL(R) + DNL(C) = R + (2n-1) C LSBs
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.3-15
CMOS Analog IC Design
EXAMPLE 10.3-3 Design of a DAC using Voltage Scaling for MBSs and Charge Scaling for LSBs Consider a 12-bit DAC that uses voltage scaling for the MSBs charge scaling for the LSBs. To minimize the capacitor element spread and the number of resistors, choose m = 5 and k = 7. Find the tolerances necessary for the resistors and capacitors to give an INL and DNL equal to or less than 2 LSB and 1 LSB, respectively. Solution Substituting n = 12 and k = 7 into the previous equations gives 2 = 211
∆R ∆C + 26 R C
and
1 = 27
∆R ∆C + (27-1) R C
Solving these two equations simultaneously gives 25-2 ∆C ∆C C = 211 - 26 - 25 = 0.0154 → C = 1.54% and
∆ R 2 - 26(0.0154) ∆R = 0.0005 → R = 0.05% R = 211 We see that the capacitor tolerance will be easy to meet but that the resistor tolerance will require resistor trimming to meet the 0.05% requirement. Because of the 2n-1 multiplying ∆R/R in the relationship, it will not do any good to try different values of m and k. This realization will consist of 32 equal value resistors and 7 binary-weighted capacitors with an element spread of 64.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.3-16
CMOS Analog IC Design
EXAMPLE 10.3-4 Design of a DAC using Charge Scaling for MBSs and Voltage Scaling for LSBs Consider a 12-bit DAC that uses charge scaling for the MSBs voltage scaling for the LSBs. To minimize the capacitor element spread and the number of resistors, choose m = 7 and k = 5. Find the tolerances necessary for the resistors and capacitors to give an INL and DNL equal to or less than 2 LSB and 1 LSB, respectively. Solution Substituting the values of this example into the relationships developed on a previous slide, we get 2 = 24
∆R ∆C + 211 R C
and
1=
∆R ∆C + (212-1) R C
Solving these two equations simultaneously gives 24-2 ∆C ∆C = 16 C 2 - 211 = 0.000221 → C = 0.0221% and ∆R 3 ∆R ¯ 5 = 0.0968 → = 9.68% R R 2 -1 For this example, the resistor tolerance is easy to meet but the capacitor tolerance will be difficult. To achieve accurate capacitor tolerances, we should increase the value of m and decrease the value of k to achieve a smaller capacitor value spread and thereby enhance the tolerance of the capacitors. If we choose m = 5 and k = 7, the capacitor tolerance remains about the same but the resistor tolerance becomes 2.36% which is still reasonable. The largest to smallest capacitor ratio is 16 rather than 64 which will help to meet the capacitor tolerance requirements.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.3-17
CMOS Analog IC Design
SUMMARY OF EXTENDED RESOLUTION DACS • DAC resolution can be achieved by combining several subDACs with smaller resolution • Methods of combining include scaling the output or the reference of the non-MSB subDACs • SubDACs can use similar or different scaling methods • Tradeoffs in the number of bits per subDAC and the type of subDAC allow minimization of the INL and DNL
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.4-1
CMOS Analog IC Design
10.4 - SERIAL DIGITAL-ANALOG CONVERTERS SERIAL DACS • Typically require one clock pulse to convert one bit • Types considered here are: Charge-redistribution Algorithmic CHARGE REDISTRIBUTION DAC Implementation: S1
S2 VREF
S3
C1
C2
S4
vC2
Fig. 10.4-1
Operation: Switch S1 is the redistribution switch which places C1 in parallel with C2 sharing their charge Switch S2 precharges C1 to VREF if the ith bit, bi, is a 1 Switch S3 discharges C1 to zero if the ith bit, bi, is a 0 Switch S4 is used at the beginning of the conversion process to initially discharge C2 Conversion always begins with the LSB bit and goes to the MSB bit.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.4-2
CMOS Analog IC Design
EXAMPLE 10.4-1 Operation of the Serial, Charge Redistribution Digital-Analog Converter Assume that C1 = C2 and that the digital word to be converted is given as b1 = 1, b2 = 1, b 3 = 0, and b4 = 1. Follow through the sequence of events that result in the conversion of this digital input word. Solution 1.) S4 closes setting vC2 = 0. 2.) b4 = 1, closes switch S2 causing vC1 = VREF. 3.) Switch S1 is closed causing vC1 = vC2 = 0.5VREF. 4.) b3 = 0, closes switch S3, causing vC1 = 0V. 5.) S1 closes, the voltage across both C1 and C2 is 0.25VREF. 6.) b2 = 1, closes switch S2 causing vC1 = VREF. 7.) S1 closes, the voltage across both C1 and C2 is (1+0.25)/2VREF = 0.625VREF. 8.) b1 = 1, closes switch S2 causing vC1 = VREF. 9.) S1 closes, the voltage across both C1 and C2 is (0.625 + 1)/2VREF = 0.8125VREF = (13/16)VREF. 1 13/16
3/4 1/2 1/4 0
0
1 2 3 4 5 6 7 8 t/T
Chapter 10 - DA and AD Converters (6/4/01)
vC2/VREF
vC1/VREF
1
13/16
3/4 1/2 1/4 0
0
1 2 3 4 5 6 7 8 Fig. 10.4-2 t/T
© P.E. Allen, 2001
Page 10.4-3
CMOS Analog IC Design
PIPELINE DAC Implementation: 0
1/2 bN+1 = ±1
Σ
z-1
1/2
Σ
1/2
z-1
b1 = ±1
bN = ±1 VREF
Vout(z) = [b1
z-1
+
2-1b
-2 2z
+ ··· +
Σ
vOUT
z-1
Fig. 10.4-3
2-(N-1)b
-N -(N+1)]V Nz bN+1z REF
where bi is either ±1 if the ith bit is high or low. Attributes: • Takes N+1 clock cycles to convert the digital input to an analog output • However, a new analog output is converted every clock after the initial N+1 clocks
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.4-4
CMOS Analog IC Design
ALGORITHMIC (ITERATIVE) DAC Implementation: +VREF -VREF
A
+1
B
Σ
+1
Sample and hold 1 2
vOUT
FIG. 10.4-4
Closed form of the previous series expression is, Vout(z) =
biz-1VREF 1 - 0.5z-1
Operation: Switch A is closed when the ith bit is 1 and switch B is closed when the ith bit is 0. Start with the LSB and work to the MSB.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.4-5
CMOS Analog IC Design
EXAMPLE 10.4-2 Digital-Analog Conversion Using the Algorithmic Method Assume that the digital word to be converted is 11001 in the order of MSB to LSB. Find the converted output voltage and sketch a plot of vOUT/VREF as a function of t/T, where T is the period for one conversion. vOUT/VREF
Solution
2.0
1.) The conversion starts by zeroing the output (not shown on Fig. 10.4-4). 19/16 2.) The LSB = 1, switch A is closed and VREF 1.0 is summed with zero to give an output of 3/8 +VREF. 0 3.) The next LSB = 0, switch B is closed and vOUT = -VREF + 0.5VREF = -0.5VREF. 4.) The next LSB = 0, switch B is closed and vOUT = -VREF + 0.5(-0.5VREF) = -1.25VREF. 5.) The next LSB = 1, switch A is closed and vOUT = VREF + 0.5(-1.25VREF) = 0.375VREF.
0 -1/2
1
2
3
4
5
t/T
-1.0 -5/4 Fig. 10.4-5
-2.0
6.) The MSB = 1, switch A is closed and vOUT = VREF + 0.5(0.375VREF) = 1.1875VREF = (19/16)VREF. (Note that because the actual VREF of this example if –VREF or 2VREF, the analog value of the digital word 11001 is 19/32 times 2VREF or (19/16)VREF.)
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.4-6
CMOS Analog IC Design
SUMMARY OF SERIAL DACS Table 10.4-1 - Summary of the Performance of Serial DACs Serial DAC Figure Serial, Charge 10.4-1 Redistribution Serial, 10.4-3 algorithmic
Advantage Disadvantage Simple, minimum area Slow, requires complex external circuitry, precise capacitor ratios Simple, minimum area Slow, requires complex external circuitry, precise capacitor ratios
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.4-7
CMOS Analog IC Design
SUMMARY OF THE PERFORMANCE OF DIGITAL-ANALOG CONVERTERS DAC Current-scaling, binary weighted resistors Current-scaling, R-2R ladder Current-scaling, active devices Voltage-scaling Charge-scaling, binary weighted capacitors Binary weighted, charge amplifier Current-scaling subDACs using current division Charge-scaling subDACs using charge division Binary weighted charge amplifier subDACs Voltage-scaling (MSBs), charge-scaling (LSBs) Charge-scaling (MSBs), voltage-scaling (LSBs) Serial, charge redistribution Pipeline, algorithmic Serial, iterative algorithmic
Figure
Primary Advantage Fast, insensitive to parasitic capacitance
Primary Disadvantage Large element spread, nonmonotonic
10.2-4
Small element spread, increased accuracy
10.2-5
Fast, insensitive to switch parasitics
Nonmonotonic, limited to resistor accuracy Large element spread, large area
10.2-7
Monotonic, equal resistors
10.2-10
Best accuracy
10.2-12
Best accuracy, fast
10.3-3
Minimizes area, reduces element spread which enhances accuracy Minimizes area, reduces element spread which enhances accuracy Fast, minimizes area, reduces element spread which enhances accuracy Monotonic in MSBs, minimum area, reduced element spread Monotonic in LSBs, minimum area, reduced element spread Simple, minimum area Repeated blocks, output at each clock after N clocks Simple, one precise set of components
10.2-3
10.3-4 10.3-6 10.3-7 10.3-8 10.4-1 10.4-3 10.4-4
Large area, sensitive to parasitic capacitance Large area, sensitive to parasitic capacitance Large element spread, large area Sensitive to parasitic capacitance, divider must have –0.5LSB accuracy Sensitive to parasitic capacitance, slower, divider must have –0.5LSB accuracy Requires more op amps, divider must have –0.5LSB accuracy Must trim or calibrate resistors for absolute accuracy Must trim or calibrate resistors for absolute accuracy Slow, requires complex external circuits Large area for large number of bits Slow, requires additional logic circuitry
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design
© P.E. Allen, 2001 Page 10.5-1
10.5 - CHARACTERIZATION OF ANALOG-DIGITAL CONVERTERS ALL YOU EVER WANTED TO KNOW ABOUT A/D CONVERTERS†
†
From The Institute, September 1989, page 5
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.5-2
CMOS Analog IC Design
GENERAL BLOCK DIAGRAM OF AN ANALOG-DIGITAL CONVERTER
x(t) Prefilter
• • • •
Sample/Hold
Quantizer
Digital Processor
y(kTN)
Encoder
Fig.10.5-1
Prefilter - Avoids the aliasing of high frequency signals back into the baseband of the ADC Sample-and-hold - Maintains the input analog signal constant during conversion Quantizer - Finds the subrange that corresponds to the sampled analog input Encoder - Encoding of the digital bits corresponding to the subrange
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-3
CMOS Analog IC Design
NYQUIST FREQUENCY ANALOG-DIGITAL CONVERTERS The sampled nature of the ADC places a practical limit on the bandwidth of the input signal. If the sampling frequency is fS, and fB is the bandwidth of the input signal, then fB < 0.5fS which is simply the Nyquist relationship which states that to avoid aliasing, the sampling frequency must be greater than twice the highest signal frequency. Continuous time frequency response of the analog input signal.
f
fS -fB 0 fB Sampled data equivalent frequency response where fB < 0.5fS.
fB fS fS-fB fS 2 Case where fB > 0.5fS causing aliasing. -fB
0
fS fS 2 Use of an antialiasing filter to avoid aliasing. -fB
0
fS+fB 2fS-fB
2fS
2fS
2fS+fB
f
f
Antialiasing Filter -fB
0
fB fS 2
Chapter 10 - DA and AD Converters (6/4/01)
fS
f Fig. 10.5-2
© P.E. Allen, 2001
Page 10.5-4
CMOS Analog IC Design
CLASSIFICATION OF ANALOG-DIGITAL CONVERTERS Analog-digital converters can be classified by the relationship of fB and 0.5fS and by their conversion rate. • Nyquist ADCs - ADCs that have fB as close to 0.5fS as possible. • Oversampling ADCs - ADCs that have fB much less than 0.5fS. Table 10.5-1 - Classification of Analog-to-Digital Converter Architectures Conversion Rate
Nyquist ADCs
Oversampled ADCs
Slow
Integrating (Serial)
Very high resolution >14 bits
Medium
Successive Approximation 1-bit Pipeline Algorithmic
Fast
Flash Multiple-bit Pipeline Folding and interpolating
Moderate resolution >10 bits
Low resolution > 6 bits
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-5
CMOS Analog IC Design
STATIC CHARACTERIZATION OF ANALOG-TO-DIGITAL CONVERTERS DIGITAL OUTPUT CODES Table 10.5-2 - Digital Output Codes used for ADCs Decimal
Binary
Thermometer
Gray
0 1 2 3 4 5 6 7
000 001 010 011 100 101 110 111
0000000 0000001 0000011 0000111 0001111 0011111 0111111 1111111
000 001 011 010 110 111 101 100
Chapter 10 - DA and AD Converters (6/4/01)
Two s Complement 000 111 110 101 100 011 010 001
© P.E. Allen, 2001
Page 10.5-6
CMOS Analog IC Design
INPUT-OUTPUT CHARACTERISTICS Ideal input-output characteristics of a 3-bit ADC 111 Infinite Resolution Characteristic
Digital Output Code
110 101
1 LSB 100 Ideal 3-bit Characteristic
011 010 1 LSB 001
Quantization Noise LSBs
000
1.0
0.5 0.0 -0.5
vin VREF 0 8
1 8
2 3 4 5 6 7 8 8 8 8 8 8 Analog Output Value Normalized to VREF
8 8 Fig. 10.5-3
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-7
CMOS Analog IC Design
DEFINITIONS • The dynamic range, signal-to-noise ratio (SNR), and the effective number of bits (ENOB) of the ADC are the same as for the DAC • Resolution of the ADC is the smallest analog change that can be distinguished by an ADC. • Quantization Noise is the ±0.5LSB uncertainty between the infinite resolution characteristic and the actual characteristic. • Offset Error is the horizontal difference between the ideal finite resolution characteristic and actual finite resolution characteristic • Gain Error is the horizontal difference between the ideal finite resolution characteristic and actual finite resolution characteristic which is proportional to the analog input voltage. 111
110
Ideal Characteristic
101 100 011 010
Offset = 1.5 LSBs
001 000
0 8
1 8
2 8
3 8
4 8
5 8
6 8
7 8
vin 8 VREF 8
Example of offset error for a 3-bit ADC.
Chapter 10 - DA and AD Converters (6/4/01)
Digital Output Code
Digital Output Code
111
Gain Error Ideal Characteristic
110 101 100 011 010 001 000
0 8
1 8
2 8
3 8
4 8
5 8
6 8
7 8
8 8
vin VREF
Example of gain error for a 3-bit ADC.
Fig. 10.5-4
© P.E. Allen, 2001
Page 10.5-8
CMOS Analog IC Design
INTEGRAL AND DIFFERENTIAL NONLINEARITY The integral and differential nonlinearity of the ADC are referenced to the vertical (digital) axis of the transfer characteristic. • Integral Nonlinearity (INL) is the maximum difference between the actual finite resolution characteristic and the ideal finite resolution characteristic measured vertically (% or LSB) • Differential Nonlinearity (DNL) is a measure of the separation between adjacent levels measured at each vertical step (% or LSB). DNL = (Dcx - 1) LSBs where Dcx is the size of the actual vertical step in LSBs. Note that INL and DNL of an analog-digital converter will be in terms of integers in contrast to the INL and DNL of the digital-analog converter. As the resolution of the ADC increases, this restriction becomes insignificant.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-9
CMOS Analog IC Design
EXAMPLE OF INL and DNL
111
Ideal Characteristic
Digital Output Code
110
INL = +1LSB
101
Actual Characteristic
100 011
INL = -1LSB
DNL = +1LSB
010 001
DNL = 0 LSB
vin 000 0 1 2 3 4 5 6 7 8 VREF 8 8 8 8 8 8 8 8 8 Example of INL and DNL for a 3-bit ADC.) Fig.10.5-5
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.5-10
CMOS Analog IC Design
MONOTONICITY A monotonic ADC has all vertical jumps positive. Note that monotonicity can only be detected by DNL. Example of a nonmonotonic ADC: 111
Actual Characteristic
Digital Output Code
110 101 100
DNL = -2 LSB
011
Ideal Characteristic
010 001 000
0 8
1 8
2 8
4 8
3 8
5 8
6 8
7 8
8 8
vin VREF
Fig. 10.5-6L
If a vertical jump is 2LSB or greater, missing output codes may result. If a vertical jump is -1LSB or less, the ADC is not monotonic.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-11
CMOS Analog IC Design
EXAMPLE 10.5-2 INL and DNL of a 3-bit ADC Find the INL and DNL for the 3-bit ADC shown on the previous slide. Solution With respect to the digital axis: 1.) The largest value of INL for this 3-bit ADC occurs between 3/16 to 5/16 or 7/16 to 9/16 and is 1LSB. 2.) The smallest value of INL occurs between 11/16 to 12/16 and is -2LSB. 3.) The largest value of DNL occurs at 3/16 or 6/8 and is +1LSB. 4.) The smallest value of DNL occurs at 9/16 and is -2LSB which is where the converter becomes nonmonotonic. 111
Actual Characteristic
Digital Output Code
110
INL = -2LSB
101 100
INL = +1LSB
011
Ideal Characteristic
010
DNL = +1 LSB
001 000
DNL = -2 LSB
0 8
1 8
Chapter 10 - DA and AD Converters (6/4/01)
2 8
3 8
4 8
5 8
6 8
7 8
8 8
vin VREF
Fig. 10.5-6DL
© P.E. Allen, 2001
Page 10.5-12
CMOS Analog IC Design
DYNAMIC CHARACTERISTICS The dynamic characteristics of ADCs are influenced by: • Comparators • Sample-hold circuits • Circuit parasitics • Logic propagation delay
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-13
CMOS Analog IC Design
COMPARATOR The comparator is the quantizing unit of ADCs. Open-loop model: VOS + Comparator
V1 Ri
Vi Av(s)Vi
Ro
Vo
V2 Fig.10.5-7
Nonideal aspects: • Input offset voltage, VOS (a static characteristic) • Propagation time delay - Bandwidth (linear) Av(0) Av(0) = sτ + 1 Av(s) = s c ωc+1 - Slew rate (nonlinear) C·∆V ∆T = I (I is constant)
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.5-14
CMOS Analog IC Design
LINEAR PROPAGATION TIME DELAY (Small input changes) If VOH and VOL are the maximum and minimum output voltages of the comparator, then minimum input to the comparator (resolution) is VOH - VOL vin(min) = A (0) v VOH+VOL If the propagation time delay, tp, is the time required to go from VOH or from VOL to , then if 2 vin(min) is applied to the comparator, the tP is, VOH - VOL VOH - VOL = Av(0) [1- e-tp/τc] vin(min) = Av(0) [1- e-tp/τc] A (0) 2 v Therefore, tp is tp(max) = τc ln(2) = 0.693τc If vin is greater than vin(min), i.e. vin = kvin(min), then 2k tp = τc ln2k -1
Illustration of these results: vout VOH
vin
+ -
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design
vout
vin > vin(min) VOH+VOL 2 vin = vin(min)
VOL 0 t t (max) 0 p p
t Fig.10.5-8
© P.E. Allen, 2001 Page 10.5-15
NONLINEAR PROPAGATION TIME DELAY (Large input changes) The output rises or falls with a constant rate as determined by the slew rate, SR. ∆ V VOH - VOL ∴ tp = ∆ T = SR = 2·SR (If the rate of the output voltage of the comparator never exceeds SR , then the propagation time delay is determined by the previous expression.)
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.5-16
CMOS Analog IC Design
EXAMPLE 10.5-2 Propagation Delay Time of a Comparator Find the propagation delay time of an open loop comparator that has a dominant pole at 103 radians/sec, a dc gain of 104, a slew rate of 1V/µs, and a binary output voltage swing of 1V. Assume the applied input voltage is 10mV. Solution The input resolution for this comparator is 1V/104 or 0.1mV. Therefore, the 10mV input is 100 times larger than vin(min) giving a k of 100. Using the previous expression for this case, we get 1 2·100 200 tp = 103 ln2·100-1 = 10-3 ln199 = 5.01µs If the output is slew-rate limited, then 1 tp = 2·1x106 = 0.5µs Therefore, the propagation delay time for this case is the larger or 5.01µs. Note that the maximum slope of the linear response is Av(0) Av(0) Av(0)ωc 104·103 dvout d Max dt = dt Av(0)[1-e-t/τc](0.01V) = τ e-t/τc(0.01V) = 100τ = 100 = 100 = 0.1V/µs c c Since the maximum rate of the linear response is less than the slew rate, the response is linear and the propagation time delay is 5.01µs.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-17
CMOS Analog IC Design
SAMPLE-AND-HOLD CIRCUIT Waveforms of a sample-and-hold circuit: S/H Command
Amplitude
Hold vin*(t)
Sample
Hold
ta
ts
Output of S/H valid for ADC conversion vin*(t)
vin(t)
vin(t) Time
Fig.10.5-9
Definitions: • Acquisition time (ta) = time required to acquire the analog voltage • Settling time (ts) = time required to settle to the final held voltage to within an accuracy tolerance ∴ Tsample = ta + ts
→
Maximum sample rate = fsample(max) = T
1
sample
Other consideratons: • Aperture time= the time required for the sampling switch to open after the S/H command is initiated • Aperture jitter = variation in the aperture time due to clock variations and noise Types of S/H circuits: • No feedback - faster, less accurate • Feedback - slower, more accurate
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.5-18
CMOS Analog IC Design
OPEN-LOOP, BUFFERED S/H CIRCUIT Circuit:
vin(t)
vin(t), vout(t)
-
vout(t)
+
CH
Amplitude
φ
Switch Closed (sample)
vout(t) vin(t) Switch Open (hold) Time
vin(t), vout(t) Switch Closed (sample) Fig.10.5-10
Attributes: • Fast, open-loop • Requires current from the input to charge CH • DC voltage offset of the op amp and the charge feedthrough of the switch will create dc errors
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-19
CMOS Analog IC Design
SETTLING TIME Assume the op amp has a dominant pole at -ωa and a second pole at -GB. The unity-gain response can be approximated as, GB2 A(s) ≈ s2 + GB·s + GB2 The resulting step response is,
4 -0.5GB·t 3 e sin GB·t + φ 3 4 Defining the error as the difference between the final normalized value and vout(t), gives,
vout(t) = 1 -
4 -0.5GB·t 3e In most ADCs, the error is equal to ±0.5LSB. Since the voltage is normalized, we can write Error(t) = ε = 1 - vout(t) =
1 = 2N+1
4 N 2 3 Solving for the time, ts, required to settle with ±0.5LSB from the above equation gives ts
2 = GB
4 -0.5GB·t s 3e
→
e 0.5GB·ts =
1 4 N 2 = GB [1.3863N + 1.6740] 3
ln
Thus as the resolution of the ADC increases, the settling time for any unity-gain buffer amplifiers will increase. For example, if we are using the open-loop, buffered S/H circuit in a 10 bit ADC, the amount of time required for the unity-gain buffer with a GB of 1MHz to settle to within 10 bit accuracy is 2.473µs.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.5-20
CMOS Analog IC Design
OPEN-LOOP, SWITCHED-CAPACITOR S/H CIRCUIT Circuit: + vin(t)
C φ1d
φ2
+ φ1
vout (t)
φ1d
C φ2
+ φ1
-
vin(t)
-
+ vout (t)
φ2
-
φ1
+
-
φ1d C Differential switched-capacitor S/H
Switched capacitor S/H circuit.
Fig.10.5-11
• Delayed clock used to remove input dependent feedthrough. • Differential version has lower PSRR, cancellation of even harmonics, and reduction of charge injection and clock feedthrough
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-21
CMOS Analog IC Design
OPEN-LOOP, DIODE BRIDGE S/H CIRCUIT Circuit: VDD
VDD
Clock D1 vin(t)
D3 Clock
IB
IB
D2
D4
vout(t)
IB
D5
D1
D2
-
D3
D4
+
vin(t)
CH
vout(t)
CH
IB VSS
Diode bridge S/H circuit.
Hold
M1 M2
D6 Sample
2IB VSS Practical implementation of the diode bridge S/H. Fig.10.5-12
Attributes: • Fast • Clock feedthrough is signal independent • Sample uncertainty caused by the finite slope of the clocks is minimized • During the hold phase the feedthrough from input to hold node is minimized because of D5 and D6
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.5-22
CMOS Analog IC Design
CLOSED-LOOP S/H CIRCUIT Circuit: φ1
-
- φ2
vin(t)
+
+
φ1
vout(t)
vin(t)
CH
φ1
+ -
-
CH Closed-loop S/H circuit. φ1 is the sample phase and φ2 is the hold phase.
vout(t)
+
φ2
An improved version. Fig.10.5-13
Attributes: • Accurate • First circuit has signal-dependent feedthrough • Slower because of the op amp feedback loop
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-23
CMOS Analog IC Design
CLOSED-LOOP, SWITCHED CAPACITOR S/H CIRCUITS Circuit: CH φ1 CH
φ2 vin(t) φ1d CH
φ1 -
+ vout(t)
+
Switched capacitor S/H circuit which autozeroes the op amp input offset voltage.
vin(t)
-
φ1d φ2d
φ1
φ2
CH
φ1d
φ2d
φ2
+ -+ +-
φ2d φ1 φ1d
CH
φ2 φ2
vout(t)
CH
φ CH 1d
φ1 φ2d A differential version that avoids large changes at the op amp output Fig.10.5-14
Attributes: • Accurate • Signal-dependent feedthrough eliminated by a delayed clock • Differential circuit keeps the output of the op amps constant during the φ1 phase avoiding slew rate limits
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.5-24
CMOS Analog IC Design
CURRENT-MODE S/H CIRCUIT Circuit: VDD IB
iin φ1
iout φ2
φ1
CH Fig.10.5-15
Attributes: • Fast • Requires current in and out • Good for low voltage implementations
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-25
CMOS Analog IC Design
APERATURE JITTER IN S/H CIRCUITS Illustration: vin
Clock Analog Input
Analog-Digital Converter
Digital Output
∆V t
Aperature Jitter = ∆t Fig.10.5-16
If we assume that vin(t) = Vpsinωt, then the maximum slope is equal to ωVp. Therefore, the value of ∆V is given as dvin ∆ V = dt ∆ t = ω V p∆ t . The rms value of this noise is given as
ω V p∆ t dvin ∆V(rms) = dt ∆ t = . 2 2 The aperature jitter can lead to a limitation in the desired dynamic range of an ADC. For example, if the aperature jitter of the clock is 100ps, and the input signal is a full scale peak-to-peak sinusoid at 1MHz, the rms value of noise due to this aperature jitter is 111µV(rms) if the value of VREF = 1V.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.5-26
CMOS Analog IC Design
TESTING OF ADCs INPUT-OUTPUT TEST FOR AN ADC Test Setup:
N-bit ADC under test
Vin
Digital Word Output (N bits)
Qn = Vin-Vin'
DAC with Vin' more resolution than ADC + (N+2 bits)
Σ
Fig.10.5-17
The ideal value of Qn should be within ±0.5LSB Can measure: • Offset error = constant shift above or below the 0 LSB line • Gain error = contant increase or decrease of the sawtooth plot as Vin is increased • INL and DNL (see following page)
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-27
CMOS Analog IC Design
ILLUSTRATION OF THE INPUT-OUTPUT TEST FOR A 4-BIT ADC
Quantization Noise (LSBs)
2.0 LSB 1.5 LSB
+2LSB INL
1.0 LSB 0.5 LSB
-2LSB DNL
0.0 LSB -0.5 LSB
+2LSB DNL
-1.0 LSB -1.5 LSB -2.0 LSB 0 16
-2LSB INL
1 16
2 16
3 16
4 16
Chapter 10 - DA and AD Converters (6/4/01)
5 6 7 8 9 10 11 12 13 14 15 16 16 16 16 16 16 16 16 16 16 16 16 16 Fig.10.5-18 Analog Input Normalized to VREF
© P.E. Allen, 2001
Page 10.5-28
CMOS Analog IC Design
MEASUREMENT OF NONLINEARITY USING A PURE SINUSOID This test applies a pure sinusoid to the input of the ADC. Any nonlinearity will appear as harmonics of the sinusoid. Nonlinear errors will occur when the dynamic range (DR) is less than 6N dB where N = number of bits. Vin
fsig t VREF
Harmonic Vin free sinusoid
1 0 0 1
1 1 1 1
0 1 1
1
1 0 0 0
1 0 0 0
Vout(DAC)
|Vout(jω)| DR
t VREF
fsig
N-bit Distortion DAC Vout(DAC) or with N+2 Spectrum bits Analyzer resolution
N-bit ADC under test
Noise floor due to nonlinearities ω
Spectral Output
Fig. 10.5-19A
Clock
Comments: • Input sinusoid must have less distortion that the required dynamic range • DAC must have more accuracy than the ADC
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-29
CMOS Analog IC Design
FFT TEST FOR AN ADC Test setup: Clock fc
Pure Sinusoidal Input, fin
AnalogDigital Converter
Fast RAM Buffer
FFT Postprocessor
Frequency Spectrum Fig.10.5-19B
Comments: • Stores the digital output codes of the ADC in a RAM buffer • After the measurement, a postprocessor uses the FFT to analyze the quantization noise and distortion components • Need to use a window to eliminate measurement errors (Raised Cosine or 4-term Blackmann-Harris are often used) • Requires a spectrally pure sinusoid
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.5-30
CMOS Analog IC Design
Number of Occurances
HISTOGRAM TEST FOR AN ADC The number of occurances of each digital output code is plotted as a function of the digital output code. Illustration:
0
Sinusoidal Input
0
Triangular Input Output Full Code Scale
Mid Scale
Fig.10.5-20
Comments: • Emphasizes the time spent at a given level and can show DNL and missing codes • DNL H(i)/Nt Width of the bin as a fraction of full scale DNL(i) = Ratio of the bin width to the ideal bin width -1 = P(i) -1 where H(i) = number of counts in the ith bin Nt = total number of samples P(i) = ratio of the bin width to the ideal bin width • INL is found from the cumulative bin widths
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.5-31
CMOS Analog IC Design
COMPARISON OF THE TESTS FOR ANALOG-DIGITAL CONVERTERS Other Tests • Sinewave curve fitting (good for ENOB) • Beat frequency test (good for a qualitative measure of dynamic performance) Comparison Test→ Error ↓
Histogram or Code Test Yes (spikes)
FFT Test
Sinewave Curve Fit Test Yes
Beat Frequency Test Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
No
Noise
No
Bandwidth Errors
No
Yes (Elevated noise floor) Yes (Elevated noise floor) Yes (Harmonics in the baseband) Yes (Elevated noise floor) Yes (Elevated noise floor) No
Gain Errors Offset Errors
Yes (Peaks in distribution)
No
No
Yes (Measures analog bandwidth) No
Yes (Offset of distribution average)
No
No
No
DNL Missing Codes INL Aperature Uncertainty
Yes (Bin counts with zero counts) Yes (Triangle input gives INL directly) No
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.5-32
CMOS Analog IC Design
BIBLIOGRAPHY ON ADC TESTING 1.) D. H. Sheingold, Analog-Digital Conversion Handbook, Analog Devices, Inc., Norwood, MA 02062, 1972. 2.) S.A. Tretter, Introduction to Discrete-Time Signal Processing, John Wiley & Sons, New York, 1976. 3.) J. Doernberg, H.S. Lee, and D.A. Hodges, Full-Speed Testing of A/D Converters, IEEE J. of SolidState Circuits, Vol. SC-19, No. 6, December 1984, pp. 820-827. 4.) Dynamic performance testing of A to D converters, Hewlett Packard Product Note 5180A-2.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.6-1
CMOS Analog IC Design - Chapter 10
10.6 - SERIAL ANALOG-DIGITAL CONVERTERS INTRODUCTION Serial ADCs typically require 2NT for conversion where T = period of the clock Types: • Single-slope • Dual-slope SINGLE-SLOPE ADC Block diagram: vin* VREF
nT
Interval Counter
0
0
nT
+ -
vT Ramp Generator vT * v in Reset
T
t Output Counter
nT
Clock
Output
n≤N
t
t
Fig.10.6-1
f =1/T
Attributes: • Simplicity of operation • Subject to error in the ramp generator • Long conversion time ≤ 2NT
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.6-2
CMOS Analog IC Design - Chapter 10
DUAL-SLOPE ADC Block diagram:
Waveforms:
1
vin*
Positive Integrator
2
-VREF
vint Vth
vin VREF+Vth
+ -
Digital Control Carry Output
NREFT
t1 = NREFT vin''' vin''' > vin'' > vin'. vin'' vin'
Binary Output
Counter
Vth 0
0
Fig.10.6-2
Reset
t0(start)
Operation:
t2'
t t2'' t2''' t2= NoutT
Fig.10.6-3
1.) Initially vint = 0 and vin is sampled and held (vIN* > 0). 2.) Reset the positive integrator by integrating a positive voltage (not shown) until vint (0) = Vth.. 3.) Integrate vin* for NREF clock cycles to get, ⌠NREFT
vint(t1) = K ⌡0
vin* dt + vint(0) = KNREFTvin* + Vth 4.) At the end of NREF counts, the carry output of the counter is applied to switch 2 and-VREF. is applied to the positive integrator. The output of the integrator decreases until vint(t) = Vth at t = t1+t2. Thus, ⌠NoutT
vint(t1+t2) = vint(t1) + K ⌡ t
1
5.) Solving for Nout gives, Comments:
(−VREF) dt =Vth
→
KNREFTvin* + Vth - KNoutTVREF = Vth
vin* Nout = NREF V
REF
Conversion time ≤ 2(2N)T and the operation is independent of Vth and K.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.7-1
CMOS Analog IC Design
10.7 - MEDIUM SPEED ANALOG-DIGITAL CONVERTERS INTRODUCTION Successive Approximation Algorithm: 1.) Start with the MSB bit and work toward the LSB bit. 2.) Guess the MSB bit as 1. 3.) Apply the digital word 10000.... to a DAC. 4.) Compare the DAC output with the sampled analog input voltage. 5.) If the DAC output is greater, keep the guess of 1. If the DAC output is less, change the guess to 0. 6.) Repeat for the next MSB. If the number of bits is N, the time for conversion will be NT where T is the clock period. Illustration: vguess VREF 0.75VREF 0.50VREF 0.25VREF 0
0
1
2
3
4
t 6 T
5
Fig.10.7-2
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.7-2
CMOS Analog IC Design
BLOCK DIAGRAM OF A SUCCESSIVE APPROXIMATION ADC†
Vin*
VREF
+ Comparator
Digital-Analog Converter
Output Register
Output
Shift Register
Conditional Gates
Clock
Fig.10.7-1
† R. Hnatek, A User's Handbook of D/A and A/D Converters, JohnWiley and Sons, Inc., New York, NY, 1976.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.7-3
CMOS Analog IC Design
5-BIT SUCCESSIVE APPROXIMATION ADC vIA
vOA CompAnalog arator In + MSB Analog Switch 1
5-bit Digital-Analog Converter
VREF
Analog Switch 2
Analog Switch 3
Analog Switch 4
LSB Analog Switch 5
0 1 FF1 R RD S
0 1 FF2 R RD S
0 1 FF3 R RD S
0 1 FF4 R RD S
0 1 FF5 R RD S
G1
G2
G3
G4
G5
LSB
MSB Gate -1 Delay Delay
Clock pulses
SR1 Start pulse
1
SR2
1
The delay allows for the circuit transients to settle before the comparator output is sampled.
SR3
1
1
SR4
1
SR5
Shift Register Fig.10.7-3
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.7-4
CMOS Analog IC Design
m-BIT VOLTAGE-SCALING, k-BIT CHARGE-SCALING SUCCESSIVE APPROX. ADC Implementation: m-MSB bits m-bit, MSB voltage scaling subDAC
VREF
R2 R3
Bus A R2m-2 R2m-1 R2m
m-to-2m Decoder B m-MSB bits Vin* m-MSB bits
Fig.10.7-4
C2= 2C
C1= C
Sk,A
Sk-1,A
S2A
S1A
Sk,B
Sk-1,B
S2B
S1B
C
SB
Bus B k-bit, LSB charge SF scaling subDAC Capacitor Switches Clock SF Successive approximation register & switch control logic
(m+k) bit output of ADC
-
R1
Ck-1= 2k-2C
+
m-to-2m Decoder A
Ck = 2k-1C
Start
Operation: 1.) With the two SF switches closed, all capacitors are paralleled and connected to Vin* which autozeros the comparator offset voltage. 2.) With all capacitors still in parallel, a successive approximation search is performed to find the resistor segment in which the analog signal lies. 3.) Finally, a successive approximation search is performed on charge scaling subDAC to establish the analog output voltage.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.7-5
CMOS Analog IC Design
VOLTAGE-SCALING, CHARGE-SCALING SUCCESSIVE APPROX. DAC - CONTINUED Autozero Step vC Removes the influence of the + VOS offset voltage of the comparator. k 2 C The voltage across the capacitor + Vin* + is given as, V OS vC = Vin* - VOS Fig.10.7-5
Successive Approximation Search on the Resistor String The voltage at the comparator input is
Busses A and B V*in
vcomp = VRi - Vin* If vcomp > 0, then VRi > Vin*
VRi=V'REF
+
vcomp 2kC -
-
+
If vcomp < 0, then VRi < Vin* Successive Approximation Search on the Capacitor SubDAC The input to the comparator is written as, Ceq 2kC-Ceq vcomp = (VRi+1 - Vin* ) k + (VRi - Vin* ) k 2C 2C VRi+1 However, VRi+1 = VRi + 2-mVREF + -mVREF 2 Combining gives, 2kC-Ceq C VRi=V'REF * ) eq + (V -V * ) vcomp = (VRi + 2-mVREF -VIN Ri IN 2kC 2 kC Ceq * + 2-m V = V Ri - V IN REF 2kC
Fig.10.7-6a
Bus V*in Ceq. A + -
2kC - Ceq.
Bus B +
vcomp +
V*in Fig.10.7-6b
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.7-6
CMOS Analog IC Design
A SUCCESSIVE APPROXIMATION ADC USING A SERIAL DAC Implementation: Vin*
+ -
VDAC
S2 precharge VREF
Start Clock
Serial DAC (Fig. 10.4-1)
Data storage register
1
DAC control register
S3 discharge S1 charge share S4 reset
Sequence and control logic Fig.10.7-7
Conversion Sequence: Digital-analog Conversion Number 1 2 3 . . . N
Digital-analog Input Word d1 1 1 1 . . . 1
d2
d3
...
aN aN-1 . . . a2
aN . . . a3
d1
...
Comparator
dN-1
dN
. . . aN-1
. . . aN
Output aN aN-1 aN-2 . . . a1
Number of Charging Steps 2 4 6 . . . 2N
Total number of charging steps = N(N+1)
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.7-7
CMOS Analog IC Design
A SUCCESSIVE APPROXIMATION ADC USING A SERIAL DAC - CONTINUED Example: Analog input is 13/16.
vc1/VREF
1.00
1xxx
11xx
111x
1101 13/16
0.75 0.50 0.25 0.00 0 1 2 0 1 2 3 4 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 1 bit
2 bits
3 bits
t/T
4 bits
vc2/VREF
1.00 0.75 0.50 0.25 0.00 0 1 2 0 1 2 3 4 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8
t/T
Fig.10.7-8
Digital word out is b0 = 1, b1 = 1, b2 = 0, and b3 = 1.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.7-8
CMOS Analog IC Design
PIPELINE ANALOG-DIGITAL ALGORITHMIC CONVERTER Implementation: LSB
MSB + -
Vin*
2
Σ ±1
z-1
VREF
Stage 1
+ -
z-1
+ -
+ -
Vi-1
2
Σ ±1
z-1
2
Σ ±1
Vi
z-1
i-th stage
Stage 2
Stage N Fig.10.7-9
Operation: • Each stage muliplies its input by 2 and adds or subtracts VREF depending upon the sign of the input. • i-th stage, V i = 2V i-1 - biV REF where bi is given as +1 if Vi-1>0 bi = -1 if V 0? Bit i 1 2V Yes 1 2 (2V·2) - 5 = -1V No 0 3 (-1V·2) + 5 = 3V Yes 1 4 (3V·2) - 5 = 1V Yes 1 Illustration: Stage Ouputs normalized to V REF
1
Stage 4
0.8 0.6 0.4
1 1 1 1 Vanalog = 52 − 4 + 8 + 16
Stage 3
0.2 0
= 5(0.4375) = 2.1875
Stage 2
where bi = +1 if the ith-bit is 1
-0.2 -0.4
and bi = -1 if the ith bit is 0
Stage 1
-0.6 -0.8 -1
-1
-0.8 -0.6 -0.4 -0.2 0 0.2 V in*/V REF
0.4
0.6
0.8
1
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.7-10
CMOS Analog IC Design
ACHIEVING THE HIGH SPEED POTENTIAL OF THE PIPELINE ALGORITHMIC ADC If shift registers are used to store the output bits and align them in time, the pipeline ADC can output a digital word at every clock cycle with a latency of NT. Illustration: MSB SR
MSB-1
SR
SR
SR
SR
SR
SR
Digital Ouput Word
i-th Bit SR LSB
+ -
Vin* VREF
z-1
2
Σ ±1
Stage 1
+ -
z-1
2
Σ ±1
Stage 2
+ -
+ -
Vi-1
z-1
2
Σ ±1
i-th stage
Vi
z-1
Stage N Fig.10.7-9B
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.7-11
CMOS Analog IC Design
ERRORS IN THE PIPELINE ALGORITHMIC ADC The output voltage for the N-th stage can be written as, i=1
VN = ∏ AiVin N
i=1 N A b + b ) V Σ ∏ j j N REF N-1j = i+1
where Ai (Aj) is the actual gain of 2 for the i-th ( j-th) stage. Errors include: 1.) Gain errors - x2 amplifier or summing junctions 2.) Offset errors - comparator or summing junctions i-th stage including errors, V i = A iV i-1 + V OSi - biA siV REF = +1 if Vi-1>VOCi bi = = -1 if V VREF. V REF ∆A1 ≤ 3 ∴ 2 Vin
∆Α1 1 The smallest value of ∆A1 occurs when Vin = VREF which gives A ≤ 4 . 2 1 It can be shown that the tolerance of A2 will be half of the tolerance of A1, and so forth. V REF V REF ∆Α 1 1 Generally, A ≤ N , V OS1 ≤ N , and V OC1 ≤ N 2 2 2 1
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.7-13
CMOS Analog IC Design
EXAMPLE 10.7-2 Accuracy requirements for a 4-bit pipeline algorithmic ADC Show that if Vin = VREF, that the pipeline algorithmic ADC will have an error in the 5th bit if the gain of the first stage is 2-(1/8) =1.875 which corresponds to when an error will occur. Show the influence of Vin on this result for values of Vin of 0.65VREF and 0.20VREF. Solution For Vin = VREF, we get the following results shown in the table below. The input to the fifth stage is 0V which means that the bit is uncertain. If A1 was slightly less than 1.875, the fifth bit would be 0 which would be in error. This result of course assumes that all stages but the first are ideal. i 1 2 3 4 5
Vi(ideal) 1 1 1 1 1
Bit i (ideal) 1 1 1 1 1
Vi(A1=1.875) 1.000 0.875 0.750 0.500 0.000
Bit i (A1=1.875) 1 1 1 1 ?
Now let us repeat the above results for Vin = 0.65VREF. The results are shown below. We see that now an error occurs in the fourth (LSB) bit. i 1 2 3 4
Vi(ideal) +0.65 +0.30 -0.40 +0.20
Bit i (ideal) 1 1 0 1
Vi(A1=1.875) 0.65 0.21875 -0.5625 -0.1250
Bit i (A1=1.875) 1 1 0 0
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.7-14
CMOS Analog IC Design
EXAMPLE 10.7-2 - CONTINUED Next, we repeat for the results for Vin = 0.20VREF. The results are shown below. We see that no error occurs in the fourth (LSB) bit. i 1 2 3 4
Vi(ideal) +0.20 -0.60 -0.20 +0.60
Bit i (ideal) 1 0 0 1
Vi(A1=1.875) 0.20 -0.625 -0.250 0.500
Bit i (A1=1.875) 1 0 0 1
Note the influence of Vin in the fact that an error occurs for A1= 1.875 for Vin = 0.65VREF but not for Vin = 0.2VREF. Why? Note on the plot for the output of each stage, that for Vin = 0.65VREF, the output of the fourth stage is close to 0V so any small error will cause problems. However, for Vin = 0.2VREF, the output of the fourth stage is at 0.6VREF which is further away from 0V and is less sensitive to errors. ∴ The most robust values of Vin will be near -VREF , 0 and +VREF. or when each stage output is furthest from the comparator threshold, 0V.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.7-15
CMOS Analog IC Design
ITERATIVE (CYCLIC) ALGORITHMIC ANALOG-DIGITAL CONVERTER The pipeline algorithmic ADC can be reduced to a single stage that cycles the output back to the input. Implementation: +
Voi
x2
-
+1
Sample and Hold
Σ
+VREF
+1
-VREF
+ -
Va
x2
Sample and Hold
Vb
+1
Vo
VREF
Σ
Vo ="1"
+1
-VREF
Vo ="0"
S1
Vin* Different version of iterative algorithm ADC implementation
Iterative algorithm ADC
Fig. 10.7-13
Operation: 1.) Sample the input by connecting switch S1 to Vin*. 2.) Multiply Vin * by 2. 3.) If Va , is greater than VREF set the corresponding bit = 1 and subtract VREF from Va.. If Va , is less than VREF set the corresponding bit = 0 and add zero to Va.. 4.) Repeat until all N bits have been converted.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.7-16
CMOS Analog IC Design
EXAMPLE 10.7-3 Conversion Process of an Iterative, Algorithmic Analog-Digital Converter The iterative, algorithmic analog-digital converter is to be used to convert an analog signal of 0.8VREF. The figure below shows the waveforms for Va and Vb during the process. T is the time for one iteration cycle. 1.) The analog input of 0.8VREF givesVa = 1.6VREF and a value of Vb = 0.6VREF and the MSB as 1. 2.) Vb is multiplied by two to give Va = 1.2VREF. Thus the next bit is also 1 and Vb = 0.2VREF.. 3.) The third iteration givesVa = 0.4VREF, making the next bit 0 and Vb = 0.4VREF . 4.) The fourth iteration gives Va = 0.8VREF, which gives Vb = 0.8VREF and the fourth bit as 0. 5.) The fifth iteration gives Va = 1.6VREF, Vb = 0.6VREF and the fifth bit as 1. The digital word after the fifth iteration is 11001 and is equivalent to an analog voltage of 0.78125VREF. Va/VREF 2.0 1.6 1.2 0.8 0.4 0.0
Vb/VREF
;;;; ;;;; ;;;; ;;;; ;;;; ;;;; 2.0 1.6 1.2 0.8 0.4
0
1
2
3
4
5
t/T
0.0
0
1
2
3
4
5
t/T
Fig. 10.7-14.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.7-17
CMOS Analog IC Design
SELF-CALIBRATING ANALOG-DIGITAL CONVERTERS Self-calibration architecture for a m-bit charge scaling, k-bit voltage scaling successive approximation ADC To Successive Approximation Register
- S1
m-bit subDAC
+
C1
C2
C3
Cm-1
Cm
Cm
VREF Register m+2-bit k-bit Calibration subDAC DAC k-bits
m control lines Successive Approximation Register
Adder Data Register
Control Logic
m+k-bits Vε1
Data Output
Vε2 Fig.10.7-15
Comments: • Self-calibration can be accomplished during a calibration cycle or at start-up • In the above scheme, the LSB bits are not calibrated • Calibration can extend the resolution to 2-4 bits more that without calibration
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.7-18
CMOS Analog IC Design
SELF-CALIBRATING ANALOG-DIGITAL CONVERTERS - CONTINUED Self-calibration procedure starting with the MSB bit: 1.) Connect C1 to VREF and the remaining capacitors (C2+C3+···+Cm+Cm = C1 ) to ground with SF closed. 2.) Next, connect C1 to ground and C1 to VREF. C1
C1
+
VREF
VREF
C1 Connection of C1 to VREF.
Vx1 C1
+
VREF Connection of C1 to VREF. Fig.10.7-16
3.) The result will be Vx1 =
C1 -C1
C1 +
VREF.
C1
If C1 = C1 , then Vx1 = 0.
4.) If Vx1 ≠ 0, then the comparator output will be either high or low. Depending on the comparator output, the calibration circuitry makes a correction through the calibration DAC until the comparator output changes. At this point the MSB is calibrated and the MSB correction voltage, Vε1 is stored. 5.) Proceed to the next MSB with C1 out of the array and repeat for C2 and C2 . Store the correction voltage, Vε2, in the data register. 6.) Repeat for C3 with C1 and C2 out of the array. Continue until all of the capacitors of the MSB DAC have been corrected. Note that for any combination of MSB bits the calibration circuit adds the correct combined correction voltage during normal operation.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.7-19
CMOS Analog IC Design
SUMMARY OF MEDIUM SPEED ANALOG-DIGITAL CONVERTERS Medium speed ADCs generally use some form of successive approximation. Type of ADC Voltage-scaling, charge-scaling successive approximation ADC
Advantage High resolution
Disadvantage Requires considerable digital control circuitry
Successive approximation using a serial DAC Pipeline algorithmic ADC
Simple
Slow
Fast after initial latency of NT
Accuracy depends on input
Iterative algorithmic ADC
Simple
Requires other digital circuitry
Successive approximation ADCs also can be calibrated extending their resolution 2-4 bits more than without calibration.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-1
CMOS Analog IC Design
10.8 - HIGH SPEED ANALOG-DIGITAL CONVERTERS Conversion time is T where T is a clock period. Types: • Parallel or Flash ADCs • Interpolating ADCs • Folding ADCs • Speed-Area Tradeoffs - Multiple-Bit, Pipeline ADCs - Digital Error Correction • Time-Interleaved ADCs
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-2
CMOS Analog IC Design
PARALLEL OR FLASH ANALOG-DIGITAL CONVERTER A 3-bit, parallel ADC: VREF Vin*=0.7VREF R 0.875VREF R 0.750VREF R 0.625VREF R 0.500VREF R 0.375VREF R 0.250VREF R 0.125VREF
+ + + + + + +
1 1 0 0
2N-1 to N encoder
Output Digital Word 101
0 0 0
R Fig.10.8-1
Comments: • Fast, in the first phase of the clock the analog input is sampled and applied to the comparators. In the second phase, the digital encoding network determines the correct output digital word. • Number of comparator required is 2N-1 • Can put a sample-hold at the input or can used clocked comparators • Typical sampling frequencies can be as high as 400MHz for 6-bits in sub-micron CMOS technology.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-3
CMOS Analog IC Design
EXAMPLE 10.8-1 Influence of the Comparator Offset on the ADC Performance Two comparators are shown of an N-bit flash ADC. Comparators 1 and 2 VREF Vin have an offset voltage indicated as VOS1 and VOS2, respectively. A portion of the ideal transfer function of the converter is VOS2 R also shown. (a.) When do the comparator V + R2 + offsets cause a missing code? Express this 2 condition in terms of VOS1, VOS2, N, and R Encoder VOS1 + VREF. (b.) Assume all offsets are identical VR1 + 1 and express the magnitude of INL in R terms of VOS1(=VOS2), N, and VREF. (c.) Express the DNL in terms of VOS1, VOS2, N, and VREF.
VOS2 1 LSB
VOS1
VR1
Vin
VR2
Fig.10.8-2.
Solution (a.) We note that comparator 1 changes from a 0 to 1 when Vin(1) > VR1-VOS1 and comparator 2 changes from a 0 to 1 when Vin(2) > VR2-VOS2. A missing code will occur if Vin(2) < Vin(1). Therefore, V R2 - V OS2 > V R1 - V OS1
→
V R2 - V R1 > V OS2 - V OS`
But, V R2 - V R1 =
V REF 2N
→
Chapter 10 - DA and AD Converters (6/4/01)
|V OS2 - V OS1|
1V Therefore, slew rate does not influence the maximum conversion rate.
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design
© P.E. Allen, 2001 Page 10.8-7
OTHER ERRORS OF THE PARALLEL ADC • Resistor string error - if current is drawn from the taps to the resistor string this will create a “bowing” effect on the voltage. This can be corrected by applying the correct voltage to various points of the resistor string. • Input common mode range of the comparators - the comparators at the top of the string must operate with the same performance as the comparators at the bottom of the string. • Kickback or flashback - influence of rapid transition changes occuring at the input of a comparator. Can be solved by using a preamplifier or buffer in front of the comparator. • Metastability - uncertainty of the comparator output causing the transition of the thermometer code to not be distinct.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-8
CMOS Analog IC Design
INTERPOLATING ANALOG-DIGITAL CONVERTERS A 3-bit interpolating ADC using a factor of 4 interpolation: Vin
VREF V DD +A2
Vth V2 V2a V2b
R
VREF 2
VDD +A1
R R
-7 -6
8 to 3 encoder
+
-5
3-bit digital output
+
V1b
V2 V2a V2b V2c
+
R
V1
-8
+
V2c R
V1a R
Volts VDD
+
R
-4
1 2 3 4 5 6 7 8 Comparator Threshold
Vth
+
R
-3
V1c V1b V1a V1
+
V1c R R
-2
+
-1
0
Fig.10.8-3
0.5VREF
0
VREF
Vin Fig.10.8-4
Comments: • Loading of the input is reduced from 8 comparators to two amplifiers. • The outputs of the two amplifiers, V1 and V2, are interpolated through the resistor string and applied to the comparators. • Because of the amplification of the input amplifiers and a single threshold, the comparators can be simple and are often replaced by a latch. • If the dots in Fig. 10.8-4 are not equally spaced, INL and DNL will result. • The comparators no longer need a large ICMR
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-9
CMOS Analog IC Design
A 3-BIT INTERPOLATING ADC WITH EQUALIZED COMPARATOR DELAYS One of the problems in voltage (passive) interpolation is that the delay from the amplifier output to each comparator can be different due to different source resistance. Solution: Vin
VREF V DD +A2
Vth
V2a V2b
R VDD +A1
VREF 2
+
R R/4
V1
V1b
-8
+
R
-7
+
V2c R R/4
V1a R
R
V2
R R
-6
+
-5
+
R R/4
-4
8 to 3 encoder
3-bit digital output
+
R
-3
+
V1c R R/4 R
-2
+
-1
Fig.10.8-6
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-10
CMOS Analog IC Design
FOLDING ANALOG-DIGITAL CONVERTERS Allows the number of comparators to be reduced below the value of 2N-1. Architecture for a folded ADC:
Preprocessor
Coarse Quantizer
Vin Folding Preprocessor
Fine Quantizer
n1 bits
n2 bits
Encoding Logic
n1+n2 bits
Digital Output
Fig.10.8-7
Operation: The input is split into two or more parallel paths. • First path uses a coarse quantizer to quantize the signal into 2n1 values • The second path maps all of the 2n1 subranges onto a single subrange and applies this analog signal to a fine quantizer of 2n2 subranges. Thus, the total number of comparators is 2n1-1 + 2n2-1 compared with 2n1+n2-1 for a parallel ADC. I.e., if n1 = 2 and n2 = 4, the folding ADC requires 3 + 15 = 18 compared with 63 comparators.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-11
CMOS Analog IC Design
FOLDING PREPROCESSOR Illustration: FS/2
2n1 subranges
-FS/2
FS/F
2n2 subranges
Fig.10.8-8
Comments: • Folding is done simultaneously or in parallel so that only one clock cycle is needed for conversion. • Folding will tend to increase the bandwidth of the analog input by a factor of F. • Folding can reduce the power consumption and require less chip area.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-12
CMOS Analog IC Design
EXAMPLE OF A FOLDING PREPROCESSOR Folding characteristic for n1 = 2 and n2 = 3.
No Folding
n1 = 2 n2 = 3
32
After Analog Preprocessing
VREF
VREF 4
8
Folding
0 0 MSBs =
00
VREF
Analog Input 01 10
11
Fig.10.8-9
Problems: • The sharp discontinuities of the folder are difficult to implement at high speeds. • Fine quantizer must work at voltages ranging from 0 to VREF/4 (subranging).
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-13
CMOS Analog IC Design
MODIFIED FOLDING PREPROCESSORS The above problems can be removed by the following folding preprocessors: Folder that removes discontinuity problem. Vout VREF 8 0 -VREF 8
0
Vin VREF
Multiple folders allow a single value quantizer (comparator). Vout VREF 8 0 0 -VREF 8
Chapter 10 - DA and AD Converters (6/4/01)
Vin VREF Fig.10.8-10.
© P.E. Allen, 2001
Page 10.8-14
CMOS Analog IC Design
A 5-BIT FOLDING ADC USING 1-BIT QUANTIZERS (COMPARATORS) Block diagram: Coarse MSBs (n1=2)
Folder 2
+ -
Vin
5-bit digital output Decoder
Folder 1
+ -
2 bits
+ Comparators
Folder 7
3 bits LSBs
Fig.10.8-11
Comments: • Number of comparators is 7 for the fine quantizer and 3 for the course quantizer for 10 total • The zero crossings of the folders must be equally spaced to avoid linearity errors • The number of folders can be reduced and the comparators simplified by use of interpolation
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-15
CMOS Analog IC Design
FOLDING CIRCUITS Implementation of a times 4 folder: VDD
+VREF R
RL
Folding Outputs +V - out
RL
V8
R
I V7 V2
R R
I
V1
I
I
V2
V7
V8
I
V1 Vin
Vout +IRL
0
V1
V2
-IRL
V3
V4
V5
V6
V7
V8 VREF
Vin
Fig. 10.8-12A
Comments: • Horizontal shifting is achieved by modifying the topmost and bottom resistors of the resistor string • Folding and interpolation ADCs offer the most resolution at high speeds (≈8 bits at 200MHz)
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-16
CMOS Analog IC Design
SUMMARY OF INTERPOLATING AND FOLDING ADCs Advantages of Interpolation: • Large area and power reduction • Input capacitance reduced • Folder offset errors are averaged among interpolated signals Comments on Resistive Interpolation: • Low resistance is required for high speed implies high drive required from previous folding circuit • Guaranteed monotonicity of phase shift Comments on Active Interpolation: • Subject to additional offsets (fine active interpolation not recommended) • Lower drive necessary from initial folding circuits than for resistive interpolation
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design
© P.E. Allen, 2001 Page 10.8-17
USE OF A S/H IN FRONT OF THE FOLDING ADC Benefit of a S/H: • With no S/H, the folding circuit acts as an amplitude-dependent frequency multiplier. BW of ADC ≥ BW of Folding Circuit • With S/H, all inputs to the folding circuit arrive at the same time. - Therefore the folding circuit is no longer an amplitude-dependent frequency multiplier - BW of the ADC is now limited by the BW of the S/H circuit - Settling time of the folding and interpolating preprocessor is critical Single S/H versus Distributed S/H: • Single S/H requires high dynamic range for low THD • Dynamic range requirement for distributed S/H reduced by a factor equal to the number of S/H stages • If the coarse quantizer uses the same distributed S/H signals as the fine preprocessor, the coarse/fine synchronization is automatic • The clock skew between the distributed S/H stages must be small. The clock jitter will have a greater effect on the distributed S/H approach. Including a Preamplifier in the S/H circuit: • Reduces the effect of folding circuit input offset and comparator input offset • For a S/H distributed over D stages, then: - The preamp linear range requirement is the input range/D (all subsequent interpolated signals use this range) - The preamp input common mode range is the input range - The preamp output common mode range is small which implies the switch nonlinearity is not dependent on input signal amplitude
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-18
CMOS Analog IC Design
ERROR SOURCES AND LIMITATIONS OF A BASIC FOLDING ADC Error Sources: • Offsets in reference voltages due to resistor mismatch • Preamp offset (reduced by large input devices for low VGS-VT, with common-centroid geometry) • vin feedthrough to reference ladder via Cgs of input pairs loading the input places a maximum value on ladder resistance which is dependent on the input frequency. Also, the no. of preamp/folder circuits loading the input must be minimized. • Folder current-source mismatches (gives signal-dependent error⇒distortion) • Comparator kickback (driving nodes should be low impedance) • Comparator metastability condition (uncertainty of comparator output) • Misalignment between coarse and fine quantization outputs (large code errors are possible) Sampling Speed Limitations: • Folding output settling time • Comparator settling time • Clock distribution and layout • Clock jitter Input Bandwidth Limitations: • Maximum folding signal frequency ≥ (F/2)·fin, unless a S/H is used • Preamplifier has a limited linear range and frequency dependent delay which gives distortion • The folder has limited linear range and frequency dependent delay which gives distortion • Parasitic capacitance of routing to comparators
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-19
CMOS Analog IC Design
MULTIPLE-BIT, PIPELINE ANALOG-DIGITAL CONVERTERS A compromise between speed and resolution is to use a pipeline ADC with multiple bits/stage. i-th stage of a k-bit per stage pipeline ADC with residue amplification: Residue
Clock Vi-1
S/H VREF
VREF
k-bit ADC
k-bit DAC
Vi
+ Σ -
k-bits
Av =2k i-th stage Fig.10.8-13
bk-1 b k b1 b 2 Residue voltage = Vi-1 - 2 + 22 + ··· + 2k-1 + 2k VREF
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-20
CMOS Analog IC Design
A 3-STAGE, 3-BIT PER STAGE PIPELINE ADC Illustration of the operation: Stage 1 111 110 101 100 011 010 001 000
Stage 2 111 110 101 100 011 010 001 000
Stage 3 111 110 101 100 011 010 001 000
Clock 1 Digital output = 011
Clock 2 111
Clock 3 001
Voltage
VREF VREF 2
0
LSB
MSB
Time
Fig.10.8-14
Converted word is 011 111 001 Comments: • Only 21 comparators are required for this 9-bit ADC • Conversion occurs in three clock cycles • The residue amplifier will cause a bandwidth limitation, 50MHz GB = 50MHz → f-3dB = 23 ≈ 6MHz
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-21
CMOS Analog IC Design
SUBRANGING, MULTIPLE-BIT, PIPELINE ADCs The residue amplifier can be replaced by dividing VREF to the next stage by 2k if the stage has k-bits. Illustration of a 2-stage, 2-bits/stage pipeline ADC: VREF
Stage 1
Stage 2
11 0.7500VREF
Voltage
10 0.5000VREF 0.4375VREF 0.3750VREF 0.3125VREF 0.2500VREF
01
11 10 01 00
00
0
Clock 1 Digital output word = 01
Time Clock 2 10
Fig.10.8-15
Comments: • Resolution of the comparators for the following stages increases but fortunately, the tolerance of each stage decreases by 2k for every additional stage. • Removes the frequency limitation of the amplifier
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-22
CMOS Analog IC Design
IMPLEMENTATION OF THE DAC IN THE MULTIPLE-BIT, PIPELINE ADC Circuit: Analog * Out VREF Vin -
R
OFF
1
+ 0
R
-
1
+
ON 1 R
-
0
+
OFF 0 R
-
0
+
OFF 0
0 Fig.10.8-16
Comments: • A good compromise between area and speed • The ADC does not need to be a flash or parallel if speed is not crucial • Typical performance is 10 bits at 50Msamples/sec
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-23
CMOS Analog IC Design
EXAMPLE 10.8-3 Examination of error in subranging for a 2-stage, 2-bits/stage pipeline ADC The stages of the 2-stage, 2-bits/stage pipeline ADC shown below are ideal. However, the second stage divides VREF by 2 rather than 4. Find the ±INL and ±DNL for this ADC. Vin(2) Vin(1)
2-bit ADC
2-bit DAC VREF
VREF b1
b2
Σ Vout(1)
2-bit ADC VREF 2
2-bit DAC
b3
b4
Vout(2)
VREF 2 Fig.10.8-17
Solution Examination of the first stage shows that its output, Vout(1) changes at Vin(1) 1 2 3 4 VREF = 4, 4, 4, and 4 . The output of the first stage will be Vout(1) b1 b2 VREF = 2 + 4 . The second stage changes at Vin(2) 1 2 3 4 VREF = 8, 8, 8, and 8 where Vin(2) = Vin(1) - Vout(1). The above relationships permit the infomation given in Table 10.8-1.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-24
CMOS Analog IC Design
EXAMPLE 10.8-3 - CONTINUED Table 10.8-1 Output digital word for Ex. 10.8-3 b3 b4
Ideal Ouput b 1 b 2 b3 b4
0 1/16 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 0 0 4/16 4/16 4/16 4/16 8/16 8/16 8/16 8/16 12/16 12/16 12/16 12/16
0 1/16 2/16 3/16 0 1/16 2/16 3/16 0 1/16 2/16 3/16 0 1/16 2/16 3/16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1111 1110 1101
Ideal Finite Characteristic
1100 1011
Digital Output Code
VREF
b1 b2 Vout(1) Vin(2) VREF VREF
Vin(1)
1010 INL=0LSB
1001
-DNL=0LSB
1000 0111 0110
-INL=2LSB
0101 0100 0011 +DNL=2LSB
0010 0001 0000 0 16
1 16
2 16
3 16
4 16
5 16
6 7 8 9 10 16 16 16 16 16 Analog Input Voltage
11 16
12 13 14 15 16 16 16 16 16 16
Comparing the actual digital output word with the ideal output word gives the following results: +INL = 0LSB, -INL = 0111-0101 = -2LSB, +DNL = (1000-0101) - 1LSB = +2LSB, and -DNL = (0101-0100) - 1LSB = 0LSB.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-25
CMOS Analog IC Design
EXAMPLE 10.8-4 Accuracy requirements for the amplifier of a 2-stage, 2-bits/stage pipeline ADC A 4-bit ADC consisting of two, 2-bit stages (pipes) is shown. Assume that the 2-bit ADC’s and the 2-bit DAC function ideally. Also, assume VREF VREF VREF that VREF = 1V. The ideal value of the scaling factor, k, is 4. Find the vin(2) maximum and minimum value of k + 2-bit 2-bit 2-bit that will not cause an error in the 4vin(1) k - Σ DAC ADC ADC bit ADC. Express the tolerance of k vout(1) in terms of a plus and minus percentage. Fig.10.8-18 b 1 b2 b3 b4 Solution b1 b 2 The input to the second ADC is vin(2) = k vin(1) - 2 + 4 . Designating this voltage as v’in(2) when k = 4, then the difference between vin(2) and v’in(2) must be less than ±1/8 or the LSB bits will be in error. b1 b 2 b1 b 2 1 Therefore, vin(2) - v’in(2) = k vin(1) - k 2 + 4 - 4 vin(1) + 4 2 + 4 ≤ 8 b1 b 2 b1 b 2 b1 b 2 1 If k = 4 + ∆k, then 4 vin(1) + ∆k vin(1) - 4 2 + 4 - ∆k 2 + 4 - 4 vin(1) + 4 2 + 4 ≤ 8 b1 b 2 1 or ∆kvin(1) - 2 + 4 ≤ 8 . b1 b 2 The largest value of vin(1) - 2 + 4 is 1/4 for any value of vin(1) from 0 to VREF. ∆k 1 ∆k ±1 ±1 Therefore, 4 ≤ 8 ⇒ ∆k ≤ 1/2. The tolerance of k is k = 2·4 = 8 ⇒ ±12.5%
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-26
CMOS Analog IC Design
EXAMPLE OF A MULTIPLE-BIT, PIPELINE ADC Two-stages with 5-bits per stage resulting in a 10-bit ADC with a sampling rate of 5Msamples/second. Architecture: Vin S/H
Vin*
MSB ADC
MSBs Increment by 1
DAC Vr1 LSB ADC Fig.10.8-21
LSBs
Vr2 DAC
Features: • • • •
Requires only 2n/2-1 comparators LSBs decoded using 31 preset charge redistribution capacitor arrays Reference voltages used in the LSBs are generated by the MSB ADC No op amps are used
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-27
CMOS Analog IC Design
EXAMPLE OF A MULTIPLE-BIT, PIPELINE ADC - CONTINUED MSB Conversion: DAC
VREF R32 R31
R30
Vr2
Vr1
Analog MUX
Vin* + Vin*
Vin*
VRi Ri
Vin*
32C Vin* + 32C
+ +
Vin* + -
-
32C
+
Latch Bank and Binary Encoder
MSB Output
VRi-Vin* R2 R1 MSBs
Vin*
Vin* + -
-
32C
+ Fig.10.8-22
Operation: 1.) Sample Vin* on each 32C capacitance autozeroing the comparators 2.) Connect each comparator to a node of the resistor string generating a thermometer code.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-28
CMOS Analog IC Design
EXAMPLE OF A MULTIPLE-BIT, PIPELINE ADC - CONTINUED LSB Conversion: Operation: 1.) MSB comparators are preset to each of the Vr2 31 possible digital codes. ADC set to Code 11111 Vin* 2.) Vr1 and Vr2 are derived from the MSB Vr1 conversion. Vr2 3.) Preset comparators will produce a thermometer code to the encoder. ADC set to Code 11110 Vin* Latch Bank and Binary Encoder
Vr1 Vr2 Vin*
ADC set to Code 00010
LSB Output Comments:
• Requires two full clock cycles • Reuses the comparators • Accuracy limited by resistor string and its dynamic loading • Accuracy also limited by the capacitor array • Comparator is a 3-stage, low-gain, widebandwidth, using internal autozeroing
Vr1 Vr2 Vin*
ADC set to Code 00001 Vr1 -
C 16C 8C
4C
2C
C
+
Switches set to "Code"
Vr2 Vr1
Fig.10.8-23
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-29
CMOS Analog IC Design
DIGITAL ERROR CORRECTION The multiple-bit, pipeline ADC architecture permits the correction of digital errors that occur in the previous stage. The problem (Comparator in 1st stage has an error): The solution (use an additional bit for correction): Stage 1 Stage 2
Stage 1
VREF 11 0.75VREF 10 0.50VREF Vin* = 0.4VREF
11 0.75VREF
11 10 01 00 Error
10 0.50VREF Vin* = 0.4VREF
01
0.25VREF
01
111 110 101 100 011 010 001 000
101 100 11 10 01 00 -01 -10
0.25VREF 00
0
Stage 2
VREF
Clock 1 Clock 2 00 Digital output word = 10
00
Time
0
Time Clock 1 Clock 2 10 Digital output word = 01 Fig.10.8-19
For an input of 0.4VREF the output should be 0110. Comments: • The idea is to add a correcting bit to the following stage to correct for errors in the previous stage. • The subranging or amplification of the next stage does not include the correcting bit. • Correction can be done after all stages of the pipeline ADC have converted or after each individual stage.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-30
CMOS Analog IC Design
EXAMPLE OF A PIPELINE ADC WITH DIGITAL ERROR CORRECTION ADC uses 4 stages of 4-bits each and employs a successive approximation ADC to get 13-bit resolution at 250 ksamples/sec. Block diagram of a 13-bit pipeline ADC: Vin
2N1
+
S/H
S/H -
ADC-N2 bit
2N3
+
S/H
-
-
DAC-N1 bit
ADC-N1 bit
2N2
+
DAC-N2 bit
ADC-N3 bit
DAC-N3 bit
VREF 3 bits N3 bit REG
3 bits
N2 bit REG
N2 bit REG
3 bits
N1 bit REG
N1 bit REG
4 bits
S/H
N1 bit REG
0.5 LSB offset
0.5 LSB offset
Comments: • The ADC of the first stage uses 16 equal capacitors instead of 4 binary weighted for more accuracy • One bit of the last three stages is used for error correction.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-31
CMOS Analog IC Design
12-BIT PIPELINE ADC WITH DIGITAL ERROR CORRECTION & SELF-CALIBRATION† vin
S/H
DAC
ADC
DAC
ADC 3 bits
DAC
ADC
ADC
ADC 3 bits
DAC
3 bits
3 bits
4 bits
Clock 12 bits Digital Error Correction Logic Fig. 11-30
Digital Error Correction: • Avoids saturation of the next stage • Reduces the number of missing codes • Relaxed specifications for the comparators • Compensates for wrong decisions in the coarse quantizers Self-Calibration: • Can calibrate the effects of the DAC nonlinearity and gain error • Can be done by digital or analog methods or both †
J. Goes, et. al., CICC’96
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-32
CMOS Analog IC Design
TIME-INTERLEAVED ANALOG-DIGITAL CONVERTERS Slower ADCs are used in parallel. Illustration: T1 S/H
N-bit ADC No. 1
T2 S/H
N-bit ADC No. 2
Digital word out
Vin TM S/H
N-bit ADC No. M
N-bit ADC No. 1 N-bit ADC No. 2 TC T= M N-bit ADC No. M T1
T2
TM
T1+TC T2+TC
TM+TC
t Fig.10.8-20
Comments: • Can get the same throughput with less chip area • If M = N, then a digital word is converted at every clock cycle • Multiplexer and timing become challenges at high speeds
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.8-33
CMOS Analog IC Design
SUMMARY OF REPORTED HIGH-SPEED ADCs Recently published high-speed, CMOS ADCs. Architecture [paper reference]
Sampling Freq. (Msps)
Signal Freq. (MHz)
ENOB1 (bits)
Feature Power Active Area 2 (mW) (mm ) Size2 (µm)
Vin (Vp-p) VDD (V)
Folding+ Interpolating [1]
70
8
5.5
110
0.7
0.8
2.0
Flash [2]
200
100
5.0
400
2.7
0.6
-
5.0 -
Flash [3]
200
20
6.0
110
1.6
0.5
0.3
3.0
Flash w. pre-processing [4]
175
84
4.0
160
12.0
0.7
1.2
3.3
Folding+ Interpolating [5]
125
10
5.5
225
4.0
1.0
-
5.0
Folding+ Interpolating [6]
80
75
5.8
80
0.3
0.5
1.6
3.3
Subranging+Interleaving [7]
95
50
8.0
1100
50.0
1.0
2.0
5.0
References for Recently Published High-Speed CMOS ADCs [1] B. Nauta and A. Venes, “A 70Ms/s 110mW 8-b CMOS Folding and Interpolating A/D Converter, IEEE J. of Solid-State Circuits, vol. 30, no. 12, Dec. 1995, pp. 1302-1308. [2] J. Spalding and D. Dalton, “A 200 Msample/s 6b Flash ADC in 0.6µm CMOS,” Proc. of ISSCC, paper SA19.5, 1996. [3] S. Tsukamoto, I. Dedic, et. al., “A CMOS 6b 200Msamples/s 3V-supply A/D converter for a PRML Read Channel LSI,” Proc. of ISSCC, paper TP4.5, 1996. [4] R. Roovers and M. Steyaert, “A 175Ms/s, 6-b, 160mW, 3.3V CMOS A/D Converter,” IEEE J. of Solid-State Circuits, vol. 31, no. 7, July 1996, pp. 938-944. [5] M. Flynn and D. Allstot, “CMOS Folding A/D Converters with Current-Mode Interpolation,” IEEE J. of Solid-State Circuits, vol. 31, no. 9, Sept. 1996, pp. 1248-1257. [6] A. Venes and R. van de Plassche, “An 80 MHz, 80mW, 8-b CMOS Folding A/D Converter with Distributed Track-and-Hold Preprocessing,” IEEE J. of Solid-State Circuits, vol. 31, no. 12, Dec. 1996, pp. 1846-1853. [7] K. Kim, N. Kusayanagi, and A. Abidi, “A 10-b, 100-Ms/s CMOS A/D Converter,” IEEE J. of Solid-State Circuits, vol. 32, no. 3, Mar. 1997, pp. 302-311.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.8-34
CMOS Analog IC Design
SUMMARY OF HIGH-SPEED ANALOG-DIGITAL CONVERTERS Type of ADC
Primary Advantage
Primary Disadvantage
Flash or parallel Interpolating
Fast Fast
Area is large if N > 6 Requires accurate interpolation
Folding Multiple-Bit, Pipeline Time-interleaved
Fast Increased number of bits Small area with large throughput
Bandwidth increases if no S/H used Slower than flash Precise timing and fast multiplexer
Typical Performance: • 6-8 bits • 200-500 Msamples/sec. • The ENOB at the Nyquist frequency is typically 1-2 bits less that the ENOB at low frequencies. • Power is approximately 0.3 to 1W
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design - Chapter 10
© P.E. Allen, 2001 Page 10.9-1
10.9 - OVERSAMPLING CONVERTERS INTRODUCTION What is an oversampling converter? An oversampling converter uses a noise-shaping modulator to reduce the in-band quantization noise to achieve a high degree of resolution. What is the possible performance of an oversampled converter? The performance can range from 16 to 18 bits of resolution at bandwidths up to 50kHz to 8 to 10 bits of resolution at bandwidths up to 5-10MHz. What is the range of oversampling? The oversampling ratio, called M, is a ratio of the clock frequency to the Nyquist frequency of the input signal. This oversampling ratio can vary from 8 to 256. • The resolution of the oversampled converter is proportional to the oversampled ratio. • The bandwidth of the signal to be converted is inversely proportional to the oversampled ratio. What are the advantages of oversampling converters? Very compatible with VLSI technology because most of the converter is digital High resolution Single-bit quantizers use a one-bit DAC which has no INL or DNL errors Provide an excellent means of trading precision for speed What are the disadvantages of oversampling converters? Difficult to model and simulate Limited in bandwidth to the clock frequency divided by the oversampling ratio
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.9-2
CMOS Analog IC Design - Chapter 10
NYQUIST VERSUS OVERSAMPLED ADCs Conventional Nyquist ADC Block Diagram:
x(t)
Digital Processor Filtering
Sampling
Quantization
y(kTN)
Digital Coding Fig.10.9-01
Oversampled ADC Block Diagram:
x(t)
Filtering
Sampling
Modulator
Decimation Filter
Quantization
Digital Coding
y(kTN)
Fig.10.9-02
Components: • Filter - Prevents possible aliasing of the following sampling step. • Sampling - Necessary for any analog-to-digital conversion. • Quantization - Decides the nearest analog voltage to the sampled voltage (determines the resolution). • Digital Coding - Converts the quantizer information into a digital signal.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.9-3
CMOS Analog IC Design - Chapter 10
FREQUENCY SPECTRUM OF NYQUIST AND OVERSAMPLED CONVERTERS Definitions: fB = analog signal bandwidth fN = Nyquist frequency (two times fB) fS = sampling or clock frequency fS fS M = f = 2f = oversampling ratio N B Frequency spectrums: Conventional ADC with fB≈ 0.5fN=0.5fS. Transition band
Amplitude
;;; ;;; ; ;
0
Signal Bandwidth
Anti-aliasing filter
fB 0.5fN = 0.5fS
0
fS =fN
f
fS =MfN
f
Amplitude
Oversampled ADC with fB≈ 0.5fN1. Therefore, the in-band, rms noise is given as n0 =
πL 1 ∆ πL 1 L+0.5 e = 2L+1 M 12 2L+1 M L+0.5 rms
SB =
Comment: Note that as the ∆Σ is a much more efficient way of achieving resolution by increasing M. erms ⇒ Doubling of M leads to a 2L+0.5 decrease in in-band noise n0 ∝ M L+0.5 which leads to an extra L+0.5 bits of resolution! ∴ The reduction of the oversampling ratio is an excellent method of increasing the resolution of a ∆Σ oversampling analog-digital converter.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.9-13
CMOS Analog IC Design - Chapter 10
ILLUSTRATION OF RMS NOISE VERSUS OVERSAMPLING RATIO FOR SINGLE LOOP ∆ Σ MODULATORS Plotting n0/erms gives, n0 πL 1 erms = 2L+1M L+0.5
0 L=0 -20 L=1 -40 n0 erms (dB) -60
L=2 L=3 L=4
-80 -100
1
2
Chapter 10 - DA and AD Converters (6/4/01)
4
8 16 32 64 128 512 1024 Oversampling Ratio, M Fig.10.9-15
© P.E. Allen, 2001
Page 10.9-14
CMOS Analog IC Design - Chapter 10
DYNAMIC RANGE OF ∆Σ ANALOG-DIGITAL CONVERTERS Oversampled ∆Σ Converter: The dynamic range, DR, for a single bit-quantizer with level spacing ∆ =VREF, can be found as
DR2 =
∆ 2 2 2
Maximum signal power 3 2L+1 2L+1 = = SB(f) π2L 1 ∆2 2 π2L M 2L+1 M2L+1 12
Nyquist Converter: The dynamic range of a N-bit Nyquist rate ADC is given as (now ∆ becomes ≈VREF for large N), DR 2 =
2 Maximum signal power (VREF/2 2) 3 = = 2 22N SQ ∆2/12
→
DR = 1.5 2N
Expressing DR in terms of dB (DRdB) and solving for N, gives DRdB - 1.7609 or DRdB = (6.0206N + 1.7609) dB 6.0206 For Example: A 16-bit ∆Σ ADC requires about 98dB of dynamic range. For a second-order modulator, this implies that M is 153 or 256 since we must use powers of 2. If the bandwidth is 20kHz, then the clock frequency must be 10.24MHz. N=
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.9-15
CMOS Analog IC Design - Chapter 10
MULTIBIT QUANTIZERS A single-bit quantizer: ∆ = VREF
v
+
y
-
Advantage is that the DAC is linear.
v0 VREF 2
Fig. 10.9-13
Multi-bit quantizer: Consists of an ADC and DAC of B-bits. VREF ∆ = 2B-1 Disadvantage is that the DAC is no longer perfectly linear.
fS v
u VREF
∆
VREF 2
A/D
y
D/A Quantizer Fig. 10.9-14
Fig. 10.9-135
Dynamic range of a multibit ∆Σ ADC: 3 2L+1 DR2 = 2 π2L M2L+1 ( 2B-1) 2
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.9-16
CMOS Analog IC Design - Chapter 10
EXAMPLE 1 - TRADEOFF BETWEEN SIGNAL BANDWIDTH AND ACCURACY OF ∆ Σ ADCs Find the minimum oversampling ratio, M, for a 16-bit oversampled ADC which uses (a.) a 1-bit quantizer and third-order loop, (b.) a 2-bit quantizer and third-order loop, and (c.) a 3-bit quantizer and second-order loop. For each case, find the bandwidth of the ADC if the clock frequency is 10MHz. Solution We see that 16-bit ADC corresponds to a dynamic range of approximately 98dB. (a.) Solving for M gives 2 DR2 π2L 1/(2L+1) ˚ M= ˚ 3 2L+1 (2B-1)2
Converting the dynamic range to 79,433 and substituting into the above equation gives a minimum oversampling ratio of M = 48.03 which would correspond to an oversampling rate of 64. Using the definition of M as fc/2fB gives fB as 10MHz/2·64 = 78kHz. (b.) and (c.) For part (b.) and (c.) we obtain a minimum oversampling rates of M = 32.53 and 96.48, respectively. These values correspond to oversampling rates of 32 and 128, respectively. The bandwidth of the converters is 312kHz for (b.) and 78kHz for (c.).
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.9-17
CMOS Analog IC Design - Chapter 10
Z-DOMAIN EQUIVALENT CIRCUITS The modulator structures are much easier to analyze and interpret in the z-domain. q[nTs] Integrator Delay
w[nTs] +
x[nTs] + -
y[nTs]
v[nTs] +
+
Quantizer Q(z)
X(z) +
Integrator z-1
W(z) + -
V(z)
+
Y(z)
+
Quantizer Q(z)
X(z) +
z-1 1-z-1
-
Y(z)
+
Fig.10.9-16
z-1 Y(z) = Q(z) + 1-z-1 [X(z) - Y(z)]
→
Y(z)
Y(z) = (1-z-1)Q(z) + z-1X(z)
→
NTFQ (z) = (1-z-1) for L = 1
∴
Chapter 10 - DA and AD Converters (6/4/01)
z-1 1 = Q(z) + -1 X(z) -1 1-z 1-z
© P.E. Allen, 2001
Page 10.9-18
CMOS Analog IC Design - Chapter 10
ALTERNATIVE MODULATOR ARCHITECTURES Since the single-loop architecture with order higher than 2 are unstable, it is necessary to find alternative architectures that allow stable higher order modulators. Cascaded ∆Σ Modulator - Second-Order Q2(z) X2(z) +
+
z-1 1-z-1
-
Y2(z)
Q1(z) X(z) +
z-1 1-z-1
-
+
Y1(z)
z-1 +
-
z-1 +
+
Y(z)
Fig.10.9-17
Y1(z) = (1-z-1)Q1(z) + z-1X(z) z-1 z-1 z-1 X2(z) = 1-z-1 (X(z) -Y1(z) = 1-z-1 X(z) - 1-z-1 [(1-z-1)Q1(z) + z-1X(z)]
z-2 z-2 Y2(z) = (1-z-1)Q2(z) + z-1X2(z) = (1-z-1)Q2(z) + 1-z-1 X(z) - z-2Q1(z) - 1-z-1 X(z)
= (1-z-1)Q2(z) - z-2Q1(z) Y(z) =Y2(z) - z-1Y2(z) + z-2Y1(z) = (1-z-1)Y2(z) + z-2Y1(z) = (1-z-1)2Q2(z) - (1-z-1)z-2Q1(z) + (1-z-1)z-2Q1(z) + z-3X(z) = (1-z-1)2Q2(z) + z-3X(z) ∴ Y(z) = (1-z-1)2Q2(z) + z-3X(z)
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.9-19
CMOS Analog IC Design - Chapter 10
ALTERNATIVE MODULATOR ARCHITECTURES - CONTINUED MASH Architecture - Third Order X(z) +
-
1 1-z-1
Q1(z) + +
+ +
Y1(z)
Y(z)
z-1 -Q1(z) + -
+ Q2(z) + + 1 1-z-1 z-1
-Q2(z) + -
+ Q3(z) + + 1 1-z-1 z-1
1-z-1 Y2(z)
+ + 1-z-1
1-z-1 Y3(z)
Fig. 10.9-17A
It can be shown that Y(z) = X(z) + (1-z-1)3Q3(z) Comments: • The above structures that eliminate the noise of all quantizers except the last are called MASH or multistage architectures. • Digital error cancellation logic is used to remove the quantization noise of all stages, except that of the last one.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.9-20
CMOS Analog IC Design - Chapter 10
ALTERNATIVE MODULATOR ARCHITECTURES - CONTINUED Distributed Feedback ∆Σ Modulator - Fourth-Order Q a1z-1 Y1 1-z-1
X + -
a2z-1 Y2 1-z-1 +
a3z-1 Y3 1-z-1
+
+
+
a4z-1 Y4 + 1-z-1
1-bit A/D
+
1-bit D/A
Y
Fig.10.9-20
amplitude of integrator output / VREF
Amplitude of integrator outputs: fourth order distributed feedback modulator a1=0.1, a2=0.1, a3=0.4, a4=0.4 1.50 y1 y2
1.25
y3 y4
1.00 0.75 0.50 0.25 0.00 -1.00
-0.60 -0.20 0.20 0.60 input signal amplitude / VREF
1.00
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.9-21
CMOS Analog IC Design - Chapter 10
ALTERNATIVE MODULATOR ARCHITECTURES - CONTINUED Distributed Feedback ∆Σ Modulator - Fourth-Order Q a1z-1 Y1 a2z-1 Y2 a3z-1 Y3 a4z-1 Y4 + 1-z-1 1-z-1 1-z-1 1-z-1 + + + + +
X + -
1-bit A/D
1-bit A/D
Y
Fig.10.9-20
Amplitude of integrator outputs: fourth order feedforward modulator a1=0.5, a2=0.4, a3=0.1, a4=0.1
amplitude of integrator outputs
1.50
y1 y2
1.25
y3 y4
1.00 0.75 0.50 0.25 0.00 -1.00
-0.60 -0.20 0.20 0.60 input signal amplitude / VREF
Chapter 10 - DA and AD Converters (6/4/01)
1.00
© P.E. Allen, 2001
Page 10.9-22
CMOS Analog IC Design - Chapter 10
X +
a1z-1 + 1-z-1
-
-
+
α
+
q2 + +
a3z-1 1-z-1
+
β
q1 +
a2z-1 1-z-1
Fig.10.9-21
Digital error cancellation circuit
ALTERNATIVE MODULATOR ARCHITECTURES - CONTINUED Cascaded of a Second-Order Modulator with a First-Order Modulator
Y
Comments: • The stability is guaranteed for cascaded structures • The maximum input range is almost equal to the reference voltage level for the cascaded structures • All structures are sensitive to the circuit imperfection of the first stages • The output of cascaded structures is multibit requiring a more complex digital decimator
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.9-23
CMOS Analog IC Design - Chapter 10
INTEGRATOR CIRCUITS FOR ∆Σ MODULATORS Fundamental block of the ∆Σ modulator: Vi(z)
a
+
Vo(z)
z-1
Vi(z)
+
az-1 1-z-1
Vo(z) Fig.10.9-22
Fully-Differential, Switched Capacitor Implementation:
φ2 + vin -
φ1
Cs
φ1 φ1
φ2 φ2Cs
φ1
φ2
Ci + - +
+ vout -
Ci Fig.10.9-23
It can be shown (Chapter 9) that, Vout(z) Cs z-1 Vin(z) = Ci 1-z-1 o V out(e jωΤ ) o Vin( e jωΤ )
o
⇒
V out(e jωΤ )
e-jωΤ/2 ω T C1 C1 = o C2 j2 sin(ωT/2) ω T = jω TC2 V ( e jωΤ ) in
ω T/2 -jωΤ/2 e ) sin(ωT/2) (
ωI C = (Ideal)x(Magnitude error)x(Phase error) where ωI = TC1 ⇒ Ideal = j ω
Chapter 10 - DA and AD Converters (6/4/01)
2
© P.E. Allen, 2001
Page 10.9-24
CMOS Analog IC Design - Chapter 10
POWER DISSIPATION VS. SUPPLY VOLTAGE AND OVERSAMPLING RATIO The following is based on the above switched-capacitor integrator: 1.) Dynamic range: The noise in the band [-fs,fs] is kT/C while the noise in the band [-fs/2M,fs/2M] is kT/MC. We must multiply this noise by 4; x2 for the sampling and integrating phases and x2 for differential operation. VDD2 2 V DDMCs 2 ∴ DR = 4kT = 8kT MCs 2.) Lower bound on the sampling capacitor, Cs: Cs =
8kT·DR 2
VDDM 3.) Static power dissipation of the integrator: Pint = IbVDD 4.) Settling time for a step input of Vo,max: Vo,max Ci Ib = C i T = T settle settle ∴
Cs CsVDD C VDD = T = CsVDD(2fs) = 2MfNCsVDD settle i
Pint = 2MfNCsVDD2 = 16kT·DR·fN
Because of additional feedback signal to the first integrator, the maximum voltage can be as large as 2VDD. P1st-int = 32kT·DR·fN Note that the power dissipation is a strong function of the dynamic range or number of bits.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.9-25
CMOS Analog IC Design - Chapter 10
IMPLEMENTATION OF ∆Σ MODULATORS Most of today’s delta-sigma modulators use fully differential switched capacitor implementations. Advantages are: • Doubles the signal swing and increases the dynamic range by 3dB • Common-mode signals that may couple to the signal through the supply lines and substrate are canceled • Charge injected by the switches are canceled to a first-order Example: X +
0.5z-1 1 - z-1
-
VRef+
VRef-
Y
YB
φ1 C
φ1d φ1d
C
YB VRef
φ2 φ2
-
-
VRef
0.5z-1 1 - z-1
-
VRef+
VRef-
Y
YB
+
YB 2C
VRef
C
+
Q1 Y
2C φ2 φ2
φ1
-
Y
+
YB
φ1
Y +
+
φ1 C
φ1d φ1d
φ1
Y +
2C
+
VRef
-
2C
Fig.10.9-24
First integrator dissipates the most power and requires the most accuracy.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.9-26
CMOS Analog IC Design - Chapter 10
EXAMPLE - 1.5V, 1mW, 98dB ∆Σ ANALOG-DIGITAL CONVERTER† α X
Σ
a1 z - 1 y1
a2 z - 1 y2
b1
Σ
a3 z - 1 y3 Σ
E
a4 1-bit z - 1 y4 A/D
Y
b2 Σ 1-bit D/A
(6-1)
where a1 = 1/3, a2 = 3/25, a3 = 1/10, a4 = 1/10, b1= 6/5, b2= 1 and α = 1/6 Advantages: • The modulator combines the advantages of both DFB and DFF type modulators: Only four op amps are required. The first integrator’s output swing is confined between ±VREF for large input signal amplitudes (0.6VREF), even if the integrator gain is large (0.5). • A local resonator is formed by the feedback around the last two integrators to further suppress the quantization noise. • The modulator is fully pipelined for fast settling.
† A.L. Coban and P.E. Allen, “A 1.5V, 1mW Audio ∆Σ Modulator with 98dB Dynamic Range, “Proc. of 1999 Int. Solid-State Circuits Conf., Feb. 1999, pp. 50-51.
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design - Chapter 10
© P.E. Allen, 2001 Page 10.9-27
1.5V, 1mW, 98dB ∆Σ ANALOG-DIGITAL CONVERTER - CONTINUED Integrator power dissipation vs. integrator gain
DR = 98 dB BW = 20 kHz Cs = 5 pF 0.5 µm CMOS
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.9-28
CMOS Analog IC Design - Chapter 10
1.5V, 1mW, 98dB ∆Σ ANALOG-DIGITAL CONVERTER - CONTINUED Modulator power dissipation vs. oversampling ratio
OSR = 64
OSR = 32 OSR = 16 OSR = 8
Suppy Voltage (V) DR = 98 dB BW = 20 kHz Integrator gain = 1/3 0.5µm CMOS
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.9-29
CMOS Analog IC Design - Chapter 10
1.5V, 1mW, 98dB ∆Σ ANALOG-DIGITAL CONVERTER - CONTINUED Circuit Implementation
Capacitor Cs
Capacitor Values Integrator 1 Integrator 2 Integrator 3 5.00pF
0.15pF
0.30pF
Integrator 4 0.10pF
1 1d 2
Ci
15.00pF
1.25pF
3.00pF
1.00pF
Ca
-
-
0.05pF
-
Cb1
-
-
-
0.12pF
Cb2
-
-
-
0.10pF
Chapter 10 - DA and AD Converters (6/4/01)
2d Fig.10.9-25
© P.E. Allen, 2001
CMOS Analog IC Design - Chapter 10
Page 10.9-30
1.5V, 1mW, 98dB ∆Σ ANALOG-DIGITAL CONVERTER - CONTINUED Microphotograph of the experimental ∆Σ modulator.
Chapter 10 - DA and AD Converters (6/4/01) CMOS Analog IC Design - Chapter 10
© P.E. Allen, 2001 Page 10.9-31
1.5V, 1mW, 98dB ∆Σ ANALOG-DIGITAL CONVERTER - CONTINUED Measured SNR and SNDR versus input level of the modulator.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.9-32
CMOS Analog IC Design - Chapter 10
1.5V, 1mW, 98dB ∆Σ ANALOG-DIGITAL CONVERTER - CONTINUED Measured baseband spectrum for a -7.5dBr 1kHz input.
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.9-33
CMOS Analog IC Design - Chapter 10
1.5V, 1mW, 98dB ∆Σ ANALOG-DIGITAL CONVERTER - CONTINUED Measured baseband spectrum for a -80dBr 1kHz input.
-80 dBr, 1 kHz signal VREF = 1.5 V (diff.) 2048-point FFT
frequency, (kHz)
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001
Page 10.9-34
CMOS Analog IC Design - Chapter 10
1.5V, 1mW, 98dB ∆Σ ANALOG-DIGITAL CONVERTER - CONTINUED Measured 4th-Order ∆Σ Modulator Characteristics: Table 5.4 Measured fourth-order delta-sigma modulator characteristics Technology : 0.5 µm triple-metal single-poly n-well CMOS process
Supply voltage Die area Supply current analog part digital part
Reference voltage Clock frequency Oversampling ratio Signal bandwidth Peak SNR Peak SNDR Peak S/D HD 3 @ -5dBv 2kHz input DR
1.5 V 1.02 mm x 0.52 mm 660 µA 630 µA 30 µA 0.75V 2.8224MHz 64 20kHz 89 dB 87 dB 101dB -105dBv 98 dB
Chapter 10 - DA and AD Converters (6/4/01)
© P.E. Allen, 2001 Page 10.9-35
CMOS Analog IC Design - Chapter 10
DECIMATION AND FILTERING fS
Analog f B Input x(t)
∆Σ Modulator (Analog)
fD
