CMOS Analog and Radio-Frequency Integrated-Circuit Design Employing Low-Power Switched-Capacitor Techniques

by

Yu Song

Submitted in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy

Supervised by Professor Zeljko Ignjatovic Department of Electrical and Computer Engineering Arts, Sciences and Engineering Edmund A. Hajim School of Engineering and Applied Sciences

University of Rochester Rochester, New York

2011

ii

Curriculum Vitae

The author was born in Hebei Province, China in 1980. He attended Nankai University (Tianjin, China) from 1999 to 2006, and graduated with a Bachelor of Science degree in Electronics in 2003 and a Master of Science degree in Optics in 2006. He came to the University of Rochester in the fall of 2006 and begun graduate studies in the Department of Electrical and Computer Engineering with a concentration in analog/radio-frequency integrated circuit design. He pursued his research under the direction of Professor Zeljko Ignjatovic and received the Master of Science degree from the University of Rochester in 2008.

iii

Acknowledgements My graduate studies at the University of Rochester have been full of opportunities to learn from a large body of faculty members and students with extensive and profound knowledge. I would like to thank my advisor, Prof. Zeljko Ignjatovic, for investing considerable time, effort and resources in my graduate studies. He provided me invaluable guidance throughout the years and it is a privilege to be in his group. I, also, want to thank the members of my thesis committee for providing me insightful advice and feedback. Besides, I am grateful for the assistance received from members of Prof. Ignjatovic's group, Prof. Mark Bocko's group and Prof. Hui Wu's group, regarding computer environment setup, circuit design discussion, testing assistance, and so on. Thanks to the MOSIS Educational Program for the Sigma-Delta modulator project fabrication in the IBM 130nm CMOS process.

iv

Abstract We propose and verify the design of low-power, high-performance CMOS Switched-Capacitor (SC) circuits for analog and radio-frequency (RF) applications. In low-cost CMOS semiconductor processes, SC circuits play a crucial role in implementing accurate analog signal processing functions. However, conventional SC circuits are usually power-demanding due to the accurate signal settling requirement. On the other hand, the shrinking of amplifier gain and voltage swing driven by technology scaling makes SC circuit design in deep sub-micron CMOS processes more and more challenging. To counteract these problems, low-power SC circuit techniques suitable for deep sub-micron CMOS processes are investigated in this work. In the first illustrative circuit example, a 2.5 GHz Phase-Locked-Loop (PLL) employing a new low-power SC loop filter is proposed, designed and verified in a 0.18μm CMOS technology. By employing the proposed SC loop filter, the advantages of low reference spur and small on-chip capacitor size are achieved. While the loop filter consumes a very low power, 1/f noise introduced by the inverter amplifier is also suppressed. The second circuit example is an audio-band highly-linear low-power multi-bit Delta-Sigma (ΔΣ) modulator with a SC nonlinearity-suppressed feedback DAC verified in a 0.13μm CMOS technology. By employing this proposed scheme, problems with conventional methods to realize multi-bit feedback DACs are circumvented. The power consumption of the proposed method can be maintained low. A promising approach to implement practical multi-bit ΔΣ analog-to-digital converters (ADCs) is demonstrated.

v

Table of Contents Curriculum Viate

ii

Acknowledgements

iii

Abstract

iv

List of Tables

ix

List of Figures

x

List of Acronyms

xvii

Foreword Chapter 1

1 Introduction

2

1.1 Motivation

2

1.2 Research Goals

3

1.3 Thesis Organization

6

Chapter 2

Switched-Capacitor Circuits

8

2.1 Discrete-Time Signal Basics

8

2.1.1

Spectra of Discrete-Time Signals

8

2.1.2

Sample-and-Hold Response

10

2.2 Building Blocks in Switched-Capacitor Circuits

11

2.2.1

Sampling Switches

11

2.2.2

Capacitors

16

2.2.3

Amplifiers

19

2.3 Noise in Switched-Capacitor Circuits 2.3.1

KTC noise

25 25

vi

2.3.2 Chapter 3

Thermal noise of a switched-capacitor integrator

PLL Frequency Synthesizer

3.1 PLL basics

3.2

3.3

Chapter 4

26 31 31

3.1.1

Type I PLL

32

3.1.2

Type II PLL

35

PLL Building Blocks

44

3.2.1

Phase/frequency detector

44

3.2.2

Charge Pump

47

3.2.3

Programmable Divider

48

3.2.4

Voltage Controlled Oscillator

49

Implementation Issues and Noise

52

3.3.1

Implementation Issues

52

3.3.2

Noise Consideration at Different Nodes

55

Delta-Sigma A/D Converters

4.1 A/D Conversion Basics

58 58

4.1.1

Sampling and Quantization

58

4.1.2

Oversampling ADC

61

4.2 Basics of Delta-Sigma ADCs

62

4.3 Higher-Order Delta-Sigma ADCs

67

4.3.1

4.3.2

Single-Loop ΔΣ modulators with Distributed Feedback Paths

69

Single-Loop ΔΣ modulators with Feed-Forward Paths

72

vii

4.3.3

Stability of single loop ΔΣ modulators

75

4.3.4

MASH modulators

81

4.3.5

Techniques to enhance ΔΣ modulator performance

83

4.4 Thermal Noise in ΔΣ ADCs Chapter 5

86

PLL Design with a Low-Power Active Switched-Capacitor Loop Filter 91

5.1 PLL Loop Filters in literatures

91

5.1.1

Active Continuous-Time Loop Filter

91

5.1.2

Passive Switched-Capacitor Loop Filter

93

5.1.3

Hybrid Loop Filter

96

5.2 Proposed Low-Power Active Switched-Capacitor Loop Filter 5.2.1

Sub-Threshold Inverter Amplifier

5.2.2

Design of the Low-Power Active Switched-Capacitor

5.2.3

98 98

Loop Filter

101

Reference Spur and Noise of the Loop Filter

109

5.3 Other Building Blocks of the PLL Prototype

112

5.3.1

Phase/Frequency Detector

112

5.3.2

VCO

113

5.3.3

Programmable Divider

117

5.4 Prototype Measurement Results

119

5.5 Chapter Conclusion

121

Chapter 6

A Multi-bit ΔΣ ADC with a Low-Power Switched-Capacitor

viii

Nonlinearity-Suppressed DAC 6.1 Existing Techniques to Enhance DAC Linearity

123 123

6.1.1

Layout considerations for capacitor matching

124

6.1.2

Calibration

126

6.1.3

Dynamic element matching

127

6.2 ΔΣ ADCs with Nonlinearity-Suppressed DACs

129

6.2.1

Switched-capacitor ratio-independent multiply-by-N

129

6.2.2

Low-power SC nonlinearity-suppressed DAC

139

6.2.2.1 Gain-Boosted Inverter Amplifier

139

6.2.2.2 Nonlinearity-suppressed DAC

142

6.2.2.3 Noise analysis for the nonlinearity-suppressed DAC

149

6.2.2.4 ΔΣ ADC using the low-power nonlinearity-suppressed DAC

159

6.3 Chip Measurement Results

160

6.4 Chapter Conclusion

164

Chapter 7 Conclusion

165

References

168

ix

List of Tables Table

Title

Page

Table 3-1

Design parameters for a 2.4GHz PLL

53

Table 3-2

PLL Phase noise transfer function for different noise sources

56

Table 5-1

Karnaugh map for D1

119

Table 5-2

Karnaugh map for D2

119

Table 5-3

PLL performance comparison

122

Table 6-1

ΔΣ Performance summary and comparison

164

x

List of Figures Figure

Title

Page

Figure 2-1

Sampling and Sample-and-Hold

9

Figure 2-2

Frequency domain illustration of sampling

10

Figure 2-3

Sample-and-Hold response

11

Figure 2-4

MOS sample-and-hold stage

12

Figure 2-5

Charge injection and clock feed-through suppression by dummy switch

15

Figure 2-6

Cross section of a MIM capacitor

16

Figure 2-7

A charge redistribution DAC and its equivalent circuit during output phase

17

Figure 2-8

A typical switched-capacitor integrator

20

Figure 2-9

Equivalent circuit of Figure 2-8 in Phase 2

22

Figure 2-10 Block diagram for a basic negative-feedback system

24

Figure 2-11 Bode plots of loop gain for a two-pole system

25

Figure 2-12 Sample-and-hold equivalent circuit during sampling phase

26

Figure 2-13 Input referred integrator thermal noise power versus gm(RS1+RS2)

28

Figure 2-14 Opamp feedback circuit

29

Figure 2-15 Integrator noise model

30

Figure 3-1

Phase-locked loop block diagram

31

Figure 3-2

Magnitude and phase response of the Type I PLL loop gain

33

Figure 3-3

Second order Type II PLL block diagram

36

xi

Figure

Title

Page

Figure 3-4

Magnitude and phase response of the Type II PLL loop gain

37

Figure 3-5

The ratio ω-3dB/ωc versus damping factor

40

Figure 3-6

Time-domain output frequency response of a second-order Type II PLL

40

Figure 3-7

Fourth order Type II PLL block diagram

41

Figure 3-8

Maximum phase margin versus n

42

Figure 3-9

Maximum ωc/ωref versus n

44

Figure 3-10 The inputs and output of an XOR gate

45

Figure 3-11 Implementation of a PFD

46

Figure 3-12 State machine diagram for the PFD

46

Figure 3-13 Principle of charge pump with loop filter

47

Figure 3-14 Clock aligning circuit

48

Figure 3-15 Block diagram of the divider

48

Figure 3-16 Topology of the negative-gm LC oscillator

50

Figure 3-17 Equivalent circuit for the cross-coupled transistors

50

Figure 3-18 Inductor model

51

Figure 3-19 Equivalent circuit of the oscillator

51

Figure 3-20 Mechanism of VCO control voltage ripples

54

Figure 3-21 Magnitude response of a third-order Type II PLL closed-loop transfer function Figure 3-22 Lineralized PLL phase noise model

55 56

xii

Figure

Title

Page

Figure 3-23 PLL noise transfer function response

57

Figure 4-1

Transfer characteristic of quantizers

59

Figure 4-2

Model for a conventional ADC

60

Figure 4-3

Spectral Illustration for a Nyquist rate ADC and an Oversampling ADC

61

Figure 4-4

ΔΣ ADC Block Diagram

63

Figure 4-5

Linearized model of a ΔΣ modulator

64

Figure 4-6

First-order ΔΣ noise shaping

65

Figure 4-7

Second-order ΔΣ modulator block diagram

67

Figure 4-8

Block diagram for an Mth-order ΔΣ modulator with distributed feedback

Figure 4-9

69

Block diagram for a 4th-order ΔΣ modulator with weighted feedback and delay-free integrators

71

Figure 4-10 Block diagram for a Mth-order ΔΣ modulator with weighted feedback and distributed feedforward

72

Figure 4-11: Block diagram for a Mth-order ΔΣ modulator with weighted feed-forward

73

Figure 4-12 Output swing of integrators in feed-forward topology

74

Figure 4-13 Output swing of integrators in feedback topology

74

Figure 4-14 STF magnitude response of a 3rd-order modulator

76

Figure 4-15 NTF magnitude response of a 3rd-order modulator

76

xiii

Figure

Title

Page

Figure 4-16 Block diagram for an Mth-order ΔΣ modulator with weighted feed-forward

77

Figure 4-17 Root-locus of a 3rd-order modulator with a1=1, a2=1, a3=0.5

79

Figure 4-18 Root-locus of a 3rd-order modulator with a1=1, a2=1, a3=1.5

79

Figure 4-19 A two-stage general structure for a MASH modulator

81

Figure 4-20 Noise analysis for an Mth-order ΔΣ modulator with weighted feed-forward

87

Figure 4-21 NTFs at different nodes for a 3rd-order ΔΣ modulator

88

Figure 5-1

Dual-path loop filter 1

93

Figure 5-2

Dual-path loop filter 2

93

Figure 5-3

Passive switched-capacitor loop filter and its timing scheme

94

Figure 5-4

Hybrid loop-filter in [64]

97

Figure 5-5

Hybrid loop-filter in [65]

97

Figure 5-6

Cascode inverter amplifier

99

Figure 5-7

Relationship of DC gain and bandwidth on an inverter's power supply volatge

Figure 5-8

Distribution of the amplifier’s DC gain and offset voltage with the presence of process variations

Figure 5-9

100

101

Proposed switched-capacitor PLL loop filter with complimentary charge pumps

Figure 5-10 Clocks generator circuit and a set of example clocks

102 102

xiv

Figure

Title

Page

Figure 5-11 Phase and gain responses of the sinc and single pole filters

105

Figure 5-12 Magnitude response of the active SC loop filters

106

Figure 5-13 Phase response of the active SC loop filters

107

Figure 5-14 Transient response of VCO control voltages

108

Figure 5-15 PFD schematic

112

Figure 5-16 VCO schematic

113

Figure 5-17 Tuning Characteristics for the nAMOS and pAMOS varactors

115

Figure 5-18 Phase noise model in Eq. (4-35)

116

Figure 5-19 Block diagram of the prescaler

117

Figure 5-20 State machine for the phase select signals

118

Figure 5-21 Circuit implementing the state machine in Figure 4-21

119

Figure 5-22 PLL die photo

120

Figure 5-23 PLL phase noise measurement plot

121

Figure 5-24 PLL output spectrum

122

Figure 6-1

Output power spectral density for a multi-bit ΔΣ Modulator using a conventional DAC with a component mismatch standard deviation of 0.1%

126

Figure 6-2

Element selection algorithm for DWA

128

Figure 6-3

Ratio-independent multiply-by-two circuit

130

Figure 6-4

(a) Linearity deviation for the 3-bit DAC

132

Figure 6-4

(b) Linearity deviation for the 7-level DAC

132

xv

Figure

Title

Figure 6-5

Transfer characteristics for different quantizers

133

Figure 6-6

Sigma-Delta modulator topology

134

Figure 6-7

Quantizer Schematic

135

Figure 6-8

Modulator output power spectral density using the resistor ladder DAC

Figure 6-9

Page

138

Modulator output power spectral density using the resistor ladder DAC

Figure 6-10 Gain-boosted inverter amplifier

138 140

Figure 6-11 Voltage transfer characteristic of the gain-boosted cascode inverter implies a large-gain differential output swing of more than 600mV Figure 6-12 Gain and Voff variation statistics due to process variations

141 142

Figure 6-13 Schematic of the proposed low-power ratio-independent DAC (Analog Part)

143

Figure 6-14 A DAC with one virtual ground Φ1 switch

145

Figure 6-15 Linearity deviation plots

147

Figure 6-16 Block diagram for the logic and clock control circuits

147

Figure 6-17 Schematic of the DAC logic control circuits

148

Figure 6-18 Amplifier schematic and equivalent circuit for noise analysis

150

Figure 6-19 The equivalent circuit for the DAC during the reset phase

151

Figure 6-20 The equivalent circuit for noise of Rra

151

Figure 6-21 The equivalent circuit for noise of Rrb

152

xvi

Figure

Title

Page

Figure 6-22 The equivalent circuit for noise of the inverter amplifier

154

Figure 6-23 The equivalent circuits for DAC charge transfer phase

155

Figure 6-24 The equivalent circuits for DAC charge transfer phase

157

Figure 6-25 The topology of the designed ΔΣ modulator with the ratio-independent DAC

159

Figure 6-26 Die photo for the ΔΣ modulator prototype

161

Figure 6-27 Layout for the ΔΣ modulator prototype

161

Figure 6-28 ΔΣ modulator output spectrum

162

Figure 6-29 SNDR and SNR versus input signal level

163

xvii

List of Acronyms ADC

Analog-to-Digital Converter

CMOS

Complementary Metal Oxide Semiconductor

CP

Charge Pump

DAC

Digital-to-Analog Converter

DEM

Dynamic Element Matching

DNL

Differential Nonlinearity

DR

Dynamic Range

DWA

Data-Weighted Averaging

IC

Integrated Circuit

INL

Integral Nonlinearity

ISF

Impulse Sensitivity Factor

LF

Loop Filter

LSB

Least Significant Bit

MASH

Multi-stage noise shaping

NMOS

N-channel Metal Oxide Semiconductor

OSR

Over-Sampling Ratio

OTA

Operational Transconductance Amplifier

PD

Phase Detector

PFD

Phase/Frequency Detector

PLL

Phase-Locked Loop

PMOS

P-channel Metal Oxide Semiconductor

xviii

PSD

Power Spectral Density

RF

Radio-Frequency

SC

Switched-Capacitor

SFDR

Spurious-Free Dynamic Range

SNDR

Signal-to-Noise and Distortion Ratio

SNR

Signal-to-Noise Ratio

SR

Slew Rate

TSPC

True-Single-Phase-Clock

VCO

Voltage-Controlled Oscillator

XOR

Exclusive OR gate

1

Foreword This thesis covers the author's main research contributions during his PhD studies at the University of Rochester from September 2006 to July 2011, under the supervision of Prof. Zeljko Ignjatovic. The author is the primary contributor to the thesis and performed all the design and experiments. An article coauthored with Prof. Zeljko Ignjatovic related to the contents of Section 5.2 and Section 5.4 of this thesis is accepted for publication in IEEE Transactions of Circuits and Systems II, the issue of September 2011. A manuscript coauthored with Prof. Zeljko Ignajtovic related to Section 6.2.2 and Section 6.3 is being prepared for IEEE Transactions of Circuits and Systems II.

2

Chapter 1 Introduction

1.1

Motivation The development of modern microelectronics has been greatly boosted by

complementary-metal-oxide-semiconductor (CMOS) technology. CMOS offers costand power-efficient high-density circuit integration, and due to its versatility it finds more and more important applications in the fields of mixed-signal (analog/digital) and radio-frequency (RF) integrated-circuit (IC) design [1], [2]. With the aggressive technology scaling during the past decades, CMOS feature size has decreased to tens of nanometers. While technology scaling is beneficial for digital circuits in terms of reduced device size, increased operation speed and less power consumption [3], it imposes several disadvantages on analog and RF circuit designs. One problem is the reduction of the voltage supply, which causes insufficient voltage headroom and/or signal swing in some conventional circuit topologies. Another problem is that along with the shrink of transistor length, amplifier DC gain also decreases. This increases finite gain related errors in circuits. Other factors such as the rise in leakage current and enlarged impacts of process variations also require extra care [4]. To counteract these problems and realize complex high-level integration, it is very important to investigate new circuit techniques suitable for analog and RF design in deep

3

submicron CMOS processes. In CMOS technology, the switched-capacitor (SC) technique is crucial and the most popular way to implement accurate analog signal processing functions. By using the SC technique, circuit parameters (such as gain, zero/pole frequencies) are defined by ratios of capacitors, which can be precisely set in CMOS processes with accuracy on the order of 0.1%. Therefore analog functions such as filtering and data conversion can be implemented more accurately in this way than by other methods which depend on an accurate definition of absolute resistance and capacitance. This work focuses on SC circuits in CMOS analog and RF applications, and several new techniques that offer the potential for significant improvements in both energy efficiency and performance in deep-submicron CMOS technology are presented.

1.2

Research goals The low-power and high performance SC techniques addressed in this work are

embodied in the contexts of two instructive design examples, which are a RF Phase-Locked Loop (PLL) frequency synthesizer prototype implemented in a 180nm CMOS process and a Delta-Sigma (ΔΣ) Data Converter prototype for audio signal processing implemented in a 130nm CMOS process. Techniques related to two major analog circuit functions, which are filtering and data conversion, are investigated and verified in these important application systems. PLL frequency synthesizers are critical components in modern electronic systems, such as wireless transceivers, cable tuners, and high-speed data converters. In communication applications, PLL frequency synthesizers usually serve as local

4

oscillators for the purpose of frequency translation and channel selection. These systems usually impose very stringent requirements on the PLLs' performance, and make their integrated implementation in CMOS technologies a troublesome procedure. First, due to the inferior performance of the components CMOS offers, oscillators with performance meeting specification requirements are difficult to implement compared with those in bipolar or BiCMOS technologies. Second, for a conventional resistor-capacitor (RC) loop filter, a large capacitor is required and if integrated on-chip, it takes enormous space and the effectiveness of CMOS will be reduced dramatically. Another major problem is the reference spurs or periodic jitters caused by the mismatch between the positive and negative charge pump currents. This is an inherent problem at the interface between the charge pump and the conventional loop filter, and this could introduce significant interference to other channels in wireless communication systems. Recently, several PLL frequency synthesizers with switched-capacitor (SC) loop filters have been reported. While some works have shown their effectiveness on the problems mentioned above, some imperfections still exist. In [5]-[6], with the use of passive SC loop filters, small on-chip capacitors and low reference spur levels are accomplished. However, these loop filters do not have a DC pole and the loop dynamics become Type I, resulting in unfavorable problems. In order to achieve a Type II SC PLL and keep circuit power consumption within a reasonable level, existing solutions [7], [8] employ additional continuous-time (CT) active filters to provide the missing DC pole. However, OTAs or Gm cells in these topology increase

5

power consumption, and more importantly, additional 1/f and thermal noise are introduced. In order to counteract these problems, a new low-power SC loop filter is proposed in this work. Compared with conventional RC loop filters, small on-chip capacitors can be used and reference spurs caused by charge pump current mismatch are eliminated. Compared with other SC loop filter implementations, low-power amplifiers are used to maintain its power consumption low. Additionally, 1/f noise of the active amplifiers can be suppressed by the auto-zero function in the SC circuit. Experimental results demonstrate that with less on-chip space and lower power consumption, a PLL implemented with this loop filter achieves comparable performance to other solutions. Delta-Sigma (ΔΣ) modulation is a very attractive technique to implement high-resolution analog-to-digital or digital-to-analog converters in low-cost CMOS processes, since errors caused by circuit imperfections in signal-bands can be suppressed by the loop filter employed. It is well-known that the performance of a ΔΣ ADC can be significantly improved by using a multi-bit internal quantizer. It enhances loop stability and reduces the sampling frequency compared to implementations with single-bit quantizers for the same SNR. However, when designing a ΔΣ ADC with a multi-bit quantizer, a highly-linear feedback DAC matching the overall ADC accuracy is required, because the feedback signal is subtracted from the analog input directly and no noise-shaping is carried out. The feedback DAC then becomes the major bottleneck when designing a multi-bit ΔΣ ADC, since it is not a trivial task to design a highly-linear (>14bit) DAC in CMOS

6

technologies with the presence of inherent component mismatch. To design a highly linear multi-bit DAC, many approaches have been proposed to counteract errors introduced by element mismatches. Data-weighted-averaging (DWA) technique is most widely used nowadays [9]. However, the DWA technique introduces signal-dependent distortion or performance loss for certain input levels. This is known as the in-band tone problem and its influence still depends on the matching of unit elements [10]-[11]. In this work, we propose to design the ΔΣ feedback DAC in a SC ratio-independent manner. In addition, ΔΣ modulator topologies suitable for the ratio-independent DAC are introduced. By using a gain-boosted sub-threshold inverter as an amplifier, circuit power consumption is kept low. The sensitivity of the differential DAC output linearity on circuit mismatches is reduced by using mutually-referred inputs. Moreover, in-band noise is improved since noise increase introduced by component mismatch in conventional or DWA design is suppressed. Measurement results from a ΔΣ modulator prototype fabricated in a 130nm CMOS process demonstrate that the proposed method offers a power- and space-efficient solution for highly linear data conversions.

1.3

Thesis Orgnization This thesis is organized in the following manner: Chapter 2 reviews the CMOS switched-capacitor technique. Circuit blocks and

some general design considerations along with noise issue are presented. Chapter 3 describes the general theories behind PLL frequency synthesizers. PLL

7

building blocks and implementation issues in conventional architectures are discussed. Chapter 4 explains the basic principles of analog-to-digital conversion and delta-sigma (ΔΣ) modulation. Different ΔΣ topologies are discussed. Stability, noise issues and techniques to enhance its performance are covered. In Chapter 5, PLL loop filter structures reported in recent literatures are reviewed. The low-power active switched-capacitor loop filter is proposed and a PLL frequency synthesizer is designed based on this loop filter. Measurement results are also presented. In Chapter 6, a ratio-independent feedback DAC for ΔΣ ADCs is proposed at the beginning.

In

order

to

reduce

its

power

consumption,

a

low-power

nonlinearity-suppressed switched-capacitor DAC is further proposed and applied to a ΔΣ modulator implementation. Prototype measurement results are presented. Chapter 7 concludes this thesis and future work is discussed.

8

Chapter 2 Switched-Capacitor Circuits

This chapter describes some fundamentals of switched-capacitor (SC) techniques in CMOS technology. Topics on discrete-time signal basics, circuit building blocks and design challenges are covered. A simple sample-and-hold stage and a SC integrator are used to exemplify the analysis methods.

2.1 Discrete-time signal basics Switched-capacitor techniques are widely used in the design of modern analog systems. In an essentially analog real world, SC circuits sample continuous-time input signals and then they are represented and processed in the discrete-time domain. In some applications, in order to interface with other parts of the system, the post-processed discrete-time signals are required to be converted back to analog signals as well. Therefore it's critical to have a basic understanding of the conversion between continuous-time and discrete-time signals. 2.1.1

Spectra of Discrete-Time Signals

By taking samples of the continuous-time signal at uniform time intervals, a discrete-time representation of the signal can be obtained. As shown in Figure 2-1 (a) and (b), x(t) is the continuous-time input signal and x(n) = x(nT) is a discrete-time

9

Figure 2-1: Sampling and Sample-and-Hold

representation of x(t), where T is the sampling period or the sampling frequency is fS=1/T. In order to obtain the spectrum of the sampled signal x(n), its time-domain expression can be written as

x(n) = x(t )i s (t )

(2-1)

where s(t) is a periodic impulse train or

s (t ) =

∞

∑ δ (t − nT ) .

(2-2)

n =−∞

Since multiplication in time-domain corresponds to convolution in frequency-domain, the spectrum of x(n) can be found as [12] XS ( f ) =

1 1 ∞ X ( f ) ⊗ S ( f ) = ∑ X ( j i2π f − j ik 2π f S ) . 2π T k =−∞

(2-3)

The spectra of x(t) and x(n) are illustrated in Figure 2-2. It can be observed that the sampling process in time-domain leads to periodic spectrum replicas in frequency

10

Figure 2-2: Frequency domain illustration of sampling

domain. Also, the amplitude is scaled by 1/T. In order to avoid overlapping of replicated signals in frequency domain (i.e. aliasing) during sampling, the following condition should be satisfied f S − f B ≥ f B or f S ≥ 2 f B ,

(2-4)

where fB is the highest frequency of the input signal. The minimum sampling frequency required to avoid aliasing is referred to as Nyquist rate. 2.1.2

Sample-and-Hold Response

The discrete-time signal obtained by the sampling operation can be converted back to a continuous-time signal with a simple holding operation as shown in Figure 2-1 (c). By defining the step function u(t) as ⎧1, (t ≥ 0) , u (t ) ≡ ⎨ ⎩0, (t < 0)

(2-5)

the sample-and-hold signal xh(t) can be expressed mathematically to be xh (t ) =

∞

∑ x(nT ) [u (t − nT ) − u(t − (n + 1)T )] .

n =−∞

(2-6)

11

Figure 2-3: Sample-and-Hold response

It can be shown that the spectrum of xh(t) is X h ( f ) = H h ( f )i X S ( f ) ,

(2-7)

where XS(f) is given by Eq. (2-3) and Hh(f) is e − j iπ fT sin(π f / f S ) Hh ( f ) = . π fS

(2-8)

The magnitude response of Hh(f) is plotted in Figure 2-3. The holding operation works as a low-pass filter with the sinc response.

2.2 Building Blocks in Switched-Capacitor Circuits 2.2.1

Sampling Switches

MOSFETs have several favorable properties when used as sampling switches. First, it has very large off resistance which makes charge conservation possible. Second, it has reasonable on resistance so that circuit can settle quickly during amplification phase. Third, there is no offset voltage between the source and drain of the transistor switch when it's turned on. A simple sample-and-hold stage with a MOS switch is shown in Figure 2-4.

12

Figure 2-4 MOS sample-and-hold stage

When a MOS transistor is used as a switch, it usually operates in the triode region. Ignoring higher-order effects, the behavior of the transistor can be modeled mathematically as I D = μ Cox

W⎡ 1 (VGS − VTH )VDS − VDS2 ⎤⎥ . ⎢ L⎣ 2 ⎦

(2-9)

In the above equation, ID is the drain current. μ is the mobility of charge carriers. Cox is the gate capacitance per unit area. W and L are the width and length of the transistor and VTH is its threshold voltage. For VDS

2 2(VGS − VTH ) ), the 1 2VDS term

can be ignored and drain current can be approximated as a linear function of VDS and the transistor behaves as a voltage-controlled resistor. The on resistance of the switch is Ron =

1 W μ Cox (VGS − VTH ) L

.

(2-10)

With the equivalent on-resistance known, several considerations can be addressed when a MOSFET is used as a switch. First, during the on state, the sample-and-hold circuit shown in Figure 2-4 becomes a low-pass filter. Assuming the clock high

13

voltage is VCLK,H and the maximum input signal is Vin,max, it is straightforward that the worst case (minimum) bandwidth for the sample-and-hold circuit is

f min =

1 2π Ron ,max CH

=

μCox

W (VCLK ,H − Vin,max − VTH ) L . 2π CH

(2-11)

The above bandwidth should be larger than the maximum frequency of the input signal. Moreover, the on resistance of the switch should be small enough to assure enough settling accuracy. For a single-pole first-order filter, its step response can be found to be Vout (t ) = Vstep (1 − e −t τ ) ,

(2-12)

where τ = Ron CH is the time constant of the sample-and-hold circuit, and Vstep is the size of the voltage step at the input. From Eq. (2-12), the time required for the circuit to settle to within a specific value can be found. For 1% accuracy, t ≥ 4.6τ should be satisfied. Assuming the sampling phase takes half of a sampling period, the requirement for 1% settling accuracy can be rewritten as 1 4.6 ≥ . 2 f S 2π f min

(2-13)

Equation (2-13) can be simplified as f min ≥ 1.46 f S . Compared with Eq. (2-11), since fS should be at least two times the input maximum frequency to avoid aliasing, the settling accuracy requirement is usually more stringent than the simple bandwidth requirement above. Another concern on the MOS switch is related to precision issues. In Figure 2-4,

14

when the MOSFET is turned on, some charge is stored in the channel capacitance and it can be denoted by

Qch = WLCox (VCLK , H − Vin − VTH ) .

(2-14)

When the MOSFET is turned off, with fast transition assumed, half of the charge will flow onto the holding capacitor CH. This is called the charge injection problem and it causes an output voltage error which equals

ΔV =

WLCox (VDD − Vin − VTH ) . 2CH

(2-15)

Equation (2-15) indicates that ΔV is linearly related to Vin, and this introduces gain error to the circuit. But this is obtained under the assumption that VTH is a constant. In the real case, VTH changes with the variations of the transistor's source-bulk voltage VSB and the relationship between the two is a nonlinear process which can be modeled as VTH = VTH 0 + γ

(

2Φ F + VSB −

)

2Φ F ,

(2-16)

where VTH0 is the threshold voltage when VSB=0, γ is the body effect coefficient and ФF is the difference between the built-in Fermi potential of the substrate and intrinsic silicon. For a NMOS switch, assume the substrate is tied to the power ground, and thus VSB equals approximately Vin. Therefore, ΔV is related to Vin nonlinearly and this results in distortion for the circuit. In addition to the charge injection problem mentioned above, there is another phenomenon called clock feed-through which can challenge the precision of switched-capacitor circuit. Due to the gate-drain or gate-source overlap capacitance

15

Figure 2-5 Charge injection and clock feed-through suppression by dummy switch

Cov in a transistor, the clock signal will be coupled onto the holding capacitor and the error can be expressed as

ΔV = VCLK , H

Cov . Cov + CH

(2-17)

The effect of charge injection and clock feed-through should be investigated carefully in specific applications, and proper measures should be taken to counteract these problems. Otherwise, circuit performance could be degraded dramatically. A popular method of suppressing both the charge injection and clock feed-through effects are illustrated in Figure 2-5 [13], where a half-sized dummy switch is used. It can be shown that ideally the charge injected from T1 can be absorbed by T2 and the error caused by clock feed-through can also be canceled. But in real world, the assumption that the T1 channel charge is split equally in the two directions does not hold generally. However, it can still reduce the output error to less than about one-fifth the value it would have without it. Differential configuration can also relieve the charge injection problem by

16

cancelling offset and suppressing the even order distortions. Other techniques such as using complementary transmission gate, bottom-plate sampling technique [14], and bootstrapping technique are also widely adopted. 2.2.2

Capacitors

The low-cost single-poly CMOS processes employed to implement circuit designs in this work offer Metal-Insulator-Metal (MIM) options to construct relatively accurate on chip capacitors. The cross section of a dual MIM capacitor is depicted in Figure 2-6. In this structure, the top plate of the formed capacitor is Thin Metal 2 and the bottom plate is Thin Metal 1 and Metal 2 (M2) which are connected together by vias and Metal 1 (M1). It is important to indentify the two plates in applications that are sensitive to parasitic effects. Distinct difference in parasitic capacitance between the two plates is present, since a substantial capacitance exists between the bottom

Figure 2-6 Cross section of a MIM capacitor

17

plate M2 and substrate (signal ground) but the parasitic capacitance of the top plate is mainly contributed by the interconnect capacitance. By using this dual MIM capacitor shown in Figure 2-6, capacitance density and thus space-effectiveness are significantly improved. Several non-idealities in capacitors introduce noise and distortion to SC circuits. The first issue is capacitor mismatch originated from linear gradients which arise from non-uniform dielectric growth conditions and from random variations. A charge redistribution DAC consisting of unit capacitors of the same nominal size can be used to demonstrate the influence of linear gradients. As shown in Figure 2-7, during the reset phase, all the capacitors are discharged to zero. During the output phase, assuming a number of j capacitors are connected to Vref according to the input thermometer code and then the output voltage will be jVref/N if all the capacitors are

Figure 2-7 A charge redistribution DAC and its equivalent circuit during output phase

18

identical. With the presence of linear gradients effect, the capacitor array will be valued as C1, C2+ΔC, … , CN+(N-1)ΔC and the output voltage in turn will be j −1

Vout =

∑ ( C + iΔC )V

ref

i =0 N −1

∑ ( C + iΔC ) i =0

j ( j − 1) ΔC 2 = Vr ef . N ( N − 1) NC + ΔC 2 jC +

(2-18)

Differential nonlinearity (DNL) can be found as

DNL j = (V j +1 − V j ) − Vref

N −1 ⎞ ⎛ ⎜ j− ⎟ ΔC V 2 ⎠ ref ⎝ N= . N −1 C+ ΔC N 2

(2-19)

Integral nonlinearity (INL) can be found as

INL j =

j ( N − j ) ΔC Vref j Vref − V j = . N −1 N N 2 C+ ΔC 2

(2-20)

In addition to mismatch caused by process linear gradients, in reality capacitors also exhibit random mismatch originating from dimension variations during fabrication. The percentage mismatch for identical adjacent MIM capacitors with the same orientation and at the same voltage can be modeled as

M=

M A2 M W2 M L2 + + 2 %, WL W 2 L

(2-21)

where W and L is the width and length of the capacitor and MA, MW and ML are the mismatch parameters. Though Eq. (2-21) indicates that increasing capacitor dimension can increase the matching, gradient effect becomes more significant in large capacitors and mismatch can deteriorate when the dimension reach a certain size

19

[15]. For large capacitors, unit-size capacitors laid out in the common-centroid manner can be employed to achieve good matching. The second issue with capacitors is their voltage dependence [16]. With αi as the ith-order voltage coefficient of a capacitor, its capacitance can be modeled as

C=

dQ = C0 (1 + α1V + α 2V 2 + ...) . dV

(2-22)

This voltage dependence introduces nonlinearities into the circuits. In most cases, coefficients with orders higher than two are much smaller and negligible. In differential applications, assume an increase of voltage from 0 to V1 happened on the capacitor in the positive half circuit and a decrease of voltage from 0 to –V1 is accompanied in the negative half, the amount of charge changed on the two capacitors are expressed as ΔQ1 ≈ ∫ C0 (1 + α1V + α 2V 2 ) dV = C0V1 + V1

0

α1 2

C0V12 +

α2 3

C0V13

(2-23)

α2

(2-24)

and

ΔQ2 ≈ ∫

−V1

0

C0 (1 + α1V + α 2V 2 ) dV = −C0V1 +

α1 2

C0V12 −

3

C0V13 ,

respectively. Therefore when the output is taken as ΔQ1-ΔQ2, odd order coefficients in Eq. (2-22) can be suppressed and the effect of α2 is dominant. 2.2.3

Amplifiers

In switched-capacitor technique, amplifiers play a critical rule in defining circuit's precision, speed and power consumption. With capacitive loads employed in SC circuits, the low-output-impedance buffer in an operational amplifier (opamp) is

20

usually omitted and operational-transconductance-amplifier (OTA) is thus formed. Though different structures can be used to implement an OTA, the same model with parameters such as DC gain, unity gain frequency and slew rate can be used to describe the performance of a conventional OTA. Some insights on the performance of the SC circuit can also be obtained with these parameters. If an OTA is properly compensated, it exhibits a simple first-order single-pole response at frequencies of interest. With ωp1 as the dominant pole, the transfer function of an OTA can be modeled as A( s ) =

A0 , 1 + s ω p1

(2-25)

where A0 is the finite DC gain of the OTA and s is the complex frequency. The unity gain frequency ωta of the OTA can be calculated by setting the magnitude of Eq. (2-25) to 1 and we have

ωta ≈ A0ω p1 .

(2-26)

The effects of finite DC gain and unity gain frequency of the OTA on the performance of a SC integrator shown in Figure 2-8 are discussed in detail below. Φ1 and Φ2 are non-overlapping clocks and Φ1a and Φ2a are simply the advanced version of them. This arrangement can reduce the effect of switch charge injection. It can be derived that with an infinite OTA DC gain, the transfer function of the circuit is H ( z) =

Vout ( z ) C1 z −1 = . Vin ( z ) C2 1 − z −1

(2-27)

On the other hand, if the finite gain of A0 is accounted for, the integrator becomes

21

leaky and the gain is also altered. The transfer function becomes H ( z) =

Vout ( z ) C1 gz −1 = , Vin ( z ) C2 1 − α z −1

(2-28)

where g and α are the actual gain and the leakage factor, respectively, shown below g=

A0 , A0 + 1 + C1 C2

(2-29)

α=

A0 + 1 . A0 + 1 + C1 C2

(2-30)

It can be observed that in a SC filter circuit, the finite OTA DC gain not only affects the accuracy of circuit coefficients (magnitude error), it also changes the locations of the poles or zeros (phase error) of the filter. Depending on applications, the DC gain of an OTA in SC circuits typically ranges from 40dB to 90dB. As mentioned in Section 2.2.1, a single-pole first-order filter has an exponential step response. In order to assure a certain settling accuracy, the OTA should have a unity gain bandwidth large enough. The small-signal equivalent circuit of the integrator in Figure 2-8 during the amplification phase or Phase 2 is illustrated in

Figure 2-8 A typical switched-capacitor integrator

22

Figure 2-9 Equivalent circuit of Figure 2-8 in Phase 2

Figure 2-9. Two resistors RS1 and RS2 are used to model the resistance of the MOS switches. gm is the transconductance of the OTA. By applying an input signal Vin to the integrator, the current i can be found as i=

Vin − VX . ( RS1 + RS 2 ) + 1 sC1

(2-31)

Considering the fact that i = g mVX ,

(2-32)

VX is found to be VX =

Vin sC1 / g m . 1 + sC1 (1/ g m + RS 1 + RS 2 )

(2-33)

Then the transfer functions of the capacitor voltages are

where

VC1 1 = , Vin 1 + sτ

(2-34)

VC 2 C1 1 = , Vin C2 1 + sτ

(2-35)

23

τ = C1 (1 g m + RS 1 + RS 2 ) .

(2-36)

The closed-loop -3dB bandwidth is

ω−3dB =

gm 1 . C1 (1 + g m ( RS 1 + RS 2 ) )

(2-37)

The settling error can be simply denoted as Int ω−3 dB

δ = e −T

(2-38)

,

where TInt is the duration of the integration phase and it's directly related to sampling frequency fS of the integrator. If TInt is taken as 1/(2fS), f-3dB should be at least 2.23 times fS to achieve 0.1% settling accuracy. The sampling frequency and the size of C1 are usually selected according to specifications of circuit performance. It is obvious that to achieve good settling accuracy, an adequate gm or unity gain frequency ( ωta = g m CLOAD ) of the OTA is required. Also the resistance of the switches should be as small as possible. In order to assure fast settling, slew rate limiting should be avoided. Slew rate (SR) is the maximum rate that the output voltage can change, or mathematically SR =

dVout dt

max

=

I LOAD max . CLOAD

(2-39)

For the output voltage response described in Eq. (2-12), its maximum slope is dVout dt

max

=

VSTEP

τ

.

(2-40)

Thus, the output current that an OTA can provide should statisfy I LOAD ≥

VSTEP

τ

CLOAD

(2-41)

24

Figure 2-10 Block diagram for a basic negative-feedback system

and then no slew rate limiting would occur. The above analysis focuses on the effects of the magnitude response of circuits and the OTA is approximated as a first-order single pole system. However, in reality, the phase response is more complicated and it has a strong influence on circuit behavior. The block diagram of a negative-feedback system is shown in Figure 2-10. Its closed-loop transfer function is H CL ( s ) =

H ( s) . 1 + H ( s) β

(2-42)

Its loop gain is H OL ( s) = β H ( s ) .

(2-43)

The magnitude and phase responses of the loop gain for a two-pole system are depicted in Figure 2-11. To assure system stability, loop gain magnitude should drop to below unity at a frequency for which its phase shift is less than 180 degree. Defining phase margin (PM) as PM = H OL (ω0 ) + 180° ,

(2-44)

where ω0 is the gain crossover frequency, at which the magnitude of loop gain is unity. Phase margin is an important parameter to evaluate system stability, and moreover,

25

Figure 2-11 Bode plots of loop gain for a two-pole system

the transient response for switched-capacitor circuits. To achieve small ringing and fast settling at the same time, a phase margin of around 60 degree is usually selected.

2.3 Noise in Switched-Capacitor Circuits 2.3.1

KTC noise

The equivalent circuit during sampling phase for the sample and hold circuit shown in Figure 2-4 is illustrated in Figure 2-12. Since the power spectral density of the resistor thermal noise is 4kTR (k is Boltzmann Constant and T is the absolute temperature), the output noise power of the circuit is

26

Figure 2-12 Sample-and-hold equivalent circuit during sampling phase

Pn = ∫

∞

0

2

∞ 1 4kTR kT . 4kTR df = ∫ df = 2 2 2 2 0 1 + sRC 4π R C f + 1 C

(2-45)

This is known as the KTC noise or sampling noise. This result implies that the output noise is independent of the value of R. For a given temperature, kT/C noise can be decreased only by increasing C. In switched capacitor circuits, the bandwidth of thermal noise is usually much larger than the sampling frequency. Therefore, the thermal noise is under-sampled and heavily aliased. For each sampling bandwidth fS, the noise power is kT/C. Since the spectrum of the folded thermal noise is very nearly white [17], [18], the single-sided sampled thermal noise power spectral density is S( f ) = 2.3.2

2kT . Cf S

(2-46)

Thermal noise of a switched-capacitor integrator

For the integrator shown in Figure 2-8, during the sampling phase, the thermal noise power on C1 is Pn ,Φ1 =

kT . C1

(2-47)

During the integration phase, as illustrated in Figure 2-9, the integrator can be

27

approximated as a lowpass filter with a -3dB bandwidth shown in Eq. (3-27). For a first-order filter with -3dB bandwidth of ω-3dB and DC gain of G0, its transfer function can be expressed as H (s) =

G0 . 1 + s ω−3dB

(2-48)

Its equivalent noise bandwidth is f eq =

1 2π

∫

∞

0

2

H ( jω ) ω π ω−3dB π dω = = f −3dB = −3dB . 2 G0 2 2π 2 4

(2-49)

With gm as the trans-conductance of the input transistor, the power spectral density of a conventional OTA is approximately [19] SOTA ≈

16kT . 3g m

(2-50)

The noise power on C1 during the integration phase is thus ⎛ 16kT ⎞ ω−3dB , Pn ,Φ 2 = ⎜ 4kT ( RS 1 + RS 2 ) + ⎟ 3g m ⎠ 4 ⎝

(2-51)

where ω-3dB is given by Eq. (2-37). The input-referred thermal noise power of the switched-capacitor integrator Pn is then given by Pn = Pn ,Φ1 + Pn ,Φ 2 =

⎞ 2kT ⎛ 16 ⎜⎜ 1 + ⎟. C1 ⎝ 1 + g m ( RS 1 + RS 2 ) ⎟⎠

(2-52)

Since 0 < g m ( RS 1 + RS 2 ) < ∞ , we have 2kT C1 < Pn < 2.33kT C1 .

(2-53)

The relationship between Pn and gm(RS1+RS2) is plotted in Figure 2-13. Though a

28

Figure 2-13 Input referred integrator thermal noise power versus gm(RS1+RS2)

large gm(RS1+RS2) gives a relatively small noise power, this does not indicate that the large switch on-resistance is a good circuit design practice. When large on-resistance switches are used, gm should be increased accordingly in order to achieve comparable circuit speed. This would result in a significant increase of circuit power consumption. This can also be explained mathematically below. Equation (2-52) can be rearranged as Pn = and gm can be solved as

2kT ω−3dB ( 7 6 + g m ( RS1 + RS 2 ) ) , gm

(2-54)

29

Figure 2-14 Opamp feedback circuit

gm =

kT ω−3dB 7 . 3 Pn − 2kT ω−3dB ( RS 1 + RS 2 )

(2-55)

This result implies that for a given settling time (determined by ω-3dB) and noise constraint Pn, the solution to minimize gm or power consumption is the one that minimize the switch resistance RS1+RS2. The above analysis only accounts for the noise on C1 for each integration period. The opamp noise during the sampling phase is not included. However, in reality, the opamp noise does contribute to the total output noise. For an opamp circuit with capacitive feedback coefficient β=C2/(C1+C2) and load CL=C3+C1C2/(C1+C2) as shown in Figure 2-14, its transfer function is H (s) ≈

1

1 β ⎛ C 1+ s ⎜ L ⎝ gm β

⎞ ⎟ ⎠

.

(2-56)

Using Eq. (2-50) and (2-56), the output noise for the circuit in Figure 2-14 is thus ⎛ 16kT Pn ,op ,out = ⎜ ⎝ 3 g m1

⎞ ⎛ 1/ β 2 ⎞ 4 kT . ⎟⎜ ⎟= 4 τ 3 β C ⎝ ⎠ L ⎠

(2-57)

When the integrator is in the sampling phase, the opamp forms a circuit similar to the

30

Figure 2-15 Integrator noise model

one in Figure 2-14 with C1=0. Therefore its output noise power is simply Pn ,op ,Φ1 =

4 kT . 3 CL

(2-58)

This noise is under sampled at the integrator output and has a nearly white PSD. Its power over [0, fS] is simply Eq. (2-58). The integrator can then be modeled as shown in Figure 2-15 with a noiseless integrator and two white noise sources, which are mathematically described by Eq. (2-52) and (2-58), at the input and output, respectively.

31

Chapter 3 PLL Frequency Synthesizer

This chapter presents the theoretical analysis of PLL-based frequency synthesizers. Linearized small-signal phase loop transfer function and basic building blocks are included. Implementation issues and noise considerations are discussed.

3.1 PLL basics The concept of phase-locked loops (PLLs) was first introduced by H. de Bellescize in 1932 [20] and it is soon widely used in the areas of televisions and FM radio. Nowadays, PLLs have become critical components in various electronic systems for their versatility. In super-heterodyne transceivers, the local oscillator signal for frequency translation and channel selection comes from a PLL-based frequency synthesizer. For high speed micro-processing and data conversion systems,

Figure 3-1: Phase-locked loop block diagram

32

generation and recovery of clock signals also relies on PLLs. Though the basic principle behind PLLs remains nearly the same, with the fast development of modern semiconductor technology, their implementation with compatible architectures for diverse applications is still an area of active research. 3.1.1

Type I PLL

A PLL synchronizes the output phase of a tunable oscillator with the phase of a reference clock, by means of negative feedback. Generally, it consists of a phase detector, a low-pass loop filter, and a voltage-controlled-oscillator (VCO). The basic PLL architecture is depicted in Figure 3-1. A PLL is a phase-processing system and it should be analyzed in the phase domain. The phase detector compares the phase difference between the reference input and the feedback output signals, and it produces an output in terms of current or voltage which is usually proportional to the phase difference. The output from the phase detector is filtered and then used to drive the VCO in order to reduce the phase difference. Ignoring the nonlinearities in the VCO, it is straightforward that a VCO is an integrator in phase domain and its continuous-time transfer function is HVCO ( s ) = KVCO s ,

(3-1)

where KVCO is the sensitivity of the VCO with a unit of Mrad/s/V. Assuming that a simple first-order low-pass filter with -3dB bandwidth of ωLF is employed as the loop filter in Figure 3-1 and the phase detector has a gain of KPD, the loop gain of the PLL can be obtained as

33

Figure 3-2: Magnitude and phase response of the Type I PLL loop gain

H OL ( s ) =

K PD KVCO . s (1 + s ωLF )

(3-2)

Since Eq. (3-2) has only one pole at origin, this PLL is named as Type I. Another pole exists at s=ωLF and the loop gain magnitude and phase response is plotted in Figure 3-2. In a Type I PLL, phase margin can be adjusted easily. The phase margin Фm of Eq. (3-2) is simply Φ m = 90 − tan −1

ωc , ωLF

(3-3)

where ωc is the crossover frequency or the open-loop unity gain frequency and it is given by

34

ωc =

2 2 2 2 ωLF ωLF + 4 K PD KVCO − ωLF

2

.

(3-4)

With fixed ωc, increasing ωLF results in a larger phase margin. The closed-loop transfer function of this Type I PLL can be written as H CL ( s ) =

H OL ( s ) K PD KVCO = . 1 + H OL ( s ) K PD KVCO + s + s 2 ωLF

(3-5)

Equation (3-5) can be rearranged as H CL ( s ) =

ωn2 , s 2 + 2ζωn s + ωn2

(3-6)

where ωn and ζ are the natural frequency and the damping ratio respectively and they are given by

ωn = ωLF K PD KVCO , ζ =

ωLF 1 . 2 K PD KVCO

(3-7) (3-8)

The step response of this system can be overdamped, critically damped, or underdamped, depending on the value of ζ. For ζ ≤ 1 , the step response approaches its final value exponentially with a time constant 1 (ζωn ) , thus the settling speed of the PLL is directly related to

ζωn =

ωLF 2

.

(3-9)

Though a large ωLF decreases the settling time of the system, it allows more high-frequency components pass through the loop filter and compromises system performance. This is a problem rising from the direct coupling of the above loop

35

parameters. Another observation on Type I PLL is that a non-zero phase error between the input and output is required to drive the VCO to the correct frequency. To examine this problem, the input to phase error (Φin-Φout) transfer function can be derived as H e (s) =

Φ in − Φ out s 2 + 2ζωn s = 2 . Φ in s + 2ζωn s + ωn

(3-10)

Assume an input frequency step of Δωinu(t) (where u(t) is the step function) occurs, the steady-state phase error can be found as sΦ e ( s ) = lim s ( Φin − Φ out ) t =∞ = lim s →0 s →0

Δωin Δωin H e (s) = . 2 s K PD KVCO

(3-11)

This result reveals that the steady-state phase error cannot be zero in this system and it is directly related to KPD and KVCO, or the loop bandwidth. Generally, a steady-state phase error of zero is preferred. Along with the limited lock-in range problem [21], [22], i.e. the loop can acquire lock only if the difference between the input and output is on the order of ωLF, Type-I PLL is not frequently used. 3.1.2

Type II PLL

Zero steady-state phase error can be achieved using the Type II PLL or the charge pump PLL. A simple charge pump PLL with a first-order passive loop filter is illustrated in Figure 3-3. A divider with division ratio N is also included to illustrate a more general frequency synthesizer. The impedance of the loop filter can be found as Z LF ( s ) =

1 + sR1C1 . sC1

With a charge pump output current ICP, the loop gain for this PLL is

(3-12)

36

Figure 3-3: Second order Type II PLL block diagram

H OL ( s ) =

I CP KVCO (1 + sR1C1 ) . 2π Ns 2C1

(3-13)

Though a first-order loop filter is used, since the VCO introduces another pole at origin, this PLL is a second-order system. It is called the Type II PLL because there are two poles at the origin. In practical designs, higher-order filters may be used to suppress VCO control voltage ripples. Similarly, the PLL is always one-order higher than the loop filter. A zero

ω z = 1 ( R1C1 )

(3-14)

is introduced by R1 and it serves for stabilizing purpose. Without the zero, the loop is obviously unstable due to the two origin poles. Let KCP=ICP/2π, K=KCPKVCOR1/N, the loop gain is rewritten as H OL ( s ) =

K (1 + s ω z ) . s 2 ωz

(3-15)

The magnitude and phase response of Eq. (3-15) is plotted in Figure 3-4. The zero stabilizes the loop by providing a positive phase shift. The phase margin Фm is

37

Figure 3-4: Magnitude and phase response of the Type II PLL loop gain

simply Φ m = tan −1

ωc , ωz

(3-16)

and the crossover frequency ωc is given by

ωc =

K 2 + K K 2 + 4ω z2 . 2

(3-17)

At the crossover frequency the phase shift is Фc, and we have sin Φ c = −

K ωc ωz

ω ωz 2 c

=−

K

ωc

,

(3-18)

38

Φ m = 180 + Φ c ,

(3-19)

With the use of the above two equations ωc can also be expressed as

ωc = K sin Φ m .

(3-20)

The closed-loop gain of this PLL can be found as H CL ( s ) = N

K ( s + ωz ) . s + Ks + K ω z 2

(3-21)

Equation (3-21) can be rearranged in the following form H CL ( s ) = N

2ζωn s + ωn2 , s 2 + 2ζωn s + ωn2

(3-22)

where the natural frequency ωn and the damping factor ζ are

ωn = K ω z , ζ =

1 K 2 ωz

(3-23) (3-24)

,

By using Eq. (3-16) and Eq. (3-20), the above equations can be rewritten as

ωn = ωc cos Φ m , ζ =

(3-25)

1 sin Φ m . 2 cos Φ m

(3-26)

The closed-loop -3dB frequency for the loop can be found as

ω−3dB = ωn

( 2ζ

2

+ 1) +

( 2ζ

2

+ 1) + 1 . 2

(3-27)

Using Eq. (3-25) and Eq. (3-26), the ratio ω-3dB/ωc versus damping factor is found and plotted in Figure 3-5. With a reasonable damping factor, ω−3dB ≈ ωc . Thus the

39

open loop crossover frequency is referred to as the PLL bandwidth in future discussion. With an input frequency step of Δωu(t)/N occurs, the PLL output response is Δωout ( s ) =

Δω H CL ( s ) . Ns

(3-28)

The time-domain step response of the PLL is found as shown in Eq. (3-29) using inverse Laplace transformation on Eq. (3-28). ⎧ ⎧ ⎡ ⎤ ⎫⎪ ζ ⎪Δωu (t ) ⎪⎨1 − e −ζωnt ⎢cos ωnt 1 − ζ 2 − sin ωnt 1 − ζ 2 ⎥ ⎬ ( 0 < ζ < 1) ⎪ 1− ζ 2 ⎢⎣ ⎥⎦ ⎪⎭ ⎪⎩ ⎪ ⎪ Δωout (t ) = ⎨Δωu (t ) ⎣⎡1 − e −ωnt (1 − ωnt ) ⎦⎤ (ζ = 1) ⎪ ⎧⎪ ⎡ ⎤ ⎫⎪ ⎪ ζ −ζωn t 2 2 Δ − − − − ω ω ζ ω ζ u ( t ) 1 e cosh t 1 sinh t 1 ⎢ ⎥ ⎬ (ζ > 1) ⎪ ⎨ n n ζ 2 −1 ⎢⎣ ⎥⎦ ⎪⎭ ⎪⎩ ⎪⎩

)

(

(

)

(

)

)

(

(3-29) The response is also plotted in Figure 3-6 for different damping factors. For most practical designs, 0 < ζ < 1 . The first line of Eq. (3-29) can be rewritten as ⎧⎪ ⎫⎪ 1 e −ζωnt ⎡sin sin −1 1 − ζ 2 − ωnt 1 − ζ 2 ⎤ ⎬ . (3-30) Δωout (t ) = Δωu (t ) ⎨1 − ⎣⎢ ⎦⎥ ⎪ 1− ζ 2 ⎩⎪ ⎭

(

)

Equation (3-30) indicates that the step response settles with a time constant 1/(ζωn) or 4πN/(ICPR1KVCO) and it also contains a decaying sinusoidal component. Compared with the Type I PLL whose settling speed is strongly coupled with ωLF only, the locking time of Type II PLL depends on multiple factors. It is clear that the second term in Eq. (3-30) has a maximum value of 1/ 1 − ζ 2 . Then the locking time for a specific relative settling accuracy ε is

40

Tlock =

(

ln ε 1 − ζ 2

ζωn

).

(3-31)

Figure 3-5: The ratio ω-3dB/ωc versus damping factor

Figure 3-6: Time-domain output frequency response of a second-order Type II PLL

41

Figure 3-7: Fourth order Type II PLL block diagram

The second-order Type II PLL is infrequently used because of large VCO control voltage ripples generated by the loop filter. In order to solve this problem, one or more additional poles in the loop filter are usually present in a practical design [23] as shown in Figure 3-7 and a third- or higher order PLL is formed. The analysis of a third-order Type II PLL (with R3=0 and C3=0 in Figure 3-7) is presented below and design insights for higher-order systems can be obtained similarly. The impedance of the loop filter can be found as Z LF ( s ) =

1 + sR1C1 1 + s ωz R1C1 = , ⎛ 1 + s ω p 2 ) s ω z C1 + C2 R1C1C2 ⎞ ( ⎜1 + s ⎟ s ( C1 + C2 ) C1 + C2 ⎠ ⎝

(3-32)

where ωz=1/(R1C1). Let n=(C1+C2)/C2, we have

ω p 2 = ( C1 + C2 ) ( C2 R1C1 ) = nω z .

(3-33)

Let K=KCPKVCOR1/N, the loop gain for this third-order PLL is H OL ( s ) =

n − 1 K (1 + s ω z ) . n s 2 ω z (1 + s ω p 2 )

The bandwidth of a third-order Type II PLL is

(3-34)

42

ωc = K

cos(tan −1 ωc ω p 2 ) n − 1 sin(tan −1 ωc ωz )

n

.

(3-35)

The loop gain phase margin can be found as Φ m = tan −1 (ωc ω z ) − tan −1 (ωc ω p 2 ) .

(3-36)

d Φm =0, d ωc

(3-37)

By setting

the condition for the maximum phase margin can be found as

ωc = ω p 2ωz = n ⋅ ωz .

(3-38)

The maximum phase margin is Φ m ,max = tan −1

n −1 . 2 n

(3-39)

and the relationship between the maximum phase margin and n is plotted in Figure 3-8. In practice, (n-1) or C1/C2 is usually larger than 10 to allow sufficient phase margin.

Figure 3-8: Maximum phase margin versus n

43

When Eq. (3-38) is satisfied the closed-loop transfer function of the PLL can be found as H CL ( s )

max Φ m

=

N nωc2 s + ωc3

( s + ωc ) ( s 2 + (

)

n − 1 ωc s + ωc2

)

=N

( 2ζ + 1) ωn2 s + ωn3 , (3-40) ( s + ωn ) ( s 2 + 2ζωn s + ωn2 )

where the damping factor ζ and the natural frequency ωn are n −1 , 2

ζ =

(3-41)

ωn = ωc .

(3-42)

The criterion for stability of the third-order Type II PLL is found as [23], [24] 2π K ( n − 1) < − 2π nω z ωref n 2π 1 + e

(

(

4 1+ e ωref

)ω

z

− 2π nω z ωref

(

)

ωref + 2 1 − e

− 2π nω z ωref

) ( n − 1)

n

,

(3-43)

where ωref is the input reference frequency. Under the maximum phase margin condition, the loop bandwidth is reduced to

ωc = K

n −1 . n

(3-44)

By using Eq. (3-38) and Eq. (3-44), Equation (3-43) can be rewritten as ⎛ ω ⎜⎜ 2π c ⎝ ωref

2

⎞ 1 + e −2π ⎟⎟ n ⎠

n

⎛ ω + ⎜ 2π c ⎜ ω ref ⎝

(

−2π n ⎞ 2 1− e ⎟⎟ n ⎠

) ( n − 1) − 4 1 + e (

−2π n

)1 and resonant frequency of ω0, we have

( ω0 L )

RLSP = RLS ( Q + 1) ≈ RLS Q = RLS 2 L

2 L

2

2 RLS

,

(3-51)

thus

RLSP

(ω L ) ≈ 0

2

RLS

= QLω0 L .

(3-52)

Similarly, for a varactor with a quality factor of QV>>1, its equivalent parallel resistance is

RCP ≈

QV ω0CV

(3-53)

The total positive trans-conductance of the tank is approximately

gtotal

g + gV + g 0 1 RLP + RLS 1 = = L ≈ 2R 2

2 (ω L ) + ωCV

QV + 1 R0

2

.

(3-54)

The circuit oscillates if the absolute value of the negative trans-conductance is equal or greater than the positive trans-conductance, or mathematically

gm ≥ gtotal , or g m ≥ 1 RLP + RLS 2

2 (ω L ) + ωCV

QV + 1 R0 .

(3-55)

In practice, the trans-conductance of the cross-coupled transistor is usually taken as more than 3 times of gtotal to account for circuit non-idealities.

3.3 Implementation Issues and Noise 3.3.1

Implementation Issues

The first problem with the charge-pump PLL is the large on-chip capacitors required [40]-[42]. In the above analysis, it has been shown that a C1/C2 ratio of more

53

than 10 is usually required to achieve sufficient phase margin. This problem can be better demonstrated by the following design example, with target parameters listed in Table 3-1. Table 3-1: Design parameters for a 2.4GHz PLL Center Frequency

2.4GHz

Tuning Range

160MHz

KVCO

2π×160M rad/s/V

ICP

100uA

ωc

2π×100kHz

Reference Frequency

10MHz

The division ratio is 232~248. Chose n=16, and ωz=ωc/4, ωp2=4ωc. Phase margin calculated from Eq. (3-39) is Φ m = 62 . Using Eq. (3-44), we have

ωc =

I CP KVCO R1 n − 1 = 2π ×100 ×103 rad / s . 2π N n

(3-56)

R1 is found to be 10.05kΩ. C1 = 1 (ω z R1 ) = 634 pF and C2 = 42 pF . If the capacitors (especially C1) are implemented on-chip, they will take enormous space. In order to counteract this problem, off-chip loop filters are often used. In other solutions, active loop-filters can be employed. The disadvantage of these methods is performance degradation by additional noise introduced to the PLL and additional power consumed by the active elements. Another issue with the Type II or charge-pump PLL is the reference spur caused by the mismatch of the charge pump currents [43]-[48]. As shown in Figure 3-12, the Up current is defined by a PMOS current source and the Down current is defined by a

54

Figure 3-20: Mechanism of VCO control voltage ripples

NMOS current source. It is difficult to match the two currents accurately in CMOS technologies and the presence of current mismatch leads to periodic ripples on the VCO control voltage even when the loop is locked. This can be explained with the help of Figure 3-20. When the loop is locked, the net charge injected into the loop filter should be zero. If the Up current is smaller than the absolute value of the Down current, the duration of the Up current pulse should be longer than the Down current pulse. Then the loop filter will see a positive input current when the Up current is on at the beginning. Later the input current becomes negative when the Down current is also on. Thus the voltage on the loop filter will experience a ripple. Moreover, since the currents are related to the drain voltages of the current source transistors, the current mismatch relies on the control voltage or the VCO output frequency. Other factors such as charge injection and clock feed-through from the switch transistors and charge sharing of the parasitic capacitance at the drain nodes of the current source transistors further increases the VCO control voltage ripple. Jitter peaking is another factor that can affect the performance of Type II PLL

55

[49][50]. It is caused by the stabilizing zero which gives a greater than one (for N=1) closed-loop transfer function gain at frequencies approximately between the zero and the second pole frequency. The magnitude response of a third-order Type II PLL closed-loop transfer function is plotted in Figure 3-21. The zero and the second pole are located at 1.6 MHz and 18MHz, respectively. If there is modulation on the input signal, spectral components within the jitter peaking frequency band experience excess phase excursion. In most applications, the jitter peaking problem can be neglected as long as a large enough damping ratio is used. 3.3.2

Noise Consideration at Different Nodes

A PLL frequency synthesizer consists of multiple circuit blocks as described in Section 3.2. Each of these sub-circuits injects noise into the frequency synthesizer and it is necessary to examine the effects of the noise at each node to gain some design insights. With a PLL open-loop gain HOL(s), the phase noise transfer function for each

Figure 3-21: Magnitude response of a third-order Type II PLL closed-loop transfer function

56

Figure 3-22: Lineralized PLL phase noise model

noise source are listed in Table 3-2. Their magnitude response for an example PLL is plotted in Figure 3-23. Table 3-2: PLL Phase noise transfer function for different noise sources Noise Source Input Noise PFD/CP Noise

Transfer Function

θ out ( s) H ol ( s ) =N θ n ,in ( s) 1 + H ol ( s ) θ out ( s ) in,CP ( s )

=N

H ol ( s ) K CP (1 + H ol ( s ) )

Low-pass Low-pass

Loop Filter Noise

θ out ( s ) KVCO 1 = vn , LF ( s ) s 1 + H ol ( s )

Band-pass

VCO Noise

θ out ( s) 1 = θVCO ( s ) 1 + H ol ( s)

High-pass

Divider Noise

θ out ( s) H ol ( s ) = −N θ n , div ( s) 1 + H ol ( s )

Low-pass

It can be observed that while the input noise transfer function has a low-pass shape, the VCO noise transfer function has a high-pass shape. This introduces a trade-off on the loop bandwidth when implementing a PLL. If noise from input clock source is dominant, then reducing the PLL (noise) bandwidth reduces the phase noise

57

Figure 3-23: PLL noise transfer function response

at the output. However, if the VCO noise is dominant, then a large bandwidth is in need to reduce the output phase noise. Therefore, an optimal bandwidth which leads to the minimum output phase noise exists. It can be found with the knowledge of detailed parameters for each noise source.

58

Chapter 4 Delta-Sigma A/D Converters

4.1

A/D Conversion Basics Digital signal processing is extensively used in modern electronic systems due to

its simplicity, robustness and flexibility for design and implementation. However, in an inherently analog world, analog-to-digital (A/D) or digital-to-analog (D/A) converters are indispensable to interface signals in real world with the digital signal processing blocks. With the rapid development of digital signal processing techniques, the demand for high-speed high-accuracy data converters becomes ever-increasingly large. While technology scaling imposes multiple difficulties in accurate analog circuit implementation, a new technique suitable for low-power high-resolution Multi-bit Delta-Sigma (ΔΣ) A/D converters is proposed and presented in this work. This chapter reviews the basics of A/D and ΔΣ A/D converters. 4.1.1

Sampling and Quantization

Analog-to-Digital conversion can be accomplished by uniform sampling in time and quantization in amplitude. As discussed in Section 2.1, a discrete-time representation of the analog (continuous-time) signal can be obtained by taking samples at uniform time instances nTS, where Ts is a sampling period. If the spectrum of the analog signal is band-limited within [-fB, fB] and the sampling frequency is

59

(a) 3-bit or 8-level midriser

(b) 7-level midtread

Figure 4-1: Transfer characteristic of quantizers

equal or larger than its Nyquist-rate fN=2fB, the spectrum of the discrete-time sample train consists of periodic spectrum replicas of the analog signal. Without aliasing, the original baseband spectrum can be reconstructed by applying a low-pass filter. Since this discrete-time signal is still continuous in amplitude, a quantization procedure is necessary to finally convert it into a digital signal which is represented by a finite set of amplitude values. Depending on whether there is a zero output or not, quantizers can be classified as midtread or midriser as shown in Figure 4-1. A quantizer with M levels can also be represented as N bits, where N = log2M. The least significant bit (LSB) of a quantizer with maximum and minimum output values of Vm and -Vm is

VLSB =

2Vm 2V = N m . M −1 2 −1

(4-1)

The maximum non-overloading input amplitude equals Vin ,max = 2 N (VLSB / 2 ) .

(4-2)

60

Figure 4-2: Model for a conventional ADC Figure 4-2: Model for a conventional ADC

For a quantizer, the quantization error between the output and input is confined within the range of [-LSB/2, LSB/2]. In order to simplify analysis, a linearized model for the quantizer can be obtained under the assumption that the error sequence e[n] is a stationary white noise process with a uniform power spectral density (PSD). Consequently, the quantization error or noise power can be calculated as

σ e2 =

2 VLSB . 12

(4-3)

Since the above white noise power is folded into baseband [-fS/2, fS/2], and repeats at multiples of fS due to the sampling, the PSD of the quantization noise is

Se ( f ) =

2 VLSB 1 . 12 f S

(4-4)

With the use of an anti-aliasing filter at the input to limit its input band, the model for a conventional ADC is illustrated in Figure 4-2. When the sampling frequency of an ADC is close to the fN=2fB, it is classified as a Nyquist-rate ADC. The dynamic range (DR) of an ADC is defined as the ratio of the signal power of the maximum sinusoid input and that of the input resulting in a SNR of 1. The dynamic range for a Nyquist rate ADC can be found with Eq. (4-2) and (4-3) as

61

Figure 4-3: Spectral Illustration for a Nyquist rate ADC and an Oversampling ADC

⎛ Vin2,max 2 ⎞ ⎛ 3 2N ⎞ DR = 10 log10 ⎜⎜ ⎟⎟ = 10 log10 ⎜ 2 ⎟ = 1.76 + 6.02 N [dB] . 2 ⎝2 ⎠ ⎝ σe ⎠ 4.1.2

(4-5)

Oversampling ADC

Compared with the Nyquist rate ADC, an oversampling ADC operates at a sampling frequency much higher than the Nyquist rate. Defining the oversampling ratio (OSR) as the ratio between the sampling requency and the Nyquist rate, or mathematically

OSR =

fS f = S . 2 fB fN

(4-6)

The spectral illustration for a Nyquist rate ADC and an oversampling ADC are shown in Figure 4-3. Since the quantization noise can be modeled as white noise and its power is constant for the band [-fS/2, fS/2] as expressed by (4-3), the oversampling

62

ADC has a much smaller quantization noise power when a proper digital filter is employed following the quantizer. Therefore its output in-band quantization noise power is

σ e2,OSR =

2 VLSB . 12OSR

(4-7)

The dynamic range of an oversampling ADC can be obtained as

DR = 1.76 + 6.02 N + 10 log10 OSR[dB] .

(4-8)

Equation (4-8) indicates that every doubling of the OSR increases the dynamic range by 3dB or 0.5 bit. This is one benefit of the oversampling ADC. On the other hand, since the spectrum between fB and fS-fB does not alias in the signal band, the transition of the analog anti-aliasing filter from pass to stop band can be much smoother than that in the Nyquist-rate ADC case. This relaxed specification for the anti-aliasing filter is another advantage. Nevertheless, the enhancement of dynamic range in a pure oversampling ADC is achieved at the cost of increased power consumption or reduced conversion rate. The trade-offs are not very power-efficient and this makes the pure oversampling ADCs less attractive in practive.

4.2

Basics of Delta-Sigma ADCs The Delta-Sigma (ΔΣ) ADC is an important category of oversampling ADCs

which conducts the noise shaping function, i.e., shapes the quantization noise out of the signal band. It is a very attractive technique to implement high-resolution analog-to-digital or digital-to-analog converters in low-cost CMOS processes, since circuit errors and noise in signal-bands can be suppressed or shaped by the loop-filter

63

Figure 4-4: ΔΣ ADC Block Diagram

employed. The block diagram of a ΔΣ ADC is illustrated in Figure 4-4. A discrete-time ΔΣ modulator implemented by switched-capacitor technique is adopted in this ADC. An anti-aliasing filter and a sample-and-hold stage are present preceding the ΔΣ modulator. The quantizer in the modulator has a low resolution (usually from 1- to 3-bit). With a proper low-pass loop filter H(z) and the feedback path in the modulator, quantization noise sees a high-pass transfer function and thus can be shaped to high frequencies. The modulator is followed by a decimation filter consisting of a digital low-pass filter and a down-sampling-by-OSR stage. The decimation filter has a cut-off frequency of fB and it filters out the high frequency noise and then high-resolution data-conversion is achieved. Nyquist rate high-resolution output is recovered by the down-sampling stage. Replacing the quantizer with the linear white noise model, and assuming it has a unity-gain, a linearized ΔΣ modulator model can be obtained as shown in Figure 4-5. This approximation is good for multi-bit quantizers. For a single-bit quantizer in a ΔΣ modulator, its gain is related to the scaling factor of the last integrator [51]. The simplest loop filter that fits the above requirement, i.e., passing the input signal and

64

Figure 4-5: Linearized model of a ΔΣ modulator

shaping quantization noise, is an integrator, which has a transfer function as

H ( z) =

z −1 . 1 − z −1

(4-9)

The transfer function of this system can be found as

Y ( z) =

H ( z) 1 X ( z) + E ( z) . 1+ H ( z) 1+ H ( z)

(4-10)

Define signal transfer function (STF) and noise transfer function (NTF) as

STF ( z ) =

H ( z) , 1+ H ( z)

(4-11)

NTF ( z ) =

1 . 1+ H ( z )

(4-12)

With Eq. (4-9) as the loop filter, we have STF(z) = z-1 and NTF(z) = 1-z-1. The transfer function for the first-order ΔΣ modulator can be obtained as

Y ( z ) = z −1 X ( z ) + (1 − z −1 ) E ( z ) .

(4-13)

It can be observed that the STF is simply a delay and the NTF is a differentiator which has a high pass magnitude response. Applying

z = e j 2π f / f S ,

(4-14)

65

Figure 4-6: First-order ΔΣ noise shaping

the shaped quantization noise PSD can be analyzed as S ( f ) = Se ( f ) NTF ( f ) = Se ( f ) 1 − e − j 2π f / f S 2

2

= 4 Se ( f ) sin 2 (π f / f S ) . (4-15)

The effect of first-order ΔΣ noise shaping is plotted in Figure 4-6. Since most of the quantization noise is pushed outside the signal band, the post-filtered in-band noise is reduced significantly compared with that in a pure oversampling ADC. The in-band quantization noise power for the first-order ΔΣ modulator is calculated as

Pe1 = ∫

fB

− fB

Se ( f ) NTF ( f )

2

2 VLSB df = ∫ − f B 12 f S fB

⎛ ⎛π f ⎜⎜ 2sin ⎜ ⎝ fS ⎝

2

2 ⎞⎞ VLSB π2 ≈ , (4-16) df ⎟ ⎟⎟ 36 ⋅ OSR 3 ⎠⎠

where sin(πf/fS) is approximated as πf/fS since OSR>>1. The dynamic range is obtained as

DR1 = 6.02 N − 3.41 + 30 log10 OSR[dB ] .

(4-17)

We see that doubling the OSR gives a DR improvement of 9dB or 1.5 bits for this first-order ΔΣ modulator. Compared with the case in a pure oversampling ADC, the noise shaping technique enhances circuit performance greatly. In spite of its simplicity, first-order ΔΣ modulator is rarely used in practice since

66

it suffers from the limit cycle tones caused by quantizer nonlinearity [52]. In the above analysis, the quantizer is modeled as a linear white noise source. However, in reality, the quantization noise is correlated with the input signal, and this correlation is not embodied in the white noise model. Unfortunately, in the first-order ΔΣ modulator, the correlation is quite strong and the modulator output usually contains significant tone structures if the modulator input is not a random signal or no sufficient randomization is introduced into the circuit. This problem becomes more pronounced if a DC input signal is fed into the modulator. The limit cycle tones can be suppressed by adding a (pseudo) random dither signal to the input of the quantizer or to the input of the modulator [52]. When the dither signal is introduced at the modulator input, it has to be sufficiently small in order to keep the SNR degradation at a tolerable level since noise at the modulator input is shaped by the loop. On the other hand, in higher-order ΔΣ modulators, the input signal and the quantizer noise samples are less correlated compared with the case in the first-order modulator and the limit cycle problem is relieved. Although the theoretical prediction of the limit cycle problem in higher order ΔΣ modulators depends on circuit topology and is quite complicated [53][54], it can usually be investigated by behavioral simulations. Moreover, the tones are usually located outside the signal band in higher-order ΔΣ modulators and can be readily suppressed by the decimation filter. In digital ΔΣ modulators for fractional-N PLLs, this problem is of more concern since it can influence the out of band noise performance of a PLL significantly and extra care should be taken in such an application.

67

4.3

Higher-Order Delta-Sigma ADCs The block diagram for a second-order ΔΣ modulator is illustrated in Figure 4-7.

The transfer function of this second-order modulator is found as Y ( z ) = STF2 ( z ) X ( z ) + NTF2 ( z ) E ( z ) ,

(4-18)

where STF(z) = z-1 and NTF(z) = (1-z-1)2. The square of the NTF magnitude is found as

NTF2 ( f ) = ⎡⎣ 2sin (π f / f S ) ⎤⎦ . 2

4

(4-19)

By taking integral of the filtered noise over the signal band and using sin(πf/fS) ≈ πf/fS for OSR>>1, the in-band noise power can be found approximately as 2 VLSB π4 Pe 2 ≈ , 60 ⋅ OSR 5

(4-20)

The dynamic range of this second-order ΔΣ modulator is then found to be

DR2 = 6.02 N − 11.14 + 50 log10 OSR[dB] .

(4-21)

It is shown here that the second-order modulator has a dynamic range gain of 15dB or 2.5bits/octave. This example demonstrates that by applying a higher order loop filter in a ΔΣ modulator, more aggressive noise shaping is achieved and DR/SNR of the

Figure 4-7: Second-order ΔΣ modulator block diagram

68

ADC can be improved more significantly compared with the case in the first-order ΔΣ modulator. Moreover, as discussed immediately above, the limit-cycle tones are also relieved due to less correlation between the quantization noise and the modulator input signal in a higher order ΔΣ modulator. Therefore, higher order modulators are more attractive and practical for implementation. Inferred from the above analysis on first- and second-order ΔΣ modulators, ideally, an Mth-order modulator would have an NTF of an Mth-order differentiator or NTFM(z)=(1-z-1)M. Then the gain of dynamic range would be (6.02M+3) dB/octave and high resolution ADCs can be implemented in this way under a reasonable OSR and power consumption. In practice, there are at least two ways to build a higher order ΔΣ modulator. The first one is to use the single-loop topology. In a single-loop modulator, though the second-order modulators are intrinsically stable, the out-of-band gain of the higher order NTF increases rapidly resulting in a source of instability. To guarantee system stability within a specific input amplitude range, the ideal NTFs mentioned above is not a valid choice for single-loop modulators with orders equal or greater than three. Therefore, the noise shaping effect is compromised for loop stability. In order to overcome this instability issue and also the SNR degradation, a higher order ΔΣ modulator can also be designed using the cascade of intrinsically stable first- and second-order modulators which is known as the Multi-stAge noise Shaping (MASH) structure. While an ideal higher-order NTF may be achievable, the cascade/MASH topology is more sensitive to circuit imperfections such as finite amplifier DC gain, limited amplifier bandwidth and non-zero switch

69

resistance. Moreover, its performance depends on accurate circuitry matching which is in contradiction with the aim of ΔΣ modulation to implement high-resolution data conversion with circuits of low-accuracy. With these implementation difficulties in the MASH architecture, the single-loop topology is usually more favorable in spite of its instability. The details on the two ΔΣ modulator structures and the stability issues of single-loop modulators are discussed below. 4.3.1

Single-Loop ΔΣ modulators with Distributed Feedback Paths

Single-loop ΔΣ modulators contain only one quantizer. Figure 4-8 shows the block diagram of an Mth-order single-loop ΔΣ modulator with distributed feedback paths. It incorporates multiple integrators in the forward path of the modulator loop. A feedback path exists for each integrator and integrators are weighted by coefficients ai, i=1, …, M. For the modulator shown in Figure 4-8, with the unity-gain white noise quantizer model, the STF and NTF are found to be

I M ( z ) ⋅ ∏ i =1 ai M

STF ( z ) =

1 + ∑ i =1 ∏ j =i a j I M −i +1 ( z ) M

M

,

(4-22)

Figure 4-8: Block diagram for an Mth-order ΔΣ modulator with distributed feedback

70

NTF ( z ) =

1 1 + ∑ i =1 ∏ j =i a j I M −i +1 ( z ) M

M

,

(4-23)

where I(z)=z-1/(1-z-1). At low frequencies, the noise shaping behavior is dominated by the largest term of the denominator in Eq. (4-23) and the magnitude of the NTF can be approximated as

NTF ( z ) ≈

1 − z −1

∏

M

M

a i =1 i

.

(4-24)

The in-band noise reduces exponentially with the increase of OSR. For stability reasons, some or all of the scaling coefficients ai are less than one; therefore the denominator of Eq. (4-24) is smaller than one. Quantization noise shaping effect is thus degraded and noise power is scaled up by 1/( ∏ i =1 ai ) compared with that in the M

ideal Mth-order differentiator NTF. This distributed feedback topology and its variations are widely used in practice. In Figure 4-8, to obtain simple general mathematic expressions for the STF and NTF, all the integrators carry unit-delays. However, all or some of the integrators can be replaced with delay-free integrators as long as there is at least one unit-delay in the loop for the sake of causality. And the STF and NTF should be recalculated accordingly. The block diagram of a fourth-order single-loop ΔΣ modulator with all delay-free integrators is demonstrated in Figure 4-9. The delay element in the outmost feedback path guarantees the system is causal. The NTF is found to be NTF ( z ) 4th =

(1 − z −1 ) 4 1 − (4 − a1a2 a3a4 − a2 a3 a4 − a3a4 − a4 ) z + (6 − a2 a3a4 − 2a3a4 − 3a4 ) z −2 − (4 − a3 a4 − 3a4 ) z −3 + (1 − a4 ) z −4 −1

(4-25)

71

Figure 4-9: Block diagram for a 4th-order ΔΣ modulator with weighted feedback and delay-free integrators

By removing one or two integrators in this modulator, a third- (or second-) order ΔΣ modulator can be obtained. Interestingly, the NTFs for the third- and second-order modulator are NTF ( z )3rd =

NTF ( z ) 2 nd =

NTF ( z ) 4th

a 4 =1

,

(4-26)

a 3=1

.

(4-27)

(1 − z −1 ) NTF ( z )3rd −1

(1 − z )

Besides the SNR degradation, another drawback of this modulator topology is that the outputs of the integrators track input signals and this can result in large voltage swings which overload the quantizer. To understand this, we see that the input to an integrator should be zero over time, so that the DAC output tracks the modulator input signal closely. Since the inputs of integrators are the difference between the feedback DAC signal and the output from the preceding integrator, the integrator outputs consequently contain significant amount of input signals. On one hand, this requires the active components in the integrators to have large output swings. On the other hand, to avoid quantizer overloading for large input signals, proper dynamic-range scaling should be carried out. This feedback only topology also lacks flexibility for the selection of the STF.

72

Figure 4-10: Block diagram for a Mth-order ΔΣ modulator with weighted feedback and distributed feedforward

Comparing Eq. (4-22) with Eq. (4-23), once the NTF is optimized and settled, the STF would be fixed. In order to optimize the STF as well, feed-forward paths can be added as shown in Figure 4-10. 4.3.2

Single-Loop ΔΣ modulators with Feed-Forward Paths

It is discussed in the previous section that the feed-back topology requires that the amplifiers have a large output swing. However, in deep-submicron CMOS technologies, the amplifier output swing is often limited by the small power supply voltages and the relatively larger transistor threshold. Therefore, it is worthwhile to investigate ΔΣ topologies suitable for deep-submicron processes. A ΔΣ modulator employing a single feedback path and weighted feed-forward paths is illustrated in Figure 4-11. Using the unity-gain white noise quantizer model, the STF and NTF are found to be

∑ a STF ( z ) = 1+ ∑ a M

i =1 M − i +1 M i =1

Ii (z)

i M −i +1 I ( z )

,

(4-28)

73

Figure 4-11: Block diagram for a Mth-order ΔΣ modulator with weighted feed-forward

NTF ( z ) =

1 1 + ∑ i =1 aM −i +1 I i ( z ) M

,

(4-29)

The expressions for the STF and NTF are similar to their counterparts in a distributed feedback modulator and the quantization noise shaping performance is substantially the same. In order to investigate the output swings of integrators, third-order ΔΣ modulators with different single-loop topologies are designed and behavior simulations in MATLAB are carried out. For the purpose of comparison, integrator output swings versus input signal level for a weighted feed-forward modulator and a distributed feedback modulator are plotted in Figure 4-12 and Figure 4-13, respectively. For the feed-forward topology, the outputs of the first two integrators remain small and constant over the entire input range. The output of the last integrator increases with inputs greater than about -30 dBFS but it is still smaller than that in the feedback topology. As long as quantizer overloading is avoided, errors at the output of the last integrator are shaped the same way as the quantization noise.

74

Figure 4-12: Output swing of integrators in feed-forward topology

Figure 4-13: Output swing of integrators in feedback topology

75

Moreover, if necessary, a feed-forward path from the modulator input to the summation node preceding the quantizer can decouple the correlation between the input and the output of the last integrator. In the feedback topology, output swings of all the three integrators are heavily correlated with the input signal. Their amplitudes increase sharply for a large input signal levels. Especially for the last integrator, when the input level is -3 dBFS, its output swing already occupies the full scale. Since the errors at the first and second integrator output nodes are less shaped (first-order and second-order, respectively), the integrators should have sufficient output swing capability. The difference mentioned above makes the feed-forward topology more attractive in deep-submicron CMOS technologies where amplifier swings are relatively small. The magnitude responses of STF and NTF of a sample multi-bit feed-forward 3rd-order modulator are plotted in Figure 4-14 and Figure 4-15. It can be noticed that magnitude peaking occurs for the STF. This is a common phenomenon in the feed-forward topology and care should be taken when designing the modulator to avoid STF magnitude peaking in signal band. Otherwise, it can cause nonlinearities in the quantizer. 4.3.3

Stability of single loop ΔΣ modulators

As discussed earlier, single-loop ΔΣ modulators with orders higher than two suffer from instability. The stability issue is of primary priority when designing a single-loop modulator and should be investigated exhaustively. Several methods which can be used to provide insights for a stable loop design are discussed below.

76

Figure 4-14 STF magnitude response of a 3rd-order modulator

Figure 4-15: NTF magnitude response of a 3rd-order modulator

77

The stability of a linear feedback system is determined by its loop gain, or H(z) in Eq. (4-10). However, the ΔΣ modulators are not linear systems and nonlinearities have strong effects on their stability. For example, if the loop filter is not designed properly, internal signals could grow so large to saturate the amplifiers. Additionally, in previous analysis, the quantizer is modeled as a linear unity-gain white noise source for simplicity. In reality, this is not true and the gain of the quantizer varies under different conditions. For example, a one-bit (2-level) quantizer can have an arbitrary gain since its output is simply the sign of the input signal. Simulations for some specific ΔΣ modulators indicate that for moderate input signals, the quantizer gain is related to the scaling coefficient of the last integrator and their product is a constant. For a multi-bit quantizer, the unity gain is well defined by its transfer characteristic for inputs with moderate amplitudes. However, if the input signal is so small that the output changes between ±LSB only, the gain of the quantizer can be larger than 1. On the other hand, if the quantizer is overloaded, the gain becomes

Figure 4-16: Block diagram for an Mth-order ΔΣ modulator with weighted feed-forward

78

smaller than 1. The variations of quantizer gain are closely related to the loop stability. In the following analysis, kQ is used to denote the quantizer gain. In a well-designed modulator, no severe internal signal saturation should occur, and instability is mainly caused by the overloading of the quantizer. The input of the quantizer is found as Qin ( z ) = STF ( z ) X ( z ) + ( NTF ( z ) − 1) E ( z ) .

(4-30)

Since the magnitude response of the STF is approximately 1 within the signal band and no large signal is present out of the signal band at the input node of the modulator, the stability of the modulator is primarily determined by the NTF and the amplitude of the quantization error which is determined by the resolution or the number of bits of the quantizer. A 3rd-order ΔΣ modulator with weighted feed-forward paths is taken as the example for loop stability analysis. The topology of the modulator is illustrated in Figure 4-16. It consists of one delay-free integrator and two unit-delay integrators and scaling coefficients a1, a2, and a3. The NTF of this integrator are found as

NTF ( z ) =

(1 − z )

−1 3

1 − ⎡⎣3 − ( a1 + a2 ) kQ ⎤⎦ z −1 + ⎡⎣3 − ( 2a1 + a2 − a3 ) kQ ⎤⎦ z −2 − (1 − a1kQ ) z −3

. (4-31)

The NTF root-locus of the third-order modulator shown in Figure 4-16 is plotted in Figure 4-17 for different kQ values from 0 to infinity. The moving of the three pole locations with kQ forms three curves. Another root-locus plot of a modulator with different scaling coefficients is illustrated in Figure 4-18 for the purpose of comparison.

79

Figure 4-17 Root-locus of a 3rd-order modulator with a1=1, a2=1, a3=0.5

Figure 4-18 Root-locus of a 3rd-order modulator with a1=1, a2=1, a3=1.5

80

The loci of three poles are shown in the plots above. Though the real pole approaches -∞ with the increase of kQ in the plots, it does not contribute to instability in reality since the instantaneous kQ will decrease when the quantizer is overloaded and this will pull the pole back into the unit circle. This is known as a stable limit cycle. In Figure 4-17 and 4-18, the term kQ,crit is the critical gain. If the quantizer has a gain larger than kQ,crit, all the three poles are located inside the unit circle. According to the linear control theory, then the system is stable. In the example modulators, the kQ,crit is found to be 0.5 and 1.5 for a3=0.5 and a3=1.5, respectively. It is obvious that the stable input range for the modulator with a3=0.5 is much larger. With an assumption that a multi-bit quantizer is used, the modulator with a3=1.5 will obviously fail, because kQ=1 for a multi-bit quantizer. On the contrary, the modulator with a3=0.5 will still be stable even if light overloading happens. Since ΔΣ modulators are nonlinear systems but the root-locus analysis is based on linear control theories, simulations should be carried out as the final verification step for loop stability. The above analysis explains the effect of variable quantizer gain on loop stability and gives a general idea that kQ,crit should be kept low for a relatively large stable input range. However, a small kQ,crit may compromise the noise shaping performance of the modulator and degrade the otherwise achievable SNR. Also, specific NTF requirements are not given to facilitate loop implementation. In practice, based on extensive simulations and implementations of modulators with different topologies, the Lee Criterion is widely accepted as a rule of thumb, i.e., a single-bit ΔΣ modulator is likely to be stable if its NTF has a maximum magnitude

81

less than 1.5 [55]. In [56], it is proposed that for modulators with 2-bit, 3-bit and 4bit quantizers, the maximum NTF magnitude can be set at 2.5, 3.5, and 5 respectively. These values give both a reasonable stable input range (80% full scale) and good noise shaping effect. Other techniques can also be used to assist the design of a stable higher order ΔΣ modulator. In [57], a more elaborate and complicated modulator model with nonlinear quantizer gain gives good prediction for its stable input range. Some cook-book like design procedures are also available in [52]. However, when designing and optimizing a specific modulator, extensive behavior simulations are still necessary for verification purpose before implementation. 4.3.4

MASH modulators

As discussed before, higher order ΔΣ modulators can be implemented with the

Figure 4-19 A two-stage general structure for a MASH modulator

82

ideal NTF using the MASH topology. The basic concept for a MASH modulator is illustrated in Figure 4-19. The output of the first stage is given by Y1 ( z ) = STF1 ( z ) X ( z ) + NTF1 ( z ) E1 ( z ) ,

(4-32)

where STF1 and NTF1 are the signal and noise transfer functions of the first stage, respectively. The input to the second stage is the difference between the quantizer input and output, which is equal to –e1. Therefore the output of the second stage is

Y2 ( z ) = STF2 ( z ) ⎡⎣ − E1 ( z ) ⎤⎦ + NTF2 ( z ) Y2 ( z ) ,

(4-33)

where STF2 and NTF2 are the signal and noise transfer functions of the second stage. The digital filters DF1 and DF2 are designed such that the quantization error of the first stage (e1) is cancelled in the final output. Consequently, the following condition should be satisfied NTF1 ( z ) DF1 ( z ) − STF2 ( z ) DF2 ( z ) = 0 .

(4-34)

The widely adopted solutions are DF1 ( z ) = STF2 ( z ) ,

(4-35)

DF2 ( z ) = NTF1 ( z ) .

(4-36)

Typically, both of the two stages are second-order modulators, and this yields STF1 ( z ) = STF2 ( z ) = z −1 ,

(4-37)

NTF1 ( z ) = NTF2 ( z ) = (1 − z −1 ) . 2

Then the final output is given by

(4-38)

83

Y1 ( z ) = z −2 X ( z ) + (1 − z −1 ) E1 ( z ) . 4

(4-38)

A fourth-order noise shaping NTF is obtained while the stability of this modulator is that of a second-order one and the loop is intrinsically stable. Even higher order modulator can be obtained by adding additional stages without the stability concern as shown in the single-loop modulators. Nonetheless, since the input to the second (next) stage is obtained using analog subtraction and noise cancellation depends on accurate matching of analog filters, the quantization noise cannot be canceled ideally. In other words, circuit imperfection introduces noise leakage into the next stage. Unfortunately, the noise leakage is only shaped by a low order NTF and this phenomenon may result in serious deterioration of the overall modulator performance. In real circuits, the actual coefficients of a filter are influenced by the matching of passive elements, the finite gain and the bandwidth of the active ones. Thus MASH modulators are very sensitive to variations of the above factors. For this reason, the MASH structure is not used in our design and it is not the emphasis of our work. 4.3.5

Techniques to enhance ΔΣ modulator performance

Using Eq. (4-24), the in-band noise of an Mth order ΔΣ modulator can be obtained as

σ e2, M =

2 VLSB π 2M 1 . M 12 ( 2M + 1) ∏ ai2 OSR 2 M +1

(4-39)

i =1

Therefore several ways to reduce in-band noise can be obtained from the above equation. The first is to use a larger M or higher order modulator. If OSR is much larger

84

than π, more quantization noise may be shaped out of the signal band with a larger M. Nevertheless, higher order single-loop modulator suffers from the instability issue mentioned, and in order to maintain a reasonable stable input range, the product of the scaling coefficients is usually less than one and may be reduced dramatically in higher order modulators. Thus, the performance enhancement may not be significant using this method for an already high order loop filter. Second, in-band noise can be reduced by increasing the OSR. It is straightforward that modulator SNR increases rapidly with the OSR. Also, it is easier to construct the anti-aliasing filter for a larger OSR since the transition band can take a larger frequency range. However, the increase in OSR is equivalent to increase in amplifier bandwidth. In CMOS technologies, when a transistor operates in saturation region, its bandwidth and power consumption have a square law relationship, i.e., in order to increase its bandwidth to twice the original one, its power consumption should be approximately four times the original. Therefore, this method may result in a design which is not power efficient. Moreover, operating at high sampling frequency, switched-capacitor may suffer from performance deterioration due to strict clock requirement and the finite switch resistance. Third, in the above discussed modulator topologies, the zeros of the modulator NTF are all placed at z=1. However, a better noise shaping effect may be achieved by optimally spreading zero locations on the unit circle. This can be done by adding local feedback paths in the loop filter. In order to show this, optimal zero locations for a third-order modulator is found exemplary. For a third-order modulator, its NTF zero

85

locations are z=1, z=e±jα, and it has a NTF given by

(1 − z )(1 − e NTF ( z ) =

α j −1

−1

z

A( z)

)(1 − e

−α j

z −1 )

,

(4-40)

where A(z) is the denominator of the NTF. For signal band with a large OSR, the magnitude of the NTF is

ω (ω 2 − α 2 )

NTF ( z ) in −band ≈

A ( z = 1)

.

(4-41)

The optimal zero locations yield minimum in-band noise. Therefore αopt can be found by minimizing I (α ) = ∫

ωB

0

(ω (ω

2

)

2

− α 2 ) dω .

(4-42)

Differentiating I(α) with respect to α and equating the result to zero,

α opt = ±

15 ωB ≈ ±0.77ωB . 5

(4-43)

Assuming the quantization noise is white and NTF poles have little effect on the in-band noise, the SNR improves by 10log10(I(0)/I(αopt))=8dB. It can be observed that with the decrease of OSR, ωB and thus αopt will decrease too. Since significant noise reduction relies on exact placement of zeros, this method may not be precisely realized for a modulator with a small OSR. Another approach to enhance ΔΣ modulator performance is to use a multi-bit quantizer. A multi-bit quanitzer reduces VLSB in Eq. (4-4) and the PSD of the quantization noise is thus reduced by 6dB per extra bit. Also, from Eq. (4-30), a smaller quantizer noise can also enhance the stability of the modulator. Therefore, a

86

more aggressive NTF with larger out-of-band gain can be employed as discussed above to improve noise shaping effect and reduce in-band quantization noise further. Nevertheless, when designing a ΔΣ ADC with a multi-bit quantizer, a highly-linear feedback DAC matching the overall ADC accuracy is required, because the feedback signal is subtracted from the analog input directly and no noise-shaping is carried out. The feedback DAC is the major bottleneck when designing a multi-bit ΔΣ ADC, since it is not a trivial task to design a highly-linear (>14bit) DAC in CMOS VLSI technologies with the presence of inherent component mismatch. In the following chapter, a nonlinearity-suppressed DAC is proposed and a multi-bit ΔΣ modulator is designed with the proposed DAC.

4.4

Thermal Noise in ΔΣ ADCs In a proper designed ΔΣ ADC, shaped quantization noise may take only a small

fraction of the total noise budget. Thermal noise usually becomes the dominant noise source and it is investigated in the following example specifically. The ΔΣ modulator shown in Figure 4-16 is plotted in Figure 4-20 with the noise sources indicated. Assuming conventional OTA integrators are used, using the integrator noise model derived in Chapter 2, seven noise sources are shown in the figure. Vni1, Vni2 and Vni3 are the input-referred thermal noise at the inputs of the integrators. Vno1, Vno2 and Vno3 are the opamp noises not included in the input-referred calculation but present at the integrator outputs. Vnq represents the total thermal noise present immediately preceding the quantizer. Due to the under-sampling, the spectrum of each noise source is nearly white as

87

Figure 4-20: Noise analysis for an Mth-order ΔΣ modulator with weighted feed-forward

discussed in Chapter 2. Their single-sided PSDs are given by Six ,ox =

Vnix2 ,nox fS / 2

,

(4-44)

where the integrator input noise power is Vnix2 =

2kT ⎛ 16 ⎞ ⎜1 + ⎟ , x = 1, 2,3 , CSx ⎝ 1 + g mx Rx ⎠

(4-45)

and the output noise power is 2 Vnox =

4kT , x = 1, 2,3 . 3CLx

(4-46)

Assuming for the quantizer, gmQRQ>>1, and the three input branches have scaling coefficients as shown in Figure 4-20, and the unit capacitor is Cf, then the total input noise for the quantizer is VnQ2 =

2kT ( 2.5C f

( 2.5C ) f

2

)=

2kT . 2.5C f

(4-47)

Each noise source has a specific transfer function and they are evaluated separately. Assuming the quantizer is a unity-gain white noise source, the NTFs are

88

Figure 4-21 NTFs at different nodes for a 3rd-order ΔΣ modulator

found to be NTFi1 ( z ) = STF ( z ) =

NTFo1 ( z )

2 z −1 − 2.5 z −2 + z −3 , 1 − z −1 + 0.5 z −2

(1 − z )( 2 − 2.5 z = −1

−1

+ z −2 )

1 − z −1 + 0.5 z −2

,

(4-48)

(4-49)

NTFi 2 ( z )

(1 − z )(1 − 0.5 z ) , =

(4-50)

NTFo 2 ( z )

(1 − z ) (1 − 0.5z ) , =

(4-51)

NTFi 3 ( z )

(1 − z ) =

(4-52)

−1

−1

1 − z −1 + 0.5 z −2 −1 2

−1

1 − z −1 + 0.5 z −2 −1 2

0.5 z −1

1 − z −1 + 0.5 z −2

,

89

(1 − z )

−1 3

NTFo 3 ( z ) = NTFq ( z ) = NTF ( z ) =

1 − z −1 + 0.5 z −2

.

(4-53)

The magnitude response of the above noise transfer functions are plotted in Figure 4-21. It is clear that vni1 is not shaped; vno1 and vni2 are first-order shaped; vno2 and vni3 are second-order shaped; vno3 and vnq are third-order shaped. With the PSDs and NTFs for thermal noise sources, the in-band thermal noise power can be found by applying integral from DC to fB=fS/(2OSR). With OSR>>1, the results are f S / ( 2 OSR )

Pn ,i1 = ∫

2

Si1 NTFi1 df ≈

0

f S / ( 2 OSR )

Pn ,o1 = ∫

2

So1 NTFo1 df ≈

0

f S / ( 2 OSR )

Pn ,i 2 = ∫

2

Si 2 NTFi 2 df ≈

0

f S / ( 2 OSR )

Pn ,o 2 = ∫

0

f S / ( 2 OSR )

Pn ,i 3 = ∫

Pn ,o 3 = ∫

f S / ( 2 OSR )

0

Pn ,q = ∫

f S / ( 2 OSR )

0

2

2

(4-55)

3.3 ⋅ vni2 2 . OSR 3

(4-56)

2

2

2 19.5 ⋅ vno 2 . OSR 5

19.5 ⋅ vni2 3 . df ≈ OSR 5

So 3 NTFo 3 df ≈

Sq NTFq df ≈

(4-54)

2 3.3 ⋅ vno 1 . 3 OSR

So 2 NTFo 2 df ≈

Si 3 NTFi 3

0

vni2 1 . OSR

2 549.4 ⋅ vno 3 . 7 OSR

549.4 ⋅ vni2 1 . OSR 7

(4-57)

(4-58)

(4-59)

(4-60)

With OSR =40, it is obvious that the first term dominates the total thermal noise and the thermal noise power is about

90

Pn ≈ Pn ,i1 =

2kT ⎛ 1/ 6 ⎞ −2 kT . ⎜1 + ⎟ ≈ 5.8 × 10 OSR ⋅ CS 1 ⎝ 1 + g m1 R1 ⎠ CS 1

(4-61)

The thermal noise in a ΔΣ modulator is determined by the sampling capacitor of the first integrator. Therefore, when the noise budget is settled for an ADC design, its capacitor size can be found accordingly.

91

Chapter 5 PLL Design with a Low-Power Active Switched-Capacitor Loop Filter In this chapter, a low-power switched-capacitor loop filter is proposed for PLLs. The design methodology and testing results of a high-performance PLL prototype with this loop filter in a 0.18μm CMOS process is presented. Section 5.1 reviews existing loop filter implementation topologies and in Section 5.2, the proposed loop filter structure is explained in details. Section 5.3 describes the design of other blocks of the PLL. Measurement results are provided in Section 5.4.

5.1

PLL Loop Filters in literatures The basic passive RC loop filter of a PLL has been discussed in Chapter 3. In

spite of its simplicity, the large filter capacitor required is usually an integration bottleneck. Many different loop filter structures for CMOS PLLs are reported. They can be classified into three general categories: active continuous-time (CT) loop filters, passive switched-capacitor loop filters and hybrid loop filters. 5.1.1

Active Continuous-Time Loop Filter

With the use of active filters, the origin pole and the stabilizing zero as required for a Type II PLL can be realized separately and it is known as a dual path loop filter

92

[58]-[61]. In this configuration, two separate charge pumps provide the proper currents to each path and the capacitor ratio requirement in a passive RC loop filter now can be converted into that between the two charge pump currents, which is simple to implement in CMOS technologies. The loop filters in [59] and [60] are illustrated in Figure 5-1 and Figure 5-2, respectively. The two paths can be identified as an integration path and a proportional path. In order to investigate the principle of this approach, the transfer function of the third-order dual-path loop filter shown in Figure 5-1 can be found as Vsum = Vz − V p =

BI CP R p I CP I 1 + sR p ( C p + BCz ) , + = CP sCz 1 + sR p C p sCz 1 + sR p C p VCtrl =

Vsum . 1 + sR3C3

(5-1)

(5-2)

The stabilizing zero is located at

ωz =

1 . R p ( BCz + C p )

(5-3)

It can be observed that the scaling up of the proportional path current is equivalent to scaling up the integration capacitor size. With the scaling factor B, the size of Cz becomes more flexible. Similar results can be obtained for the loop filter in Figure 5-2, where only one Opamp is used. The dual-path active loop filter has several disadvantages. Compared with the passive RC loop filter, obviously, extra power is consumed and extra noise from the active elements is introduced. Also, voltage ripple problem caused by current mismatch are not improved. Moreover, the integration path current could be very

93

Figure 5-1: Dual-path loop filter 1

Figure 5-2: Dual-path loop filter 2

small for a large B and it could contribute significant noise. 5.1.2

Passive Switched-Capacitor Loop Filter

CMOS switched-capacitor (SC) or discrete-time circuits offer high accuracy for analog signal processing. This technique can surely be used to design loop-filters for PLLs. As discussed in Chapter 2, in an active SC filter, the amplifier bandwidth must be sufficient large to assure adequate settling accuracy in SC circuits. For a

94

conventional OTA SC integrator, to achieve a settling accuracy of 0.1%, the unity gain frequency of the amplifier should be at least 2.23/β times the sampling frequency, where β is the feedback coefficient. Therefore, even for medium frequency operations, the OTA can be power hungry. To avoid high power consumption, simple passive SC filters can be used as demonstrated in [61][62]. The conceptual schematic of the loop filter along with the single-polarity charge pump employed is illustrated in Figure 5-3. Assuming the timing diagram of the reference signal fref and feedback signal fdiv is as shown in Figure 5-3, the clock timing schemes for each switch are plotted accordingly. It can be identified that one operation cycle of this circuit consists of three phases. First, the reset switch Φrst discharge Cs. Second, Φs is on and Cs is charged by a constant current ICP for a period proportional to the phase difference of fref and fdiv. Third, Φh is turned on and the charge is redistributed between the two capacitors. Since a specific phase error corresponds to a specific VCO control voltage or output frequency in this

Figure 5-3: Passive switched-capacitor loop filter and its timing scheme

95

configuration, the PLL built with this loop filter is a Type I system. This conclusion can also be obtained by investigating the transfer function of this circuit mathematically as shown below. The z-domain transfer function of the sample and hold circuit is found as [62] H ( z) =

z

−

1 2

C 1 + h (1 − z −1 ) Cs

.

(5-4)

Using z=e

jω f ref

z1/ 2 − z −1/ 2 = 2 j sin

(5-5)

,

ω 2 f ref

(5-6)

,

equation (5-4) can be rearranged as 1

H ( jω ) = cos

ω 2 f ref

⎛ C ⎞ ω + j ⎜1 + 2 h ⎟ sin 2 f ref Cs ⎠ ⎝

.

(5-7)

At frequency much smaller than fref, equation (5-7) can be approximated as H (s) =

1 ⎛ C 2 + Ch 1+ s ⎜ s ⎜ f C ref s ⎝

⎞ ⎟⎟ ⎠

,

(5-8)

where s=jω. This is a simple first-order low pass filter and no DC pole is present. Therefore, the PLL has only one DC pole provided by the VCO and the loop dynamics is Type I. Extra poles can also be added for better filtering if necessary by adding RC networks as shown in [62], where a third order low-pass filter is implemented. Though not pointed out in literatures, it is straightforward that a hold

96

action exists in this SC filter and it has a sinc low-pass response in the frequency domain. Therefore, the complete magnitude and phase response of the filter with the sinc effect added should be investigated carefully during practical design. This structure is simple and does not require large on-chip capacitors. By using the sampling switch, the VCO tuning node is isolated from the charge pump output. Therefore, the steady-state phase error doesn't have a significant effect on the reference-spur performance. Also, the switched-capacitor pole location is well defined by reference frequency and capacitor ratio. However, as addressed earlier, a PLL with this loop filter is a Type I system. It suffers from the limited lock-in range problem. Thus in the reported works [61][62], it is mentioned that a VCO with digital coarse tuning should be used and this increases circuit complexity. Also, because there is only one origin zero in the VCO noise transfer function, compared with a Type II PLL, VCO output phase noise has a more strong effect on the in-band phase noise in this Type I PLL [61]. 5.1.3

Hybrid Loop Filter

In the previous section, it is shown that with the switched-capacitor technique, the VCO tuning node is isolated with the charge pump. Considering the fact that the net charge injected into the filter is zero in a locked Type II PLL, charge pump current mismatch will have little effect on spurious performance if the SC technique can be applied. In order to obtain SC Type II dynamics and keep power consumption low, loop filters with a switched-capacitor first stage followed by a continuous-time integrator to provide the origin pole are proposed [64][65]. These loop filters are

97

Figure 5-4: Hybrid loop-filter in [64]

Figure 5-5: Hybrid loop-filter in [65]

illustrated in Figure 5-4 and 5-5, where an OpAmp filter and Gm-C filter are employed, respectively. The active filter in Figure 5-4 provides a DC pole, a stabilizing zero at ωz=1/(RzCz) and an additional pole at ωp=1/(Rz(1/Cz+1/Cp)-1). In Figure 5-5, the output of the loop filter is a current therefore a Current-Controlled-Oscillator (CCO) instead of a VCO should be used in cooperation.

98

The transfer function of the Gm-C filter is found as H Gm ( s ) =

⎛ G I Ctrl 1⎞ = Gm 2 ⎜ m1 + ⎟ , VSH ⎝ sCLF 8 ⎠

(5-9)

A DC pole and a stabilizing zero are obtained. The hybrid loop-filter combines the improved spurious performance of the SC stage and the flexibility of pole/zero locations for active continuous-time filters. However, it dissipates extra power, and moreover, additional noise is introduced by the active components and the resistor in the filter.

5.2

Proposed Low-Power Active Switched-Capacitor Loop Filter

5.2.1

Sub-Threshold Inverter Amplifier

While SC filters are very popular in CMOS analog signal processing for their high accuracy, conventional SC filters consume more power compared to their continuous-time counterparts, because the amplifier bandwidth must be large enough for adequate settling accuracy as discussed above. In our design, to achieve good power-efficiency for an active SC loop filter, sub-threshold inverters are used as the active components instead of the conventional OTAs. In [66], Sigma-Delta data converters designed with class-C inverter SC integrators demonstrates even lower power consumption than continuous-time ones. Low power consumption for the amplifier can be achieved by setting the active-element/inverter power supply voltage close to the sum of NMOS and PMOS thresholds; then, the inverter operates in a class-C manner [66]. Since the transistors in the inverter are in the weak-inversion region most of the time and the static current

99

Figure 5-6: Cascode inverter amplifier

is small, power consumption is reduced significantly. In deep-sub-micron CMOS processes, a moderate gain can be obtained by using the cascode structure as shown in Figure 5-6. The dependency of DC gain and bandwidth of a cascode inverter on its power supply in a 0.18μm CMOS environment is plotted in Figure 5-7. In this CMOS technology, the summation of NMOS and PMOS transistor threshold voltage (Vtn and Vtp) is approximately 1.2V for the minimum 0.18μm channel length, when thick oxide transistors are used to increase the output swing. The figure shows that if the inverter is powered at the boundary of weak and strong inversion, large DC gain and unity gain bandwidth can be obtained simultaneously. High slew rate can also be obtained during the short transition period when one of the inverter transistors is shifted into the strong inversion due to input voltage change. This provides a promising way to build power-efficient SC circuits, especially considering the fact that the output voltage swing of conventional OTAs continues to drop with the advancement of semiconductor technology.

100

Figure 5-7: Relationship of DC gain and bandwidth on an inverter's power supply volatge

In order to investigate the reliability of this sub-threshold inverter amplifier, Monte-Carlo analysis has been carried out in Cadence design environment for this 0.18μm CMOS technology. The distribution histograms for the DC gain and offset voltage with the presence of process variations are depicted in Figure 5-8. Simulation results indicate that the DC gain and offset voltage of the amplifier are normally distributed with standard deviations of 5.8% and 2.2% of their average values, or 2.7dB and 12.1mV, respectively. Therefore, this structure is robust in this commercial CMOS process. In order to increase the output swing of the amplifier which allows for a reduced VCO sensitivity, high-threshold transistors with minimum length 180nm are used for the inverter input transistors and VA is set to 1.2V.

101

Figure 5-8: Distribution of the amplifier’s DC gain and offset voltage with the presence of process variations

5.2.2

Design of the Low-Power Active Switched-Capacitor Loop Filter

The low-power active SC PLL loop filter is illustrated in Figure 5-9, along with a pair of complementary charge pumps. It can be identified that an integration path and a proportional path exist in the loop-filter depicted in Fig 1. The positive charge pump current Iin and CS1 form the integration input and the proportional input comprises the negative charge pump current –Iin, CS2, the source follower and C2. CC is used for auto-zeroing operation to cancel the offset voltage and suppress amplifier's 1/f noise. The timing diagram of different clock phases is shown in Figure 5-10. The clock generator circuit consists of two D flip flops, some simple combination logic cells and delay elements. Its schematic is also depicted in Figure 5-10. The Up and Down

102

Figure 5-9: Proposed switched-capacitor PLL loop filter with complimentary charge pumps

signals are the outputs from a classic phase/frequency detector. The durations of Φ2 and ΦRST are defined by the two delay blocks and they are determined according to the input reference frequency. In the loop filter, when the charge pump current sources are turned on, Φ1 is on, and CS1 and CS2 are charged or discharged accordingly. During the next phase, Φ2 is turned on and the charge is redistributed among the capacitors and a corresponding

Figure 5-10: Clocks generator circuit and a set of example clocks

103

output voltage is established at the inverter output. This voltage is taken as the VCO control voltage when the delayed Φ2 is on. When Φ2 and Φ2d are off, ΦRST is on and CS2 is reset to VREF and the filter is ready for the next update cycle. It is clear from the schematic that one control voltage update cycle consists of different phases. Since the charging phase (Φ1) is isolated from the voltage output phase (Φ2d) and the net charge injected into the loop filter is zero when the loop is locked, the matching requirement on the n and p charge pump current sources is relieved since charge pump current mismatch no longer introduces ripples in the VCO control voltage. With a source follower gain of α, and assuming CS1=CS2=CS, the discrete-time phase to amplifier output voltage transfer function (Φ2d switch not included) of this loop filter is

H ( z ) = K CP

TS CS

⎛C α C2 z -1/ 2 ⎞ z -1/ 2 S ⎜ ⎟, ⋅ ⋅ + ⎜ CI (1- z -1 ) CI ⎟ ⎝ ⎠

(5-10)

where KCP= IIN/2π and TS is the update period or the reference period when the loop is locked. If we use the relationship in Eq. (5-6), Equation (5-10) can be rearranged as Eq. (5-11), where m=αC2/CS. H ( jω ) = K CP

TS CI

⎛ 1 + 2m sin 2 (ωTS 2 ) + j ⋅ m sin (ωTS ) ⎞ ⎜⎜ ⎟⎟ . 2 sin 2 ω j T ⋅ ( ) S ⎝ ⎠

(5-11)

In PLLs, the low-frequency response of the loop filter is of greater interest because the PLL loop bandwidth should be less than 1/10 of the reference frequency for stability concerns as discussed in Chapter 3. For these frequencies, we can assume

104

sin (ωTS / 2 ) ≈ ωTS / 2 .

(5-12)

With (5-12), the SC filter transfer function can be approximated by the following continuous-time transfer function H ( jω ) ≈

K CP (1 + jω ω z1 )(1 + jω ωz 2 ) ⋅ , CI jω

(5-13)

where

ωz1 = 2 ⎡⎢ ⎣

( ⎣(

ωz 2 = − 2 ⎡⎢

)

m 2 + 2m + m TS ⎤ , ⎦⎥

)

m 2 + 2m − m TS ⎤ . ⎥⎦

(5-14)

(5-15)

In Figure 5-9, the Φ2d switch performs a sample and hold function and it has a sinc response. Assuming the holding time is much larger than the sampling time, the complete phase-to-control voltage transfer function approximation should be H ( jω ) ≅

− jωT / 2 K CP (1 + jω ω z1 )(1 + jω ω z 2 ) sin (ωTS 2 ) e S ⋅ . ωTS 2 CI jω

(5-16)

The sinc low pass filter has a strong impact on the filter's magnitude and phase behaviors. In order to simplify the analysis, a single pole ωp = 2/TS is used to approximate the sinc filter's low frequency behavior. The phase and gain responses of the sinc and its approximation single pole filters are plotted in Figure 5-11. Their differences at 1/10 sampling frequency are also shown and the small deviations verify

105

the validity of this approximation. With this method, the open loop gain of this SC loop filter can be further approximated by H (s) ≅

K CP (1 + s ωz1 )(1 + s ω z 2 ) CI s ⋅ (1 + s / ω p )

(5-17)

where s = jω. Equation (5-17) carries the necessities for a type II PLL loop filter. Unlike the passive SC filters, the DC pole is preserved by the active SC integration. The stabilizing zero ωz1 is also well defined since TS is the reference period. In addition, a redundant right half plane (RHP) zero ωz2 exists in this loop filter. However, this RHP

Figure 5-11: Phase and gain responses of the sinc and single pole filters

106

zero has negligible effects on the loop stability since it is at a frequency much higher than the frequency of the stabilizing zero (m>>1). The loop phase margin can be found easily from (5-18), as ⎛ ⎛ ωc ⎞ −1 ⎛ ωc ⎞ −1 ωc ⎟ + tan ⎜ ⎟ − tan ⎜⎜ ⎝ ω z1 ⎠ ⎝ ωz 2 ⎠ ⎝ ωp

φm = tan −1 ⎜

⎞ ⎟⎟ , ⎠

(5-18)

where ωc is the unity gain frequency of the open loop. Since ωz 2 ≅ −ω p , the phase margin reaches its maximum when

ωc =

(ω

p

− 2ω z1 ) ω z1ω p 2ω p − ω z1

.

(5-19)

A loop filter is designed following the above analysis. Its magnitude and phase responses from 10KHz to 10MHz are depicted in Figure 5-12 and 4-13. The loop filter is designed for a 2.4GHz PLL with a 10MHz reference frequency. A 51 degree phase margin is chosen. From Figure 5-12 and 4-13, it is clear that at frequencies smaller than 1/(10TS), equation (5-17) is a good approximation for the original transfer function and this proves that the series of simplifications used above is valid. Loop filter circuit simulation is also carried out in Cadence and the results follow the theoretical prediction well. A transistor-level PLL is designed with the proposed low power active SC loop filter in a 0.18um CMOS environment. The loop filter is implemented in a differential configuration and a differentially tuned VCO is used. For a 10MHz input reference frequency, the sub-threshold inverter amplifier consumes a static current of about

107

Figure 5-12: Magnitude response of the active SC loop filters

110uA under a 1.2V power supply. The increase of inverter power supply voltage can give a larger bandwidth, but the current will also rise. The source follower buffer is biased at about 50μA. Figure 5-14 shows the VCO control voltages when a ring oscillator is used in the PLL. The reason for using the ring oscillator is simply for a more clear view of the results since less PLL output signal is coupled onto the control voltage compared to a LC VCO case. However, in the prototype, a LC VCO is integrated on-chip. In Figure 5-14, the asymmetry of the differential control voltages at circuit start-up exists because the common mode voltage is not well established during that time. After that, the loop settles quickly since the loop bandwidth is large.

108

Figure 5-13: Phase response of the active SC loop filters

This loop filter separates the charge pump charging phase and the control voltage output phase, and the sample and hold action also provides a magnitude notch for the filter's transfer function at multiples of the sampling frequency, thus reference spurs would be mainly caused by switch imperfections, such as switch charge injection and clock feed-through. Reference spur levels caused by rectangular voltage disturbance from the switches are analyzed quantitatively in next section. Several measures can be taken to effectively reduce their impacts. First, switches near the virtual ground node in Figure 5-9 should be turned off first to minimize distortion and gain error. Second, with the use of a half-size dummy output switch in series with the Φ2d

109

Figure 5-14: Transient response of VCO control voltages

switch, both charge injection and clock feed-through effects can be suppressed at the output node. Finally, with a differential configuration, common mode errors, like leakage current and the above two, can be effectively reduced. 5.2.3

Reference Spur and Noise of the Loop Filter

In order to investigate the reference spur problem caused by VCO control voltage variations quantitatively, the narrow-band frequency modulation theory is applied with the assumption that the variations are small. The VCO output voltage can be expressed as

(

t

)

Vout ( t ) = Am cos ω0t + KVCO ∫ VCtrl (τ ) dτ , 0

(5-20)

where Am is the voltage amplitude of the oscillator and ω0 is its initial frequency and the initial phase is set to zero. Equation (5-20) can be expanded as

110

)

(

)

(

t t Vout ( t ) = Am ⎡ cos (ω0t ) cos KVCO ∫ VCtrl (τ ) dτ − sin (ω0t ) sin KVCO ∫ VCtrl (τ ) dτ ⎤ . ⎥⎦ 0 0 ⎣⎢

π

t

Assuming KVCO ∫ VCtrl (τ ) dτ 0

2

max

(5-21)

, equation (5-21) reduce to

)

(

t Vout ( t ) ≈ Am ⎡cos (ω0t ) − KVCO ∫ VCtrl (τ ) dτ sin (ω0t ) ⎤ . ⎢⎣ ⎥⎦ 0

(5-22)

When the PLL is locked, the variation of the VCO control voltage can be modeled as a disturbance pulse train with period of TS. In a switched-capacitor loop filter, the disturbance is mainly contributed by switch charge injection and clock feed-through. Assume each pulse is rectangular and its amplitude and duration are v0 and t0, respectively. The pulse train can be decomposed into Fourier series as VCtrl ( t ) =

∞

∑ce

k =−∞

k

j 2π kt TS

,

(5-23)

where ck = = =

1 TS

1 TS

∫

TS 2

v ⋅ [u (t + t0 2) − u (t − t0 2) ] ⋅ e − j 2π kt TS dt

−TS 2 0

(∫

t0 2

v e − j 2π kt TS dt

− t0 2 0

)

,

(5-24)

v0t0 sin ( kπ t0 TS ) TS kπ t0 TS

Since VCtrl(t) is a real signal, Equation (5-23) can be rearranged as ∞ ⎡∞ ⎤ VCtrl ( t ) = c0 + Re ⎢ ∑ 2ck cos ( 2π kt TS ) ⎥ = c0 + ∑ 2ck cos ( kωref t ) . k =1 ⎣ k =1 ⎦

(5-25)

Ignoring the DC component in VCtrl(t), the phase deviation of Eq. (5-20) is ∞

∞

Δφ = KVCO ∫ VCtrl (τ ) dτ = 2 KVCO ∑ ∫ ck cos ( 2π kτ / TS ) dτ = 2 KVCO ∑ ck t

0

k =1

t

0

k =1

sin ( 2π kt TS ) . 2π k TS

111

(5-26) Substituting Eq. (5-26) into Eq. (5-22), we have ∞ K c ⎡ ⎤ Vout ( t ) ≈ Am ⎢ cos (ω0t ) − sin (ω0t ) ∑ VCO k sin ( kωref t ) ⎥ πk k =1 ⎣ ⎦ . (5-27) ∞ KVCO ck 1 ⎡ ⎤ cos ⎡⎣(ω0 + kωref ) t ⎤⎦ − cos ⎡⎣(ω0 − kωref ) t ⎤⎦ ⎥ = Am ⎢cos (ω0t ) + ∑ 2 k =1 π k ⎣ ⎦

{

}

Equation (5-27) indicates that spurs occur at offset frequencies of integer multiple of input reference frequency. The magnitude of the spur at offset kωref is ⎛ K v sin ( kπ t0 TS ) ⎞ Pspur , kωref = 20 log ⎜ VCO 0 2 ⎟⎟ . ⎜ k πωref ⎝ ⎠

(5-28)

In order to reduce the spur power, one should reduce the amplitude of the VCO control voltage ripple and a low sensitivity VCO is preferred. Some principles regarding the size of capacitors can be obtained by investigating output noise of this loop filter. Assuming the inverter amplifier has a transconductance gm, and all the switches have the same on-resistance Ron, for the integration path, its thermal noise power at the amplifier output node is given by

Pint, n ≈

CS21 ⎛ kT kT ( 2 Ron g m + γ ) kT ( 2 Ron g m + γ ) ⎞ + + ⎜ ⎟, CI2 ⎜⎝ CS 1 CC ( 2 Ron g m + 1) CS 1 ( 2 Ron g m + 1) ⎟⎠

(5-29)

where γ is a process-dependent coefficient. The first and second terms within the bracket account for thermal noise during Φ1. The third term is the contribution during Φ2. For the proportional path, its output thermal noise power is

Pprop , n ≈

C22 ⎛ 2 kT kT ( 2 Ron g m + γ ) ⎞ + ⎜α ⎟, CI2 ⎜⎝ CS 2 C2 ( 2 Ron g m + 1) ⎟⎠

(5-30)

112

where the noise contribution from the source follower is ignored. Equation (5-29) and (5-30) indicate that to achieve a low output noise design, capacitor CI, CC and CS2 should be large and small CS1 and C2 are favorable. In practical designs, C2 are usually much larger than CS1 in order to set the stabilizing zero at a proper location. Thus the size requirement on C2 and CS2 is of more concern. A low-power low-noise differential switched-capacitor loop filter is designed for a prototype PLL based on the above analysis, with Figure 5-9 as a half circuit. The input reference frequency is selected to be 10 MHz and the loop bandwidth is around 500 KHz. All capacitors in the design are below 10 pF. Two charge pumps with opposite current polarity are used for this differential loop filter and the magnitude of each current is around 100μA.

5.3

Other Building Blocks of the PLL Prototype Function-level PLL blocks are covered in Chapter 3. Circuit details about each

block in the prototype are presented in this section. 5.3.1

Phase/Frequency Detector

The phase/frequency detector (PFD) used in this PLL prototype design is illustrated in Figure 5-15. It is the state-machine architecture as described in Chapter 3 and widely used in literatures. The reset pulse duration is set by the delay block. 5.3.2

VCO

A differentially-tuned negative-gm LC VCO is designed to interface with the differential loop filter in the prototype and its schematic is shown in Figure 5-16. The complementary structure (cross-coupled p and n transistor pairs) used offers superior

113

Figure 5-15: PFD schematic

phase noise performance and a smaller 1/f3 noise corner compared with the nMOS only oscillator [67]. The on-chip octagonal spiral inductor is about 2.5nH and its peak Q factor is about 14. RF simulation tool ASITIC is used to aid the inductor design.

Figure 5-16: VCO schematic

114

For quick inductance estimation, L ≈ μ0 n 2 r can be used, where n is the number of turns and r is the radius of the spiral in meters. Accumulation-mode MOS transistors (nAMOS and pAMOS) are used as the differential tuning varactors [68]. Accumulation-mode MOS (AMOS) varactors operate in the depletion and accumulation regions and the formation of the inversion regions is inhibited. It exhibits performance better than diode or inversion-mode varators [68]. In order to investigate the tuning characteristics of the AMOS varactors, Cadence Periodical Steady-State (PSS) simulations have been carried out and the admittance parameters (Y parameters) are obtained to derive the capacitance and quality factors of the varactors. The relationships between the capacitance C/quality factor Q and the Y11 are found as C=

Im(Y11 )

,

(5-31)

Q=

Im(Y11 ) . Re(Y11 )

(5-32)

ω

While for an inductor L, the relationships are L=

Im(1 Y11 )

,

(5-33)

Q=

Im(1 Y11 ) . Re(1 Y11 )

(5-34)

ω

The tuning characteristics for the varactors are plotted in Figure 5-17. It can be observed that the complementary varactors give a capacitance ranging from Cmin to

115

Figure 5-17: Tuning Characteristics for the nAMOS and pAMOS varactors

about 2Cmin. However, considering the parasitic capacitance in presence, the tuning range of the VCO would be much smaller. Simulation results demonstrate that the tuning characteristic of the VCO is very close to a straight line and no special linearization technique is employed. Many efforts have been carried out to model the phase noise performance of oscillators and to optimize their designs. A widely used linear time-invariant phase noise model is deduced by Leeson [69] as shown in Eq. (5-35). ⎧⎪ 2 FkT L ( Δf ) = 10 log ⎨ P ⎩⎪ s

⎡ ⎛ f ⎞ 2 ⎤ ⎛ Δf1/ f 3 ⎢1 + ⎜ 0 ⎟ ⎥ ⎜ 1 + Δf ⎢⎣ ⎝ 2QΔf ⎠ ⎥⎦ ⎝⎜

⎞ ⎫⎪ , ⎟⎟ ⎬ ⎠ ⎭⎪

(5-35)

where F is the empirical active device noise factor, k is Boltzmann constant, T is

116

temperature, Ps is output signal power, f0 is center frequency, Q is the loaded quality factor of the resonator, Δf is the offset frequency and Δf1/f3 is the corner frequency of 1/f3 phase noise. The phase noise model is plotted in Figure 5-18. A more accurate oscillator phase noise model based on linear time-varying analysis is developed in [70][71]. With the impulse sensitivity function (ISF) Γ(x), the expression for the single-sideband phase noise is 2 ⎛ i 2 Δf Γ rms ⎞ L ( Δω ) = 10 log ⎜ n 2 ⎟, 2 ⎜ qmax 2Δω ⎟ ⎝ ⎠

(5-36)

where in2 Δf is the power spectral density of the parallel current noise, Γrms is the rms value of the ISF associated with that noise source an qmax is the maximum signal charge swing. The above oscillator phase noise model becomes invalid when the frequency offset approaches zero. A general noise model based on nonlinear perturbation analysis is proposed in [72], where the errors of models based on linear analysis are

Figure 5-18: Phase noise model in Eq. (4-35)

117

eliminated. With the knowledge of oscillator phase noise, design strategy can be obtained to optimize phase noise, which is subject to various design constraints [73]. 5.3.3

Programmable Divider

The pulse swallow programmable divider is discussed in Section 3.2.3. Compared with the dual-modulus prescaler, the M and A counters operate at relatively low speeds; therefore they are implemented with simple true-single-phase-clock (TSPC) flip flops. This section focuses on the design and implementation of the high-speed prescaler. The block diagram of the dual-modulus phase-switching prescaler in this design is shown in Figure 5-19, where MC is the modulus control signal from the divider. The first and second divide-by-2 stages are implemented with the source-coupled logic (SCL) without tail current [74]. Four 90-degree-spaced outputs (in-phase, quadrature, and their reverse signals) are generated and fed into the 4:1 Mux. If MC is high, phase switching occurs and the Mux output will change from p1 to p2, p2 to p3, p3 to p4 or p4 to p1. Otherwise, the Mux output remains the same as the previous cycle. It can be identified that compared with the conventional design [75], the

Figure 5-19: Block diagram of the prescaler

118

Figure 5-20: State machine for the phase select signals

switching sequence are reversed in this design to avoid output glitch [76]. Thus the modulus is (P-1)/P instead of P/(P+1), where P is 8 in this design. The phase select signals S1, S2, S3 and S4 are generated with a simple state machine. Encoding the four phases p1, p2, p3, and p4 as states of Y1Y2=00, 01, 11, and 10, respectively, the phase select signals can be described by the state machine shown in Figure 5-20. The circuit employed to implement this state machine is shown in Figure 5-21, where D1 and D2 are defined by simple combinational logic derived by the state machine and the Karnaugh maps are shown in table 4-1 and 4-2. By using a simple decoder, the select signals can be obtained from Y1 and Y2. In this prescaler, a systematic phase mismatch exists in the physical implementation and it can cause spurs in the PLL output spectrum. If the division ratio is a multiple of P, the phase mismatch does not have an effect since no phase switching occurs. If the scenario is a fractional-N divider employing ΔΣ modulation technique [77], the spur problem is generally eliminated due to the random phase switching. Thus, the spur is most significant when an integer division ratio which is not a multiple of P is present.

119

Figure 5-21: Circuit implementing the state machine in Figure 4-20 Table 5-1:

Karnaugh map for D1

Table 5-2:

Karnaugh map for D2

However, by careful circuit design and layout for good symmetry and matching of the prescaler components, the spurs caused by prescaler phase mismatch can be suppressed to a negligible level [78].

5.4

Prototype Measurement Results The PLL prototype is fabricated in a commercial 0.18μm CMOS process. The die

photo of the PLL prototype is shown in Figure 5-22. It takes a space of about 0.55 by 0.65 mm2, among which the low-power active switched-capacitor loop filter takes about 0.3 by 0.25 mm2. The die is enclosed in a PGA package and an evaluation board providing the power supplies and the reference voltage is constructed to facilitate circuit testing.

120

Figure 5-22: PLL die photo

Under the integer-N configuration, at an input frequency of 10 MHz and an output frequency of 2.56 GHz, the PLL output phase noise is depicted in Figure 5-23. The phase noise is -86 dBc/Hz at 100 kHz offset and -124 dBc/Hz at 3 MHz offset. At low offset frequencies, the PLL's output phase noise increase gradually. With the large division ratio N used, calculation results indicate that the input reference noise dominates in-band phase noise and the increase is caused by the reference quality degradation at low offset. Due to the Type II loop dynamics, phase noise peaking can be observed in the figure. Loop bandwidth is found to be about 350 kHz. In the loop filter, the differential inverter amplifiers consume 230μA under a 1.2V power supply, and the two source followers consume 100μA with a 1.8V power supply. The entire PLL consumes about 16 mW. The output spectrum of the PLL is shown in Figure 5-24. With an output of -6.7 dBm, the reference spur is about -64 dBc. Its

121

Figure 5-23: PLL phase noise measurement plot

performance is compared to PLLs implemented with other loop filter architectures as given in Table 4-3. With reduced power consumption and chip area, the PLL employing the active switched capacitor loop filter achieves comparable reference spur and phase noise performance.

5.5

Chapter Conclusion In this chapter, a fully integrated type-II differential PLL with a proposed

low-power active switched-capacitor loop filter is designed and verified. In order to facilitate the design procedures, the complete continuous-time equivalent transfer function including the sinc holding effect and noise issues for the loop filter are presented. Design details for each PLL block are also covered. Measurement results demonstrate that the loop filter consumes only 3% out of the total PLL power. Space taken by the loop filter is small. This architecture provides a power- and cost-efficient way for high-performance PLL on-chip integration.

122

Figure 5-24: PLL output spectrum

TABLE 5-3 PLL PERFORMANCE COMPARISON Freq. (GHz) Technology Loop Filter Structure Reference Frequency Power (mW) 2

Area (mm ) Reference Spur Phase Noise

[61]

[79]

[80]

This Work

2.4

2.4

3.6

2.5

0.25μm CMOS

0.18μm CMOS

0.18μm CMOS

0.18μm CMOS

Passive SC

Passive SC

Hybrid

Active SC

1MHz

12MHz

50MHz

10MHz

?

66

110

16

?

4.8

2.7

0.36

-62dBc -126dBc/Hz @2MHz

-70dBc -125dBc/Hz @3MHz

-45dBc -155dBc/Hz @20MHz

-64dBc -124dBc/Hz @3MHz

123

Chapter 6 A Multi-bit ΔΣ ADC with a Low-Power SC Nonlinearity-Suppressed DAC

As mentioned in Chapter 4, a multi-bit ΔΣ ADC can enhance loop stability and improve SNR by reducing quantization noise power and allowing more aggressive noise shaping. In a multi-bit ΔΣ modulator, the low-resolution quantizer is simple to design since non-idealities introduced by the quantizer are shaped by the loop filter. However, nonlinearity from the feedback DAC is not shaped by the loop filter and the DAC should match the overall accuracy of the ADC. Otherwise, nonlinearity or distortion in the feedback DAC would degrade the performance of the ADC directly. In this chapter, the problems of existing methods proposed to construct the demanded high-linearity

feedback

DAC

are

reviewed.

We

propose

a

low-power

nonlinearity-suppressed DAC method in this work and a multi-bit ΔΣ modulator topology compatible with this proposed method is implemented and verified.

6.1

Existing Techniques to Enhance DAC Linearity Component mismatch is an inherent property in semiconductor technologies. In

Section 2.2.2, it has been shown that in a charge-redistribution (capacitor-array) DAC, capacitor mismatch and capacitance voltage dependency can introduce non-linearity.

124

The effect of voltage dependency can be suppressed by differential structure and is usually small compared with that of mismatch. Thus in practice, existing solutions focus on techniques which can compensate or correct mismatches among unit capacitors in the DAC. 6.1.1

Layout considerations for capacitor matching

The capacitance of a capacitor is ideally defined by permittivity, thickness and area of the dielectric. In CMOS processes, errors usually arise from two main factors when realizing a capacitor [81]. The first is over-etching, which results in a smaller actual area than that of the mask. This effect can be suppressed by implementing large capacitors from combinations of smaller, unit-sized capacitors. Then the ratio of capacitors is converted into ratio of numbers of unit capacitors. The second issue is the gradient of the oxide thickness. The measure to counteract this problem is to use the common-centroid layout of unit capacitors. This is to try to keep the gradient effect the same for both the capacitors. However, in reality, ratios between two large capacitors are arbitrary and large capacitors may not be decomposed into unit capacitors of exactly the same size. But the effect of over-etching can still be minimized when the perimeter-to-area ratios are kept the same, even if the capacitors have different sizes. Using Cox to represent the unit area capacitance, x and y to represent the length and width of a capacitor, Δe to represent the absolute over-etching error, the actual capacitance can be given by C1 = Cox ( x1 − Δe )( y1 − Δe ) .

The absolute capacitance error is

(6-1)

125

ΔC1 = Cox ⎡⎣ Δe ( x1 + y1 ) − Δe 2 ⎤⎦ .

(6-2)

Ignoring the high order error, the relative capacitance error is

ε1 =

x1 + y1 . x1 y1

(6-3)

Therefore, if the perimeter-to-area ratio is kept constant for capacitors, the relative error remains approximately the same. When a non-unit-size capacitor Ck is needed, assume it is 1