MIPS-Lite Processor Datapath Design COE608: Computer Organization and Architecture Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering

Ryerson University

Overview • • • • • •

Design a processor: step-by-step Requirements of the Instruction Set MIPS-Lite Instructions Components and Clocking Assembling an adequate Datapath Controlling the Datapath

Chapter 4 (4.1, 4.2 & 4.3) of the textbook

© G.N. Khan

Computer Organization & Architecture – coe608: MIPS- Datapath

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Design a Processor Processor design (data path, alu and control) It determines • Clock cycle time • Clock cycles per instruction

Single cycle processor: Advantage: Disadvantage:

Analyze Instruction Set => Data path Requirements Meaning of each instruction is given by register transfers

© G.N. Khan

Computer Organization & Architecture – coe608: MIPS- Datapath

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Single Cycle Processor Data path 1. Analyze the Instruction Set Interconnection to support RT 2. Select set of data path components and establish clocking methodology 3. Assemble data path meeting the requirements 4. Analyze the implementation of each instruction. 5. Assemble the control logic.

© G.N. Khan

Computer Organization & Architecture – coe608: MIPS- Datapath

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MIPS Instruction Formats All MIPS instructions are 32 bits long. There are three instruction formats: 31

26 op 6 bits

31

21 rs 5 bits

26 op 6 bits

31

16 rt 5 bits

21 rs 5 bits

11 rd 5 bits

6 shamt 5 bits

0 funct 6 bits

16 rt 5 bits

0 immediate 16 bits

26

0

op 6 bits

target address 26 bits

op funct rs, rt, rd shamt address/immediate target address

© G.N. Khan

Computer Organization & Architecture – coe608: MIPS- Datapath

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MIPS-Lite Instructions A Subset of MIPS Instructions ADD and SUB 31

26

21

op

16

rs

6 bits

11

rt

5 bits

5 bits

6

0

rd

shamt

funct

5 bits

5 bits

6 bits

OR immediate 31

26

21

op

rs

6 bits

16

0

rt

5 bits

immediate

5 bits

16 bits

LOAD and STORE Word 31

26

21

op

rs

6 bits

16 rt

5 bits

0 immediate

5 bits

16 bits

BRANCH 31

26 op 6 bits

© G.N. Khan

21 rs 5 bits

16 rt 5 bits

0 immediate 16 bits

Computer Organization & Architecture – coe608: MIPS- Datapath

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Logical Register Transfers RTL gives the meaning of the instructions All start by fetching the instruction op | rs | rt | rd | shamt | funct op | rs | rt | Imm16

inst

= MEM[ PC ] = MEM[ PC ]

Register Transfers

ADDU

PC