RISC Processor Design
[email protected]
Advance Computer Architecture http://www.serc.iisc.ernet.in/~viren/ACA/ACA.htm
Design
Laboratory
& Test
Virendra Singh Computer Design and Test Lab. Indian Institute of Science Bangalore
Computer
Implementation from Flowchart
Datapath for DLX S1 Bus
L1
S2 Bus
A L U
DST Bus
L2
A B
Register File
C
PC MAR MDR
2
Design
& Test
Advance Computer Architecture
Computer
Constants
IR
Laboratory
Arithmetic Logic Unit S1
S2
Inv
fn(3)
MUX Carry alu_overflow
Overflow
+ fn(1) fn(0)’
Cin
fn(3)
fn(3)
MUX
lr
fn(3)
ar
fn(2)
Shifter
fn(0) fn(1)
neg
Logic
fn(3)
0
Comp zero 3
Design
& Test
Advance Computer Architecture
fn(2)
Computer
MUX
Laboratory
Merged Level 2 Hardware Flowchart ADD Rd, Rs1, Rs2 ir nop none
fetch
none
rf → a rf → b pc → s2 → alu +4 → s1 → alu alu → dst → pc dec
none
dec
add_1
none
none add none
W_B none
none
nop
c → rf
add
none none
W_B
none
fetch
add_1
4
Design
& Test
Advance Computer Architecture
Computer
pc → eab edb → ir
a → s1 → alu y → s2 → alu alu → dst → c
Laboratory
Merged Level 2 Hardware Flowchart OR Rd, Rs1, Rs2 ir nop none
fetch
none
rf → a rf → b pc → s2 → alu +4 → s1 → alu alu → dst → pc dec
none
dec
or_1
none
none or none
W_B none
none
nop
c → rf
add
none none
W_B
none
fetch
or_1
5
Design
& Test
Advance Computer Architecture
Computer
pc → eab edb → ir
a → s1 → alu y → s2 → alu alu → dst → c
Laboratory
Merged Level 2 Hardware Flowchart SLT Rd, Rs1, Rs2
a → s1 → alu y → s2 → alu
ir nop
none
n=1
none
fetch
none
rf → a rf → b pc → s2 → alu +4 → s1 → alu alu → dst → pc dec
none
sub
slt_1
none
bc
n=0
dec none add
1 → s1 → alu alu → dst → c Set_1
none
none
c → rf
slt_1 W_B
none
none s1_p none
W_B none nop none
fetch
Set_0
none
c → rf W_B
none 6
none
W_B none nop none
fetch Design
& Test
Advance Computer Architecture
0 → s1 → alu alu → dst → c
none s1_p
Computer
pc → eab edb → ir
none
Laboratory
Merged Level 2 Hardware Flowchart LW Rd, Rs2(Rs1) ir
fetch
none
none
a → s1 → alu y → s2 → alu alu → dst → mar rf → b
Mem_a
none
none
rf → a rf → b pc → s2 → alu +4 → s1 → alu alu → dst → pc
dec
mar → eab edb → mdr
nop
none
dec
none
lw_1
none
none add none
Mem_a none
none
mdr → s1 → alu alu → dst → c
S1_p none
lw_2
none
W_B none
c → rf
add
none none
none
1w_1
lw_2
W_B
fetch 7
Design
& Test
Advance Computer Architecture
none
Computer
pc → eab edb → ir
RW
Laboratory
Merged Level 2 Hardware Flowchart LH Rd, Rs2(Rs1) ir
fetch
none
none
a → s1 → alu y → s2 → alu alu → dst → mar rf → b
Mem_a
none
none
rf → a rf → b pc → s2 → alu +4 → s1 → alu alu → dst → pc
dec
mar → eab edb → mdr
nop
none
dec none add
none
lh_1
none
mdr → s1 → alu
16 → s2 → alu alu → dst → c
none
Mem_a none
lh_2
none sra none
none
W_B none
c → rf
add
none none
none
lh_1
lh_2
W_B
fetch 8
Design
& Test
Advance Computer Architecture
none
Computer
pc → eab edb → ir
RH
Laboratory
Merged Level 2 Hardware Flowchart LB Rd, Rs2(Rs1) ir
fetch
none
none
a → s1 → alu y → s2 → alu alu → dst → mar rf → b
Mem_a
none
none
rf → a rf → b pc → s2 → alu +4 → s1 → alu alu → dst → pc
dec
mar → eab edb → mdr
nop
none
dec none add
none
lb_1
none
mdr → s1 → alu
24 → s2 → alu alu → dst → c
none
Mem_a none
lb_2
none sra none
none
W_B none
c → rf
add
none none
none
lb_1
lb_2
W_B
fetch 9
Design
& Test
Advance Computer Architecture
none
Computer
pc → eab edb → ir
RB
Laboratory
Implementation - States
fetch, dec, mem_a
add_1, sub_1, and_1, or_1, xor_1,sll_1, srl_1, sra_1
seq_1, neq_1, slt_1, sle_1, sgt_1, sge_1
Lw_1, lw_2, lh_1, lh_2, lb_1, lb_2, sw_11, sw_2, sh_1, sh_2, sb_1, sb_2
breqz, brnez, branch, Set_1, Set_0
reset
10
Design
& Test
Advance Computer Architecture
Computer
States:
Laboratory
Implementation - Controller clk From DP opc & funct opc & funct opc & funct Rs2 Rd Rs1
DEC1
FSM
Dst_en S1_en S2_en alu_ctl
DEC2
rf_ctl Mem_ctl various_ctl
DEC3
Rs2 address
Logic
Rd address Rs1 address To S1 bus To S2 bus
IR
11
Design
& Test
Advance Computer Architecture
Computer
From memory Laboratory
State Transition Reset
Ready=0
fetch Ready=1 dec
slt_1 sub_1
.....
sll_1
n=1 Set_1
W_B
lw_1 lw_2
....
sh_2
sb_1 sw_2
12
Design
& Test
Advance Computer Architecture
sh_1
Computer
add_1
Mem_a
Laboratory
State Transition Reset
Ready=0
fetch Ready=1 dec
ta s i s s a der’s o c e d Need
Mem_a Need decoder’s assistance
slt_1 sub_1
.....
sll_1
n=1 Set_1
W_B
lw_1 lw_2
....
sh_2
sb_1 sw_2
13
Design
& Test
Advance Computer Architecture
sh_1
Computer
add_1
nce
Laboratory
State Transition Reset
Ready=0
fetch Ready=1 dec
Mem_a
r1 e d o c De slt_1
sub_1
.....
sll_1
n=1 Set_1
W_B
lw_1 lw_2
....
sh_2
sb_1 sw_2
14
Design
& Test
Advance Computer Architecture
sh_1
Computer
add_1
Decoder2
Laboratory
Implementation Reset
15
Design
& Test
Advance Computer Architecture
Computer
when reset_1 => s1_enab
