RISC Processor Design Multi-cycle Cycle Implementation: MIPS Virendra Singh Indian Institute of Science Bangalore
[email protected] Lecture 18
SE-273: Processor Design
Courtesy: Prof. Vishwani Agrawal
Mar 07, 2008
SE-273@SERC
2
16-20 11-15
Combined Datapaths 0-15
Sign ext.
Shift left 2
0 mux 1
1 mux 0
ALU zero
MemtoReg
MemWrite MemRead
Data mem.
ALU Cont.
0-5 Mar 07, 2008
SE-273@SERC
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0 mux 1
Instr. mem.
ALU
PC
1 mux 0
21-25
1 mux 0
26-31
Branch
Reg. File
opcode
Jump
Shift left 2
CONTROL
RegDst
4
Add
0-25
Time for Jump (J-Type) z z z z z
ALU (R-type) Load word (I-type) Store word (I-type) Branch on equal (I-type) Jump (J-type)
• Fetch (memory read) • Total
Mar 07, 2008
SE-273@SERC
6ns 8ns 7ns 5ns 2ns
2ns 4
How Fast Can the Clock Be? z
If every instruction is executed in one clock cycle, then:
• Clock period must be at least 8ns to perform the • •
z
longest instruction, i.e., lw. This is a single cycle machine. It is slower because many instructions take less than 8ns but are still allowed that much time.
Method of speeding up: Use multicycle datapath. Mar 07, 2008
SE-273@SERC
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A Single Cycle Example Delay of 1-bit full adder = 1ns Clock period ≥ 32ns
a31 . . . a2 a1 a0 b31 . . . b2 b1 b0
1-b full adder 1-b full adder 1-b full adder 1-b full adder 0 Mar 07, 2008
Time of adding words ~ 32ns Time of adding bytes ~ 32ns SE-273@SERC
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c32 s31 . . . s2 s1 s0
a31 . . . a2 a1 a0 b31 . . . b2 b1 b0 Mar 07, 2008
Delay of 1-bit full adder = 1ns Clock period ≥ 1ns Time of adding words ~ 32ns Time of adding bytes ~ 8ns 1-b full adder c32
FF
Initialize to 0 SE-273@SERC
s31 . . . s2 s1 s0
Shift
Shift
Shift
A Multicycle Implementation
7
Mar 07, 2008
ALUOut Reg.
4
ALU
A Reg. B Reg.
Register file
Mem. Data (MDR)
Data
Instr. reg. (IR)
Addr.
Memory
PC
Multi-cycle Datapath
One-cycle data transfer paths (need registers to hold data)
SE-273@SERC
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Multi-cycle Datapath Requirements z z z
Only one ALU, since it can be reused. Single memory for instructions and data. Five registers added:
• Instruction register (IR) • Memory data register (MDR) • Three ALU registers, A and B for inputs and ALUOut for output
Mar 07, 2008
SE-273@SERC
9
Multicycle Datapath
MUX in1
control in2
MemRead MemWrite Mar 07, 2008
IRWrite
RegDst
MemtoReg
0-15 0-5
SE-273@SERC
Sign extend
ALUOut Reg.
ALU
ALUSrcB
28-31
ALUSrcA
A Reg.
11-15
16-20
Shift left 2
RegWrite
B Reg.
out
21-25
Register file
Data
0-25
Mem. Data (MDR)
IorD
Memory
Addr.
PC
26-31 to Control FSM
Instr. reg. (IR)
PCWrite etc.
PCSource
4
Shift left 2 ALU control
10
ALUOp
3 to 5 Cycles for an Instruction Step
R-type (4 cycles)
Mem. Ref. (4 or 5 cycles)
Branch type (3 cycles)
J-type (3 cycles)
Instruction fetch
IR ← Memory[PC]; PC ← PC+4
Instr. decode/ Reg. fetch
A ← Reg(IR[21-25]); B ← Reg(IR[16-20]) ALUOut ← PC + (sign extend IR[0-15])
