CISC Processor Design

[email protected] Lecture 5

SE-273: Processor Design

Design & Test

Virendra Singh Indian Institute of Science Bangalore

Computer

Hardware Flowchart

Laboratory

Flowchart Objective Flowchart Objective ¾ Limit controller size to some fraction of chip area ¾ Make CPU as fast as possible ¾ Complete the project as early as possible

SE-273@SERC

2

Design & Test

Jan 26, 2009

Computer

¾ Make the flowcharts easy to translate into hardware

Laboratory

MIN Instruction Set Instruction Format

Programmer’s Register Set

First Word Op-code Operation Code

Rx First Operand Register

Mode Second Operand Address Mode

Ry First Operand Register

R0 R1 R2 . . .

Second Word Rn

Displacement

SE-273@SERC

3

Design & Test

Jan 26, 2009

Computer

Optional, depending on second operand address mode

Laboratory

MIN Instruction Set 9

ADD

9

AND

9

BZ – Branch if zero bit is set. (Register Indirect only)

9

LOAD – Second operand is source and Rx is destination

9

POP – Postincrement with register indirect only

9

PUSH – Predecrement with register indirect only

9

STORE

9

SUB

9

TEST SE-273@SERC

4

Design & Test

Jan 26, 2009

Computer

MIN Instruction Set

Laboratory

MIN Instruction Set Second Operand Address Mode

Ry

Second Operand Address Mode

First Operand Register

¾

AB - Base (Ry) plus displacement (second instruction word) is an operand address

¾

AI – Register indirect. Ry holds an operand address

¾

AR – Register direct: The result is stored in Ry. For two operand instructions, Ry also is an operand source SE-273@SERC

5

Design & Test

Jan 26, 2009

Computer

Address Modes

Laboratory

MIN Datapath IRE

IRF

Internal A Bus

PC

T2

R0

R1

Rn

T1

ALU

k DI

Internal B Bus

External Data

External Address

Bus (EDB)

Bus (EAB)

SE-273@SERC

6

Design & Test

Jan 26, 2009

Computer

AO

DO

Laboratory

MIN Datapath Rules of Operation 1. A transfer from source to bus to destination takes one state time 2. A source can drive up to three destination loads 3. Inputs to the ALU are from A (internal) bus and either k (values 0, +1, -1) or the B (internal) bus 4. When ALU is destination. Ti is automatically loaded from the ALU output

SE-273@SERC

7

Design & Test

Jan 26, 2009

Computer

5. A transfer to AO activates the on-chip external bus controller. This bus controller postpones the next state until the external transfer is complete.

Laboratory

Flowcharts ADD RX AR RY

ADD RX AI (RY)

Register-to-Register R→R ADD

Register-to-Memory R→M ADD

rx → a → alu ry → b → alu

edb → di ry → b → ao di → b → alu rx → a → alu

IRE

AO PC T2

R0 R1

IRF DO

Rn

Internal B Bus

ALU

k DI

ry → b → ao t1 → a → do SE-273@SERC

8

Design & Test

Jan 26, 2009

T1

Sequence

Computer

t1 → b → ry

Internal A Bus

State

Laboratory

Flowcharts Register-to-Register R

→R

ADD

edb → irf pc → b → ao rx → a → alu ry → b → alu t1 → b → ry pc → a → alu +1 → alu t1 → b → pc

Register-to-Memory R→M ADD

Execution Speed

¾

edb → irf pc → b → ao edb → di ry → b → ao di → b → alu rx → a → alu ry → b → ao t1 → a → do pc → a → alu +1 → alu t1 → b → pc SE-273@SERC

9

Design & Test

Jan 26, 2009

ADD RX AI (RY)

Computer

ADD RX AR RY

Laboratory

Level 1 Flowchart - ADD ADD RX AR RY

Register-to-Register R

→R

ADD

rx → a → alu ry → b → alu

edb → irf pc → b → ao pc → a → alu +1 → alu

Operation tasks

irf → ire t1 → b → pc Housekeeping tasks

IRE

AO PC T2

(EAB)

SE-273@SERC

IRF DO

Rn

T1

ALU

k DI

Internal B Bus

(EDB)

10

Design & Test

Jan 26, 2009

R0 R1

Internal A Bus

Computer

t1 → b → ry

Laboratory

Level 1 Flowchart - ADD ADD RX AI (RY)

Register-to-Memory

→M

ADD

edb → di ry → b → ao

edb → irf pc → b → ao

di → b → alu rx → a → alu

pc → a → alu +1 → alu

ry → b → ao t1 → a → do

irf → ire t1 → b → pc

Operation tasks

Housekeeping tasks

IRE

AO PC T2

(EAB)

SE-273@SERC

IRF DO

Rn

T1

ALU

k DI

Internal B Bus

(EDB)

11

Design & Test

Jan 26, 2009

R0 R1

Internal A Bus

Computer

R

Laboratory

Level 2 Flowchart - ADD Register-to-Register R

→R

ADD

rx → a → alu ry → b → alu edb → irf pc → a → alu, ao t1 → b → ry +1 → alu irf → ire t1 → b → pc

Register-to-Memory R→M ADD

edb → irf pc → a → alu, ao +1 → alu edb → di ry → b → ao, t2 t1 → a → pc

Merger • Speed • Identical states

di → b → alu rx → a → alu irf → ire t1 → a → do t2 → b → ao SE-273@SERC

12

Design & Test

Jan 26, 2009

ADD RX AI (RY)

Computer

ADD RX AR RY

Laboratory

Level 2 Flowchart - ADD ADD RX AR RY

R

Register-to-Register

Do level2 flowchart of the fastest instruction Point out inadequacy in Datapath

(EAB)

R0 R1

IRF DO

Rn

Internal B Bus

ALU

k DI

pc → a → alu +1 → alu irf → ire t1 → b → pc

(EDB)

SE-273@SERC

13

Design & Test

Jan 26, 2009

T1

edb → irf pc → b → ao t1 → a → ry

Computer

AO PC T2

Internal A Bus

ADD

rx → a → alu ry → b → alu

when AO is connected to B (internal) bus only

IRE

→R

Laboratory

Level1 Flowchart Level1 Flowchart ¾ At the beginning of instruction execution, IRE is assumed to contain the current instruction ¾ Instruction execution begins with the address mode sequence ¾ The execution sequences for Register-toRegister instructions cannot be shared

SE-273@SERC

14

Design & Test

Jan 26, 2009

Computer

¾ The execution sequences for standard dual operand instructions are identical

Laboratory

Level 1 FlowchartAddress Mode Sequences Base Plus Displacement

Register Indirect

edb → di pc → a → alu, ao +1 → alu

edb → di ry → b → ao, t2

t1 → a → pc di → b → alu ry → a → alu IRE

AO PC T2

(EAB)

SE-273@SERC

DO Rn

T1

ALU

k DI

Internal B Bus

(EDB)

15

Design & Test

Jan 26, 2009

R0 R1

Internal A Bus

IRF

Computer

edb → di t1 → b → ao, t2

Laboratory

Level 1 FlowchartAddress Mode Sequences IRE

Branch Instruction AO PC T2

edb → irf ry → a → alu, ao +1 → alu

(EAB)

R0 R1

Internal A Bus

IRF DO

Rn

T1

ALU

k DI

Internal B Bus

(EDB)

Z = 0 (no branch)

Z = 1 (Branch)

edb → irf pc → a → alu, ao +1 → alu

irf → ire t1 → b → pc

SE-273@SERC

16

Design & Test

Jan 26, 2009

Computer

irf → ire t1 → b → pc

Laboratory

Level 1 Flowchart Execution Sequences Execution sequences with memory operand reference STORE

LOAD edb → irf di → b → rx, t2 pc → a → alu, ao +1 → alu t2 → a → alu 0 → alu

rx → a → alu, do edb → irf t2 → b → ao pc → a → alu, ao +1 → alu 0 → alu

irf → ire t1 → b → pc

irf → ire t1 → b → pc IRE

AO PC T2

(EAB)

Jan 26, 2009

SE-273@SERC

R0 R1

Internal A Bus

IRF DO

Rn

T1

ALU

k DI

Internal B Bus

(EDB)

17

Level 1 Flowchart Execution Sequences Execution sequences with memory operand reference SUB

ADD di → b → alu rx → a → alu

edb → irf pc → a → alu, ao +1 → alu

di → b → alu rx → a → alu

edb → irf pc → a → alu, ao +1 → alu

t1 → a → do t2 → b → ao

irf → ire t1 → b → pc

t1 → a → do t2 → b → ao

irf → ire t1 → b → pc IRE

(EAB)

SE-273@SERC

Rn

T1

ALU

k DI

Internal B Bus

(EDB)

18

Design & Test

Jan 26, 2009

R0 R1

DO

Computer

AO PC T2

Internal A Bus

IRF

Laboratory

Level 1 Flowchart Execution Sequences Execution sequences with memory operand reference TEST

AND di → b → alu rx → a → alu

edb → irf pc → a → alu, ao +1 → alu

di → b → t2

edb → irf pc → a → alu, ao +1 → alu

t1 → a → do t2 → b → ao

irf → ire t1 → b → pc

t2 → a → alu 0 → alu

irf → ire t1 → b → pc IRE

(EAB)

SE-273@SERC

Rn

T1

ALU

k DI

Internal B Bus

(EDB)

19

Design & Test

Jan 26, 2009

R0 R1

DO

Computer

AO PC T2

Internal A Bus

IRF

Laboratory

Level 1 Flowchart Execution Sequences Execution sequences for Register-to-Register and special instructions STORE

LOAD edb → irf ry → a → alu,rx pc → a → alu, ao 0 → alu +1 → alu

rx → a → alu, ry edb → irf pc → a → alu, ao 0 → alu +1 → alu irf → ire t1 → a → pc IRE

AO PC T2

(EAB)

SE-273@SERC

DO Rn

T1

ALU

k DI

Internal B Bus

(EDB)

20

Design & Test

Jan 26, 2009

R0 R1

Internal A Bus

IRF

Computer

irf → ire t1 → a → pc

Laboratory

Level 1 Flowchart Execution Sequences Execution sequences for Register-to-Register and special instructions SUB

ADD rx → a → alu ry → b → alu

edb → irf pc → a → alu, ao +1 → alu

rx → a → alu ry → b → alu

edb → irf pc → a → alu, ao +1 → alu

t1 → a → ry

irf → ire t1 → a → pc

t1 → a → ry

irf → ire t1 → a → pc IRE

(EAB)

SE-273@SERC

Rn

T1

ALU

k DI

Internal B Bus

(EDB)

21

Design & Test

Jan 26, 2009

R0 R1

DO

Computer

AO PC T2

Internal A Bus

IRF

Laboratory

Level 1 Flowchart Execution Sequences Execution sequences for Register-to-Register and special instructions PUSH

POP

di → b → rx t1 → a → ry

irf → ire t1 → a → pc

ry → a → alu -1 → alu

edb → irf pc → a → alu, ao +1 → alu

rx → a → do t1 → b → ao, ry

irf → ire t1 → a → pc IRE

AO PC T2

(EAB)

SE-273@SERC

DO Rn

T1

ALU

k DI

Internal B Bus

(EDB)

22

Design & Test

Jan 26, 2009

R0 R1

Internal A Bus

IRF

Computer

edb → di edb → irf ry → a → alu, ao pc → a → alu, ao +1 → alu +1 → alu

Laboratory

SE-273@SERC

23

Design & Test

Jan 26, 2009

Computer

Thank You Laboratory