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FPGA and ASIC
How to implement a digital system No two applications are identical and every one needs certain amount of customization Basic methods for customization a) “General-purpose hardware” with custom software • General purpose processor: e.g., performance-oriented processor (e.g., Pentium), cost-oriented processor (e.g., PIC micro-controller) • Special purpose processor: architecture with a specific set of functions: e.g., DSP processor (to do multiplication-addition), network processor (to do buffering and routing), “graphic engine” (to do 3D rendering) b) Custom hardware (no software) c) Custom software on a custom platform (CPU+other hardware), known as hardware-software co-design
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How to implement a digital system (2)
SP Hardware
ASP HW/SW CO DSP
SP Hardware
GPP
Flexibility
ASP HW/SW CO
Costs
Performance
Trade-off between flexibility, programmability, design effort, cost, performance, and power consumption
GPP
DSP
Design effort TKT-1426 Lecture 3
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DEVICE TECHNOLOGIES
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What does an IC look like? Several metal layers – Less congestion
Hierarchical scaling Wires on top levels are wider and taller than on lower levels Top layers are for – Power supply – Clock – Global signals
transistors
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What does an IC look like? (2)
Intel dual core
Package The IC
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What does an IC look like? (3) 45 nm, quad-core Note the symmetry Two dual-cores integrated
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What does an IC look like (3) Actel Fusion Mixed-signal FPGA 1. Integrated Analog-to-Digital Converter (ADC) 2. Fusion Supports Low Power, synchronization 3. Embedded Flash Memory 4. Advanced I/O Standards 5. Charge Pumps 6. Analog Quads 7. Flash FPGA VersaTile 8. SRAM and FIFOs 9. Integrated Oscillators— Crystal and RC 10. Routing Structure 11. JTAG TKT-1426 Lecture 3
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Classification of device technologies Where customization is done: – In the fab (fabrication facility): ASIC (Application Specific IC) • Full-custom ASIC • Standard cell ASIC • Gate array ASIC – Lower density and performance than other ASICs, but more expensive than non-ASIC => obsolete
– In the “field”: non-ASIC • Complex field-programmable logic device • Simple field-programmable logic device – Replaced by CPLD/FPGA
• Off-the-shelf SSI (Small Scaled IC)/MSI (Medium Scaled IC) components – No longer a viable option! TKT-1426 Lecture 3
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ASIC Full-custom – All aspects (e.g., size of a transistor) of a circuit are tailored for a particular application. – Circuit fully optimized – Design extremely complex – Very time consuming design (typically only feasible for small components) – Intel and AMD are partly full-custom
Standard-cell – Circuit made of a set of pre-defined logic, known as standard cells – Layout of a cell is pre-determined, but layout of the complete circuit is customized – Eg. Mobile phone digital ICs
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Complex Field Programmable Logic Device Device consists of an array of generic logic cells and general interconnect structure Logic cells and interconnect can be “programmed” by utilizing “semiconductor fuses” or “switches” Customization is done “in the field” Two categories: – CPLD (Complex Programmable Logic Device) • sea-of-gates to implement logic – FPGA (Field Programmable Gate Array) • Look-up tables to implement logic
No custom mask needed For example, Cisco 2600 series routers
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Comparison of technology Area (Size): silicon real-estate: [mm 2], [eq. gates] Speed (Performance): [MHz], [op/s] – Operations/second – i.e. Time required to perform a task
Power consumption [mW] Cost [€] Design effort [person-month]
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Comparison of technology Area: ASIC (sc) vs FPGA – Standard cell is the smallest since the cells and interconnect are customized – FPGA is the largest • Overhead for programmability • Capacity cannot be completely utilized – Roughly: FPGA is approximately 35 times larger using the LUTbased logic elements [1] • However, that is not seen by FPGA end users – high volume compensates some costs ($$)
Performance: ASIC (sc) vs FPGA – Roughly: FPGA is between 3.4 to 4.6 times slower, MHz [1] [1] I. Kuon and J. Rose, "Measuring the Gap between FPGAs and ASICs" in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, NO. 2, FEBRUARY 2007, pp. 203 - 215. TKT-1426 Lecture 3
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Cost Types of cost: – Chip design costs • NRE (Non-Recurring Engineering) cost: one-time, per-design cost • Part cost: per-unit cost – Indirect design costs • Lead time: time to get the chip out of the factory • Time-to-market “cost” loss of revenue
Standard cell: high NRE, small part cost and large lead time – Good for large volumes
FPGA: low NRE, large part cost and small lead time – Good for prototypes and small volumes TKT-1426 Lecture 3
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Trend of break-even point shifting when choosing ASIC or FPGA % of projects finished in less than 6 months
concept-toprototype
54%
cost [$]
ASIC
prototype to production
57%
~$20M
FPGA cheaper
ASIC cheaper
FPGA ASIC
trend
~$6M
FPGA concept-toprototype
82%
prototype to production
76%
#chips break even, 100K units
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Summary of technologies Trade-off between optimal use of hardware resource and design effort/cost No single best technology FPGA
ASIC
Tailored Masks
15 or more
Area
Best (smallest)
Speed
Best (fastest)
Power NRE Cost
Best (minimal) Best (smallest)
Per-part Cost
Best (smallest)
Design cost
Best (easiest)
Time-to-market
Best (shortest) TKT-1426 Lecture 3
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