ogic
evelopm ent ApS
LD FPGA Module
www.logic-development.dk +45 70 22 19 44
[email protected]
Features The LD FPGA Module is an easy to integrate FPGA module with Xilinx Spartan3E FPGA and necessary memories to make a FPGA based processor system. • • •
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Small size: 27mm X 64mm. Mounted height on motherboard down to 5mm. FPGA: Xilinx Spartan 3E FPGA. Standard XC3S1200E. Optional XC3S500E and XC3S1600E on request. 3 X 40 pin connectors with 100 free IO connected directly to FPGA o 28 IO’s using 3.3V IO voltage - plus o 36 IO’s with separate IO voltage - plus o 36 IO’s with separate IO voltage DDR SDRAM: 64Mbytes. Typical used for MicroBlaze software SPI Flash: 16Mbytes. Used for FPGA configuration data, application SW and other application data. Clock oscillator: 25MHz Single supply 3.3V (internal voltages made with linear regulators) Evaluation design Xilinx XPS with: o MicroBlaze CPU running at 50MHz. o DDR controller (mpmc). External DDR clock running at 100MHz. o SPI controller with SW drivers possible to read and program the Flash o UART Example of optional interfaces on request: o Ethernet MAC o CAN o UART with custom FIFO size and auto enable for RS485 o And many more Sourcing options: o Independent production supplied with production data (gerber etc.) o Buy assembled and tested modules from Logic Development ApS.
June 25, 2008 LD_FPGA_Module
PROPRIETARY
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ogic
evelopm ent ApS
LD FPGA Module
www.logic-development.dk +45 70 22 19 44
[email protected]
Electrical specifications Conditions: Standard configuration with XC3S1200E and 64Mbytes RAM. Supply 3.3V Min. Typ. Max. Power supply voltage (VCC_IN_3V3) 3.0V 3.3V 3.6V Power consumption active 1, see note 1 1059mW Power consumption active 2, see note 2 851mW Peak current during start-up (during FPGA configuration). 700mA Temperature range. No air flow. Mounted 5mm above PCB -40degC 70degC Start-up, configuration time (from VCC_IN_3V3 rise to DONE 290ms 340ms 390ms high) Oscillator frequency 25MHz – 25MHz 25MHz + 50ppm 50ppm Note 1: Design with Microblaze and DDR controller running DDR RAM test. Microblaze running at 50MHz and DDR clock 100MHz. Note 2: As note 1 but running from internal BRAM (DDR still active but not accessed).
Connector pin outs. The pin out in the three 40 pin connectors are shown in Table 2, Table 3 and Table 4. Pin description Table 1: Pin description. GND VCC_IN_3V3 VCC_OUT_1V2 VCC_OUT_2V5 TMS, TCK, TDI, TDO PROG_B DONE CONA_xx VCC_IO0 VCC_Bxx VCC_IO1 VCC_Cxx
Ground Power supply input Output from internal power supply. Can be used as vcc_io reference. JTAG connected to FPGA. Voltage level is 2.5V, use VCC_OUT_2V5 as reference. Connected to fpga PROG_B and reset generator with open-drain output. Has 5.5kohm pullup. Connect open-drain to reload configuration. Connected to DONE on FPGA – high when FPGA is configured. Connected to FPGA IO bank 2 which is using VCC_IN_3V3 as vcc_io, i.e. all signals is 3.3V. VCC_IO supply for CON_Bxx. See Spartan3E datasheet for details on possible IO standards. Connected to FPGA IO bank 1. VCC_IO supply for CON_Cxx. See Spartan3E datasheet for details on possible IO standards. Connected to FPGA IO bank 0.
June 25, 2008 LD_FPGA_Module
PROPRIETARY
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ogic
evelopm ent ApS
LD FPGA Module
www.logic-development.dk +45 70 22 19 44
[email protected]
Table 2: Connector A (J1) pin out. GND VCC_IN_3V3 TMS TCK TDI TDO CON_A2 CON_A4 CON_A6 CON_A8 CON_A10 CON_A12 CON_A14 CON_A16 CON_A18 CON_A20 CON_A22 CON_A24 VCC_IN_3V3 GND
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
VCC_OUT_1V2 VCC_OUT_2V5 DONE PROG_B CON_A0 CON_A1 CON_A3 CON_A5 CON_A7 CON_A9 CON_A11 CON_A13 CON_A15 CON_A17 CON_A19 CON_A21 CON_A23 CON_A25 CON_A26 CON_A27
Table 3: Connector B (J2) pin out. GND CON_B0 CON_B2 CON_B4 CON_B6 CON_B8 CON_B10 CON_B12 CON_B14 CON_B16 CON_B18 CON_B20 CON_B22 CON_B24 CON_B26 CON_B28 CON_B30 CON_B32 CON_B34 GND
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
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2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
VCC_IO1 CON_B1 CON_B3 CON_B5 CON_B7 CON_B9 CON_B11 CON_B13 CON_B15 CON_B17 CON_B19 CON_B21 CON_B23 CON_B25 CON_B27 CON_B29 CON_B31 CON_B33 CON_B35 VCC_IO1
PROPRIETARY
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ogic
evelopm ent ApS
LD FPGA Module
www.logic-development.dk +45 70 22 19 44
[email protected]
Table 4: Connector C (J3) pin out. GND CON_C0 CON_C2 CON_C4 CON_C6 CON_C8 CON_C10 CON_C12 CON_C14 CON_C16 CON_C18 CON_C20 CON_C22 CON_C24 CON_C26 CON_C28 CON_C30 CON_C32 CON_C34 GND
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
June 25, 2008 LD_FPGA_Module
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
VCC_IO0 CON_C1 CON_C3 CON_C5 CON_C7 CON_C9 CON_C11 CON_C13 CON_C15 CON_C17 CON_C19 CON_C21 CON_C23 CON_C25 CON_C27 CON_C29 CON_C31 CON_C33 CON_C35 VCC_IO0
PROPRIETARY
page 4 of 6
ogic
evelopm ent ApS
LD FPGA Module
www.logic-development.dk +45 70 22 19 44
[email protected]
Mechanical specifications and mounting options The mechanical outline of the module is shown in Figure 1.
Figure 1: Mechanical outline. The module is as standard mounted with Samtec dual row 40 pins 0.050” pitch pin headers (CLP-120-02-L-D). This makes it possible to mount it on the motherboard in a low height option or sky scraper, see Figure 2. Om request it is possible to deliver “solder on” option where the pin header is mounted on the FPGA module which is soldered into the mother board. This increases mechanic stability and lowers the cost.
June 25, 2008 LD_FPGA_Module
PROPRIETARY
page 5 of 6
ogic
evelopm ent ApS
LD FPGA Module
www.logic-development.dk +45 70 22 19 44
[email protected]
5mm
Low profile mounting Samtec: FTS-120-03-L-DV (SMD) Samtec: FTS-120-03-L-D (Through hole) Or other 0.050” pin header
Board saving with components under module
Sky scraper mounting Samtec: FW-20-03-L-D-XXX-065 (SMD) Samtec: FW-20-02-L-D-XXX-065 (Through hole) Or other 0.050” pin header
Delivered with connecters – ready to solder in motherboard Custom height
Solder on mounting Through hole mounting
Figure 2: Mounting options
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