Euro DesignCon 2004 Transition to Surface-Mount: An Analysis of Signal Integrity Improvement versus Manufacturing Concerns in Multi-Gigabit Systems Using High-Density Connectors Chad W. Morgan, Tyco Electronics

Tyco Electronics Communications, Computer, & Consumer Electronics Division Circuits & Design Group P.O. Box 3608 Harrisburg, PA 17105-3608 Tel: (717) 986-3342 Email: [email protected]

Abstract Difficulty in achieving reliable multi-gigabit performance in next generation communications systems has required engineers to closely scrutinize every portion of the physical layer. One area of the physical layer that has received significant attention is signal degradation due to high-density board-to-board connector footprints. These footprints are often a limiting factor in system performance, and one way to improve their performance may be to transition from traditional through-hole technology to surfacemount technology. Such a transition, however, introduces new manufacturing, cost, and assembly concerns and should be considered only when system performance improvement is necessary. In the past, numerous case studies have been presented showing the signal integrity degradation introduced by connector footprints. It is well known that significant insertion loss degradation occurs in footprints with top-layer printed circuit board (PCB) connections due to their highly capacitive via stubs. It is also known that signal degradation occurs in through-the-board, bottom-layer PCB connections that introduce transmission line discontinuities and via-to-via noise. Although both through-hole and surface-mount footprints require vias to reach internal PCB layers, techniques exist for both footprint types to minimize signal degradation. Surface-mount footprints, however, often provide better performance since they allow the usage of smaller vias and connector-independent via patterns. Although surface-mount footprints generally offer signal integrity advantages over through-hole footprints, it is not always clear the extent to which these improvements impact overall system performance. Studies to date have mainly focused on impedance and noise improvements of standalone footprints, without extending this information to a system evaluation. Without such a system evaluation, it is difficult to determine the length or speed at which a given design requires surface-mount connector footprints for proper operation. This paper quantifies the impact on system performance that occurs when transitioning from throughhole to surface-mount connector footprint technology. The paper does so by focusing on a carefully selected test case using the Tyco Electronics HM-Zd high-density backplane connector. Both throughhole and surface-mount systems are analyzed at various lengths and speeds in order to quantify the electrical gains that can be made using surface-mount footprints. System analyses are completed for throughput alone, throughput with noise, and throughput with noise and simple equalization. Following system performance quantification, the paper then focuses on outlining connector, PCB, and assembly cost and manufacturing concerns associated with surface-mount technology. The final result of the paper is a comparison of system performance gains to manufacturing concerns associated with surface-mount footprint technology. This comparison should help a system designer decide if and when the transition to surface-mount technology is appropriate.

Author Biography Chad W. Morgan received his BSEE in 1995 from the Pennsylvania State University. Since 1996, he has been an engineer with Tyco Electronics, where he has worked in full-wave electromagnetic modeling of high-speed interconnections, digital systems simulation, systems packaging, material characterization, high-frequency measurement, and technology research. He currently works in the Circuits & Design electrical development group of Tyco Electronics.

Introduction In order to achieve reliable multi-gigabit performance in high-density backplane applications, increasing focus has been placed on minimizing signal degradation resulting from board-to-board connector footprints. One way to improve the signal integrity of these footprints may be to transition from traditional plated through-hole technology (PTH), where the existence of a pressfit or soldered connector pin in the via is implied, to surface-mount technology (SMT), where the connector sits on the surface of the printed circuit board (PCB). Such a transition, however, introduces new manufacturing, cost, and assembly concerns and should be considered only when system performance improvement is necessary. The purpose of this paper is to provide a system signal integrity analysis that quantifies the lengths and speeds at which a transition from PTH to SMT connector footprints should be considered. To do this, data is presented for typical systems that use the Tyco Electronics HM-Zd connector, a prevalent connector in current high-speed systems. Another goal of the paper is to list connector, PCB, and assembly concerns associated with a transition to SMT footprints. The paper begins in the traditional manner by presenting a footprint-only performance comparison. The typical PTH HM-Zd footprint is compared electrically to both a SMT via-in-pad (VIP) HM-Zd footprint and an optimal SMT via-outside-pad (VOP) HM-Zd footprint. Modeled footprint results showing impedance, insertion loss, and noise differences between the footprints serve as a baseline for system electrical comparisons later in the paper. Note that Appendix 1 augments this section of the paper by describing how a single impedance discontinuity generally affects insertion loss. The next section presents footprint-connector-footprint performance data. Again, the PTH HM-Zd footprint is compared electrically to both a SMT VIP HM-Zd footprint and an optimal SMT VOP HMZd footprint. In this section, the electrical analysis is for the concatenated backplane footprint, HM-Zd connector, and daughtercard footprint. Validated model data shows how two footprints interact across a connector to affect overall insertion loss. Note that Appendix 2 supplements this section of the paper by describing how two impedance discontinuities generally affect insertion loss. Focus is then shifted to system performance, where gains achievable by transitioning from PTH footprints to SMT footprints are highlighted. Using the HM-Zd connector and typical system parameters, the lengths and speeds that can be gained by using SMT footprints are quantified. Validated simulations allow speed versus length charts to be shown for throughput-only, throughput with noise, and throughput with noise and equalization. Note that Appendix 3 and Appendix 4 discuss how noise can become increasingly prevalent at higher bit speeds in closing received eye patterns. The paper finishes by presenting connector, PCB, and manufacturing issues associated with the transition to SMT footprints. Appendix 5 also discusses routing advantages that can be gained by using SMT footprints with blind vias and/or quad routing. The end result of the paper is a quantified summary of the system length and/or bit rate at which one should consider using SMT connectors and footprints, along with a list of issues necessary to consider when doing so.

1

Footprint-Only Performance Stand-alone PTH and SMT footprint performance data is included in this section in order to serve as a foundation for understanding system performance differences later in the paper. Within this section, all data was generated using proven, full-wave 3D modeling, which lends itself well to small structures such as connector footprints. In order to compare PTH and SMT footprint performance, the three footprints (each with a BP & DC version) in Figure 1 were chosen and optimized: • The first is the standard HM-Zd PTH footprint. This footprint is heavily defined by the pressfit connector pins themselves, which require the PTHs to have a specific diameter and be at a specific location. Note that the BP & DC footprints are identical for this case. • The second is the HM-Zd SMT VIP footprint. This footprint has surface pad sizes, surface pad locations, and via locations defined by the connector itself. Via diameters, however, can be small in order to optimize electrical performance. A 0.0305 cm (0.012 in) outer via diameter was chosen for the signal vias, because this is near the minimum drill bit size that PCB fabricators consider reasonable. • The third footprint is the HM-Zd SMT VOP footprint. This footprint only has the surface pad size and location defined by the connector itself. Because via placement is independent of the connector, more than ten footprint cases were modeled before the one shown was chosen as the optimal footprint. Again, a 0.0305 cm (0.012 in) outer via diameter was chosen for the signal vias.

DC

BP

(a) PTH

(b) SMT VIP

(c) SMT VOP

Figure 1: HM-Zd footprints for backplane (BP) and daughtercard (DC), (a) Plated through-hole (PTH), (b) Surfacemount via-in-pad (SMT VIP), (c) Surface-mount via-outside-pad (SMT VOP)

2

For the three footprints (each with a BP & DC version) shown in Figure 1, several assumptions were made. First, differential anti-pads were made as large as possible, while still leaving an adequate routing channel for one differential pair using 0.0152 cm (0.006 in) traces and a 0.0229 cm (0.009 in) spacing. Second, a board thickness of 0.381 cm (0.150 in) was chosen with 12 half ounce copper layers (8 ground layers, 4 signal layers). This board thickness was chosen in order to have the thickest board possible, while not violating a 12.5:1 aspect ratio, considering the 0.0305 cm (0.012 in) vias used with both SMT footprints. Note that, although Figure 1 does not show it, each model consisted of one differential pair, surrounded by eight aggressor differential pairs. Refer to Table 1 for all relevant dimensions of the footprints in Figure 1. (cm/in) Signal Drill Diameter Ground Drill Diameter Signal Surface Pad Size Ground Surface Pad Size Bottom/Internal Pad Size Via Offset Distance Basic HM-Zd Dimensions:

PTH BP/DC 0.07 (0.028) 0.07 (0.028) 0.10 (0.039) ∅

SMT VIP BP SMT VIP DC SMT VOP BP SMT VOP DC 0.03 (0.012) 0.03 (0.012) 0.03 (0.012) 0.03 (0.012) 0.07 (0.028) 0.07 (0.028) 0.07 (0.028) 0.07 (0.028) 0.10 (0.039) X 0.06 (0.024) X 0.10 (0.039) X 0.06 (0.024) X 0.10 (0.039) 0.09 (0.035) 0.10 (0.039) 0.09 (0.035) 0.10 (0.039) ∅ 0.10 (0.039) ∅ 0.10 (0.039) ∅ 0.10 (0.039) ∅ 0.10 (0.039) ∅ 0.10 (0.039) ∅ 0.06 (0.024) ∅ 0.06 (0.024) ∅ 0.06 (0.024) ∅ 0.06 (0.024) ∅ 0 0 0 0.08 (0.032) 0.06 (0.024) 0.25 (0.098) x 0.15 (0.059) Via Spacing – Differential 0.16 (0.063) x 0.343 (0.135) a/p

Table 1: Plated through-hole and surface-mount footprint dimensions

Figure 2 shows the differential insertion loss, differential return loss, and time-domain impedance profiles for the PTH and SMT footprints, assuming through-the-board propagation. Note that the PTH BP and PTH DC footprints are identical, so only one series is included for PTH footprints. It should be clear that there is a throughput performance advantage gained going from PTH to SMT footprints. In fact, given a 30 ps edge rate, the 68 Ohm PTH footprint impedance can be improved to ~93 Ohms using any of the SMT footprints. In the frequency domain, this results in ~10% improvement in insertion loss at ~8 GHz. This performance improvement is the direct result of being able to use smaller diameter signal vias in the SMT footprints. Interestingly, there are not substantial throughput differences between the various SMT footprints, especially below 8 GHz. The SMT VIP footprints are slightly better than the SMT VOP footprints, and the SMT DC footprints are slightly better than the SMT BP footprints (because the surface pads are smaller), but the electrical differences are minor.

SMT VOP BP

SMT VIP BP SMT VIP DC

PTH BP/DC

Magnitude

0.8 0.6 0.4 0.2

2

4

6

8

10

12

14

16

18

100 90 80 70 60 1.75

0.0 0

SMT VOP DC

110 Impedance (Ohms)

1.0

SMT VOP BP

SMT VIP BP SMT VIP DC

PTH BP/DC

SMT VOP DC

20

1.80

1.85

1.90

1.95

2.00

2.05

Time (ns)

Frequency (GHz)

(a)

(b)

Figure 2: Footprint-only, through-the board, (a) Differential insertion and return loss, (b) Differential time-domain impedance profiles (30 ps, 20-80%)

3

Figure 3 shows differential near-end noise (NEN) for the PTH and SMT footprints, assuming throughthe-board propagation. Note that Figures 3a and 3b both show total NEN, meaning that eight differential aggressors are added together (two in-row, two in-column, and four diagonal aggressors). Figure 3a was created by adding all eight complex differential NEN s-parameter sweeps, meaning that the noise shown is total synchronous noise for each footprint. Figure 3b was created by adding all eight time-domain noise waveforms with aggressor edges reaching the footprint at the same time. This means that the noise shown in Figure 3b is also total synchronous noise for each footprint. Table 2 reports asynchronous time-domain NEN, which is calculated by adding the peak absolute values from each of the eight aggressors. Note that most of the HM-Zd footprint NEN is in-row noise. Be aware that Figure 3b and Table 2 report total NEN as a percentage. As is industry-standard, this number is calculated by dividing the total differential NEN voltage by the total differential input voltage (Appendix 3 shows that eye closure is actually twice this number). All time-domain noise plots in the footprint and footprint-connector-footprint sections of this paper are reported this way.

SMT VOP BP

SMT VIP BP SMT VIP DC

PTH BP/DC

0.08

SMT VOP DC

1.5 1.0 Percent

0.06 Magnitude

SMT VOP BP

SMT VIP BP SMT VIP DC

PTH BP/DC

SMT VOP DC

0.04 0.02

0.5 0.0 -0.5

0.00

-1.0 0

2

4

6

8

10

12

14

16

18

20

1.4

1.5

1.6

Frequency (GHz)

1.7

1.8

1.9

2.0

Time(ns)

(a)

(b)

Figure 3: Footprint-only, through-the board, synchronous, (a) Total differential NEN versus frequency, (b) Total differential NEN versus time (30 ps, 20-80%) PTH BP/DC

VIP BP

VIP DC

VOP BP

VOP DC

1.13%

1.05%

1.2%

1.06%

1.04%

Table 2: Footprint-only, through-the-board, asynchronous - Total differential NEN (30 ps, 20-80%)

Figure 3a shows that there is little difference in NEN between the PTH and SMT footprints to about 6 GHz. Translating to the time-domain, Figure 3b and Table 2 also confirm that there is little difference in NEN between the PTH and SMT footprints, even with a 30 ps edge stimulus. Given a faster edge rate, Figure 3a data above 6 GHz predicts that the PTH footprint NEN will become worse than the SMT footprint NEN. However, given a 30 ps edge rate, there is little difference in NEN between the PTH and SMT footprints. Although it is somewhat surprising that the SMT NEN is not lower, due to the smaller signal via diameters and increased edge-to-edge signal spacing, it is reasonable to assume that the noise is not lower because the SMT signal vias are also farther from the ground vias.

4

Figure 4 shows differential far-end noise (FEN) for the PTH and SMT footprints, assuming throughthe-board propagation. As was described for Figure 3 NEN, Figure 4 FEN is reported as total, synchronous FEN. Table 3 then reports total, asynchronous time-domain FEN, which is again calculated by adding the peak absolute values from each of the eight aggressors. Note that most of the HM-Zd footprint FEN is in-row noise.

SMT VOP BP

SMT VIP BP SMT VIP DC

PTH BP/DC

0.08

SMT VOP BP

SMT VIP BP SMT VIP DC

PTH BP/DC

SMT VOP DC

SMT VOP DC

0.5 0.0 Percent

Magnitude

0.06 0.04 0.02

-0.5 -1.0 -1.5 -2.0

0.00

-2.5 0

2

4

6

8

10

12

14

16

18

20

1.4

1.5

1.6

Frequency (GHz)

1.7

1.8

1.9

2.0

Time(ns)

(a)

(b)

Figure 4: Footprint-only, through-the-board, synchronous, (a) Total differential FEN versus frequency, (b) Total differential FEN versus time (30 ps, 20-80%) PTH BP/DC

VIP BP

VIP DC

VOP BP

VOP DC

2.01%

1.25%

1.12%

1.52%

1.59%

Table 3: Footprint-only, through-the-board, asynchronous – Total differential FEN (30 ps, 20-80%)

Figure 4a shows that there is little difference in FEN between PTH and SMT footprints to about 10 GHz. In this case, however, Figure 4b and Table 3 show that a translation to the time-domain reveals subtle differences in FEN between the PTH and SMT footprints. Given a 30 ps stimulus, PTH total FEN is ~2% while the SMT VIP total FEN is ~1.2%. If a faster edge rate is used, Figure 4a data above 10 GHz predicts that the difference in FEN between the PTH and SMT footprints should become larger. However, given a 30 ps edge rate, there is only 0.8% difference in FEN between the PTH and SMT footprints. To this point, footprint data has been reported for through-the-board propagation only. This is intentional, because this paper assumes that footprint via stubs will not be allowed in high-speed systems considering SMT footprints. Under this assumption, through-the-board propagation is the worst-case scenario. Throughout this paper, only through-the-board propagation will be analyzed. The assumption that via stubs will not be tolerated in high-speed systems is justifiable for several reasons. First, in systems where the extra cost of SMT footprints is seriously being considered for electrical performance improvements, via stubs are likely to have already been removed (relative to additional cost, the performance gain of removing stubs is far greater than that of transitioning to SMT footprints). Second, whether using PTH or SMT footprints, system performance becomes unacceptably poor when stubs are allowed. As an example, refer to Figure 5, which shows the footprint performance of PTH and SMT footprints with a top-layer connection that includes a via stub. System performance when stubs are present becomes intolerable around 8 GHz. In the time-domain, the presence of via stubs, with either PTH or SMT footprints, causes impedance to dip to ~60 Ohms. 5

SMT VOP BP

SMT VIP BP SMT VIP DC

PTH BP/DC

Magnitude

0.8 0.6 0.4 0.2

2

4

6

8

10

12

14

16

18

100 80 60 40 1.75

0.0 0

SMT VOP DC

120 Impedance (Ohms)

1.0

SMT VOP BP

SMT VIP BP SMT VIP DC

PTH BP/DC

SMT VOP DC

20

1.80

1.85

1.90

1.95

2.00

2.05

Time (ns)

Frequency (GHz)

(a)

(b)

Figure 5: Footprint-only, top with via stub, (a) Differential insertion and return loss, (b) Differential time-domain impedance profiles (30 ps, 20-80%)

Within this footprint-only analysis section, the HM-Zd footprint in a 0.381 cm (0.150 in) thick PCB was examined under three configurations, traditional plated through-hole (PTH), surface-mount via-in-pad (SMT VIP), and surface-mount via-outside-pad (SMT VOP). Examination of through-the-board data highlights several key points: •

HM-Zd SMT footprints provide throughput improvement over the HM-Zd PTH footprint. This improvement is due to the SMT footprint smaller signal vias. The amount of throughput improvement in an overall system will be examined later in the paper.

•

Whether using HM-Zd SMT VIP or HM-Zd SMT VOP footprints, throughput and noise are fairly similar. When using an HM-Zd SMT footprint, it is best to use the most routable footprint, which, in this case, is the HM-Zd SMT VIP footprint.

•

HM-Zd SMT footprints provide little NEN or FEN improvement over the HM-Zd PTH footprint.

•

Using HM-Zd SMT footprints (and their smaller vias) does not eliminate the need to remove via stubs in high-speed systems.

Before proceeding on to the footprint-connector-footprint section, note that Appendix 1 gives a useful summary on the effect of a single, distributed impedance discontinuity on insertion loss.

6

Footprint-Connector-Footprint Performance Footprint-connector-footprint data is presented in this section as a second building block for analyzing overall system performance differences later in the paper. Because PTH and SMT footprints are always used in conjunction with a given connector, it is useful to understand footprint-connector-footprint behavior before adding in other system variables, such as inter-connector resonances and/or trace loss.

(a)

(b)

Figure 6: HM-Zd footprint-connector-footprint, (a) Full-wave 3D model, (b) Validation test board

Results in this section were generated from the following three footprint-connector-footprint models: • • •

HM-Zd BP PTH Footprint / HM-Zd Connector EF Pair / HM-Zd DC PTH Footprint HM-Zd BP SMT VIP Footprint / HM-Zd Connector EF Pair / HM-Zd DC SMT VIP Footprint HM-Zd BP SMT VOP Footprint / HM-Zd Connector EF Pair / HM-Zd DC SMT VOP Footprint

Figure 6a shows an example of a footprint-connector-footprint model. Note that the footprint models are the same as those presented in the previous footprint-only section. The connector model is for the HM-Zd connector EF pair in an interior column of the 4-pair connector.

SMT VIP Measurement

SMT VIP Model

SMT VIP Model - NEN SMT VIP Model - FEN

4

110

2

100

Percent

Impedance (Ohms)

120

SMT VIP Meas - NEN SMT VIP Meas - FEN

90 80

0 -2 -4

70 60

-6 1.6

1.8

2.0

2.2

2.4

2.6

1.4

Time (ns)

1.6

1.8

2.0

2.2

2.4

Time (ns)

(a)

(b)

Figure 7: Footprint – connector – footprint modeled versus measured correlation, (a) Differential impedance profile (30 ps, 20-80%), (b) Total synchronous NEN and FEN (30 ps, 20-80%)

7

As Figure 6b shows, validation boards were constructed for each of the three footprint-connectorfootprint models used to present data in this section. In general, modeled and measured data correlated very well, as shown by the waveforms in Figure 7. Figure 7a shows the modeled versus measured correlation of the SMT VIP impedance profile, driven from the backplane side. Figure 7b shows the modeled versus measured correlation of the SMT VIP near- and far-end noise. Correlation was extremely good, with small differences occurring due to the 20 GHz upper frequency bound of the models. SMT VIP

PTH

SMT VOP

120

0.8

110

Impedance (Ohms)

Magnitude

PTH

1.0

0.6 0.4 0.2

SMT VIP

SMT VOP

100 90 80 70 60

0.0 0

2

4

6

8

10

12

1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7

14

Time (ns)

Frequency (GHz)

(a)

(b)

Figure 8: Footprint-connector-footprint, through-the-board, (a) Differential insertion and return loss, (b) Differential time-domain impedance profiles (30 ps, 20-80%)

Figure 8 shows the differential insertion loss, differential return loss, and time-domain impedance profiles for the three footprint-connector-footprint models, assuming through-the-board propagation. As Figure 8a shows, there is still a throughput advantage gained from using SMT footprints in place of PTH footprints. This improvement is also reflected in Figure 8b, which shows a 15 Ohm impedance improvement going from PTH to SMT footprints. Note that there is little difference in throughput or impedance between the different SMT footprints. It is important to realize that the insertion loss improvement going from PTH to SMT footprints, for footprint-connector-footprint data, is actually twice the improvement seen for a stand-alone footprint (Figure 2a showed ~10% improvement while Figure 8a shows ~20% improvement). The reason for the larger difference is that the footprint-connector-footprint PTH data has nulls that are twice as low as the footprint-only PTH data. The PTH nulls in the footprint-connector-footprint data are twice as low because the two PTH footprint discontinuities on each side of the connector can resonate with one another. When examining how footprint impedances can degrade overall insertion loss, consideration must be given to how two impedance discontinuities can interact across a short length of transmission line, such as a connector. This topic is addressed in Appendix 2. Figure 8b shows the impedance profiles driven from the backplane side of the HM-Zd connector. At first glance, Figure 8b impedances appear to be slightly different than those reported in the footprintonly section. However, upon further inspection, Figure 8b actually agrees well with footprint-only impedances. One must remember that connector impedances are now included in the profile and that the daughtercard-side impedances are no longer fully resolved. It is the connector’s inclusion that makes the backplane-side SMT footprint impedances appear as if they are ~8 Ohms low, and it is the lack of resolution on the daughtercard-side that makes all impedances appear high. 8

Figure 9 shows differential NEN for all three footprint-connector-footprint models, assuming throughthe-board propagation. Figure 9 shows total, synchronous NEN and Table 4 reports maximum total, asynchronous NEN. All values are calculated in the same manner as they were for the footprint-only section of the paper. Note that most of the total noise for each of the footprint-connector-footprint models is in-row noise.

PTH

SMT VIP

SMT VOP

4 3 Percent

0.3 Magnitude

SMT VIP

PTH

SMT VOP

0.4

0.2 0.1

2 1 0

0.0

-1 0

2

4

6

8

10

12

14

1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4

Frequency (GHz)

Time (ns)

(a)

(b)

Figure 9: Footprint-connector-footprint, through-the-board, synchronous, (a) Total differential NEN versus frequency, (b) Total differential NEN versus time (30 ps, 20-80%) PTH

VIP SMT

VOP SMT

4.48%

3.80%

3.66%

Table 4: Footprint-connector-footprint, through-the-board, asynchronous - Total differential NEN (30 ps, 20-80%)

Figure 9a shows that there is little difference in NEN between the PTH and SMT footprint-connectorfootprint models to about 8 GHz, at which point, there becomes a substantial high-frequency difference. Translating to the time-domain, Figure 9b and Table 4 show that the PTH footprint-connector-footprint model has ~0.8% more NEN than the SMT footprint-connector-footprint models, due to a narrow noise spike in the PTH response near the daughtercard-side footprint. It is likely that the 8-10 GHz PTH noise spike is the source of the narrow time-domain noise spike. Overall, there is little difference in NEN between the VIP and VOP footprint-connector-footprint models, and there is only ~0.8% difference in NEN between the PTH and SMT footprint-connector-footprint models. Figure 10 shows differential FEN for all three footprint-connector-footprint models, assuming throughthe-board propagation. Figure 10 shows total, synchronous FEN and Table 5 reports maximum total, asynchronous FEN. All values are calculated in the same manner as they were for the footprint-only section of the paper. As with footprint-connector-footprint NEN, most FEN is in-row.

9

PTH

SMT VIP

SMT VIP

PTH

SMT VOP

SMT VOP

2

0.4

1 Percent

Magnitude

0.3 0.2 0.1

0 -1 -2 -3

0.0

-4 0

2

4

6

8

10

12

14

1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4

Frequency (GHz)

Time (ns)

(a)

(b)

Figure 10: Footprint-connector-footprint, through-the-board, synchronous, (a) Total differential FEN versus frequency, (b) Total differential FEN versus time (30 ps, 20-80%) PTH

VIP SMT

VOP SMT

3.91%

4.21%

4.38%

Table 5: Footprint-connector-footprint, through-the-board, asynchronous - Total differential FEN (30 ps, 20-80%)

Figure 10a shows that there is little difference in FEN between PTH and SMT footprint-connectorfootprint models to about 8.5 GHz, at which point there is a small increase in PTH FEN over both SMT FEN waveforms. Translating to the time-domain, Figure 10b and Table 5 show that all three footprintconnector-footprint models have very similar FEN. Interestingly, both SMT footprint-connectorfootprint models have slightly more FEN than the PTH footprint-connector-footprint model. This is different than in the footprint-only section because the footprint-connector-footprint models include a very short amount of trace route over the footprint differential anti-pads, whereas the stand-alone footprints did not. Including this short amount of highly inductive trace route causes the SMT footprintconnector-footprint FEN to look higher than the PTH footprint-connector-footprint FEN, because the trace has to route slightly further in the SMT models to get to the smaller signal vias. Ultimately, the FEN for the three different models is extremely similar. As was explained in the footprint-only section of the paper, only through-the-board data will be included in the system analysis portion of this paper. This paper assumes that high-speed systems cannot tolerate via stubs, in which case through-the-board performance data is the worst-case scenario. Figure 5 in the footprint-only section of the paper showed that footprints with top-layer connections and via stubs perform extremely poorly. Figure 11 reinforces the poor performance of footprints with via stubs by plotting this type of connection for the three footprint-connector-footprint models listed in this section. Whether using a SMT or PTH footprint-connector-footprint, via stubs degrade performance substantially. The remainder of the paper will be for through-the-board connections.

10

SMT VIP

PTH

Impedance (Ohms)

0.8 Magnitude

SMT VIP

PTH

SMT VOP

1.0

0.6 0.4 0.2

SMT VOP

120 110 100 90 80 70 60 50 40

0.0 0

2

4

6

8

10

12

1.5

14

1.7

1.9

2.1

2.3

2.5

2.7

Time (ns)

Frequency (GHz)

(a)

(b)

Figure 11: Footprint-connector-footprint, top with via stub, (a) Differential insertion loss, (b) Differential timedomain impedance profiles (30 ps, 20-80%)

Within this footprint-connector-footprint section of the paper, both PTH and SMT footprints were concatenated to each side of the HM-Zd connector, and the overall response of each combination was examined. Examination of through-the-board footprint-connector-footprint data has revealed the following key points: •

HM-Zd SMT footprints provide throughput improvement over the HM-Zd PTH footprint. This improvement is due to the smaller signal vias in the SMT footprints. Throughput improvement for footprint-connector-footprint is more significant than for a stand-alone footprint. The improvement in an overall system will be examined later in this paper.

•

Footprint-connector-footprint throughput and noise are fairly similar for the HM-Zd SMT VIP footprint and the HM-Zd SMT VOP footprint. When using an HM-Zd SMT footprint, it is best to use the most routable footprint, which, in this case, is the HM-Zd SMT VIP footprint.

•

HM-Zd SMT footprints provide little NEN improvement over the HM-Zd PTH footprint in a footprint-connector-footprint response. HM-ZD SMT footprints actually have more FEN than the HM-Zd PTH footprint in a footprint-connector-footprint response since some trace route over the anti-pad is included.

•

Using HM-Zd SMT footprints (and their smaller vias) does not eliminate the need to remove via stubs in high-speed systems. Footprint-connector-footprint data confirms this point.

Before proceeding to the system analysis section, note that Appendix 2 gives a useful summary on the effect of two impedance discontinuities on overall insertion loss.

11

System Performance Although footprint-only and footprint-connector-footprint electrical comparisons are useful, a full system signal integrity analysis is ultimately required in order to decide if and when SMT footprint advantages become significant enough to warrant a transition from traditional PTH footprints. To complete such an analysis, it would be ideal to examine all potential system variables. However, today’s systems include many permutations, including connector choice, board connection method, footprint geometry, board thickness, layer connection, trace length, trace width, dielectric material, etc. Since all system variables cannot be covered in one paper, a typical system, shown in Figure 12, was selected for this paper. The goal is for this system to be as representative of today’s systems as possible.

Figure 12: Typical system used to compare SMT footprint performance to PTH footprint performance at various lengths and speeds

As with the footprint-only and footprint-connector-footprint sections, the HM-Zd connector EF pair was selected for analysis. Also, both the backplane and daughtercard stackups remain 0.381 cm (0.150 in) thick with 8 ground layers and 4 signal layers. As Figure 12 shows, all differential pairs consist of 0.015 cm (0.006 in) traces with 0.023 cm (0.009 in) spaces. These differential pairs are routed on the bottom signal layer of both the backplane and daughtercard, since this layer connection is assumed to be the worst-case scenario in the absence of via stubs. Both the backplane and daughtercard are constructed from Nelco 4000-6 FR4 material. System simulations are completed for both PTH and SMT footprints in order to compare their performance. In order to compare footprint performance for as many systems as possible, both PTH and SMT systems were simulated at numerous system lengths, ranging from 22.86 cm (9.0 in) to 152.4 cm (60.0 in). For simplicity, system length is varied by keeping both daughtercard lengths fixed at 10.16 cm (4.0 in) while varying the backplane length from 2.54 cm (1.0 in) to 132.08 cm (52.0 in). The goal of the system simulation study is to compare, for a given system length, the bit rate at which an SMT footprint fails to the bit rate at which a PTH footprint fails. To achieve this goal, a PRBS 27-1 bit pattern with a 25 ps edge was chosen as the input stimulus. This pattern was chosen because it is more worst-case than 8B/10B encoding, and because it is practical to simulate in a reasonable time. The XFP eye mask was chosen as the failure criteria at the receiver. The XFP standard specifies that the received eye pattern must be at least 110 mV open and have less than 65% unit interval zero-crossing jitter. It also specifies that overshoot and undershoot must not exceed +/-525 mV. 12

Given all of the system criteria already listed, the comparison of SMT footprints to PTH footprints in typical systems is completed in the upcoming sections. These comparisons are completed for throughput-only data, throughput with noise data, and throughput with noise and equalization data. For each section, the method of analysis is the same. First, a given footprint and system length is selected, and a given bit speed is sent through the system with that footprint and system length. Then, the output eye pattern is evaluated, using the XFP receiver eye mask. Finally, the bit rate is increased until the output eye pattern for the chosen system fails the XFP receiver mask. This failure speed is then recorded and plotted versus the given system length for that footprint. Note that all reported results were completed through simulation by concatenating the models from the footprint-connector-footprint section of this paper with differential pair trace models that accurately included the effects of dielectric constant dispersion and loss tangent variability. Although simulations were required, due to the numerous system lengths included, system test boards were built to verify simulation results for carefully selected system lengths. As shown in Figure 13, simulation validation was completed using a system test board for the PTH, SMT VIP, and SMT VOP footprints at system lengths of 30.48 cm (12.0 in) and 81.28 cm (32.0 in). Figure 13a shows network analyzer, frequencydomain verification, and Figure 13b shows multi-line bit pattern, time-domain verification.

(a)

(b)

Figure 13: PTH and SMT footprint system validation boards, (a) Frequency-domain testing to 20 GHz with Agilent 8720ES VNA, (b) Time-domain testing with multiple 12.5 Gbps generators and Agilent DCA-J

In the following sections, system failure speed versus system length results will be reported for both PTH and SMT footprints assuming throughput-only, throughput with noise, and throughput with noise and equalization. Before each of these sections, several charts are included that show simulated versus measured data correlation. These charts should give a high degree of confidence that simulated results accurately predict the behavior of all included system lengths.

13

Throughput-Only System Performance This section of the paper compares PTH to SMT system performance, assuming that only one differential pair is driven without the presence of noise. Although this assumption is not realistic, the results allow an understanding of the fundamental differences in throughput for typical systems using either PTH or SMT footprints. As already described, all results were simulated, but validation was completed for several key system lengths using the system test boards shown in Figure 13. Before proceeding to the throughput-only results, several validation points are given. SMT VIP Model

SMT VIP Meas

1.0

Magnitude

0.8 0.6 0.4 0.2 0.0 0

2

4

6

8

10

12

14

16

18

20

Frequency (GHz)

(a)

(b)

(c)

Figure 14: Simulated versus measured validation data example – 30.48 cm (12.0 in) SMT VIP system – bottom layer, (a) Differential insertion loss, (b) Simulated eye pattern at 12.5 Gbps, (c) Measured eye pattern at 12.5 Gbps

Figure 14 shows the simulated versus measured data for a 30.48 cm (12 in) system that uses the SMT VIP HM-Zd footprints. Figure 14a shows the differential insertion loss of both the simulated and measured systems. The differential insertion loss correlation is extremely good; the only discrepancies seen are small frequency shifts between the measured and simulated resonance ripples. These discrepancies are attributable to small dielectric constant differences between the simulated and measured PCBs of the system. Figures 14b and 14c show the simulated and measured eye patterns for a 12.5 Gbps signal at the receiver (along with the XFP receiver mask). In this case, eye pattern shape and overall opening agree reasonably well. However, there are differences between the two eye patterns. For example, the simulated eye pattern on the left is 19.1% open with 31.2% jitter while the measured eye pattern on the right is 14.3% open with 45.0% jitter. The discrepancy is directly attributable to imperfections in the bit pattern generator used to create the measured eye. Examination of the generator showed undershoot and up to 8 ps of jitter. In general, simulation results used a cleaner bit source and are more likely to represent a well-implemented chip output. 14

PTH Model

PTH Meas

1.0

Magnitude

0.8 0.6 0.4 0.2 0.0 0

2

4

6

8

10

12

14

16

18

20

Frequency (GHz)

(a)

(b)

(c)

Figure 15: Simulated versus measured validation data example – 81.28 cm (32.0 in) PTH system – bottom layer, (a) Differential insertion loss, (b) Simulated eye pattern at 3.125 Gbps, (c) Measured eye pattern at 3.125 Gbps

Figure 15 shows another example of validation data, this time for an 81.28 cm (32.0 in) system that uses the PTH HM-Zd footprint. Figure 15a shows the differential insertion loss of both the simulated and measured systems. Again, the differential insertion loss correlation is extremely good; the only discrepancy seen is slightly more loss in the measured system. This extra loss was found to be from a small loss tangent difference between the measured system PCBs and the loss tangent values used to simulate those PCBs. Figures 15b and 15c show the simulated and measured eye patterns for a 3.125 Gbps signal at the receiver. As with Figures 14b and 14c, eye pattern shape and overall opening agree well, but measured opening and jitter values are slightly different. The simulated eye had a 38.4% opening and 21.9% jitter, while the measured eye had 35.9% opening and 27.0% jitter. Again, the difference between the two is due to imperfections in the bit generator used during measurement. Having gained confidence in simulation results, simulations were then completed to determine the bit rates at which typical systems of different lengths failed the XFP receiver mask for both PTH and SMT footprint systems. These results are shown in Figure 16. To use Figure 16, simply pick a system length of interest and then examine the series on the chart for a specific footprint to determine the bit rate at which that length and footprint fails the XFP mask. Any bit rate below the failure rate works for the footprint and length chosen, while any bit rate above the failure rate does not work for the footprint and length chosen.

15

SMT VIP

PTH

SMT VOP

18 Speed (Gbps)

16 14 Eye Fails XFP Mask

12 10 8 Eye Passes XFP Mask

6 4 2 15

35

55

75

95

115

135

155

Length (cm) 6

16

26

36

46

56 61

Length (in) Figure 16: Throughput-only eye pattern failure speed versus given system length for PTH, SMT VIP, and SMT VOP systems (No noise, no equalization)

Given throughput-only and typical system parameter assumptions, Figure 16 quantifies the electrical performance improvement that can be expected in a system that transitions from PTH to SMT footprints. The chart is meant to show the speed improvement achievable for a given system length but can also be used to extrapolate the extra distance achievable for a given bit rate. For example, given a 22.86 cm (9.0 in) system length, a system can run over 5 Gbps faster by using SMT footprints (12.25 Gbps to >17.25 Gbps). At a longer system length, such as 81.28 cm (32.0 in), systems can run about 500 Mbps faster by going to SMT footprints (5.5 Gbps to 6 Gbps). Looking at distance gains for a given bit rate, one can go about 15.24 cm (6.0 in) farther at 12.5 Gbps using SMT footprints (22.86 cm (9.0 in) to 38.1 cm (15.0 in)). It should be apparent that there is definitely a throughput advantage for SMT footprint systems over PTH systems. However, most of this improvement is at shorter system lengths, where trace loss is not the dominating factor in system performance. At shorter system lengths, PTH footprint resonances clearly degrade differential insertion loss while SMT footprints allow differential insertion loss to remain smooth. This effect can be seen with the top three series, representing a 22.86 cm (9.0 in) system length, in Figure 17a. At longer lengths, such as 81.28 cm (32.0 in) or 152.4 cm (60.0 in), PTH resonances become damped by trace loss. At these longer lengths, the PTH response then approaches the SMT response. This effect is also shown by Figure 17a. Figure 17b shows how PTH resonances become minimized as overall system length increases. 16

SMT VIP

PTH

SMT VOP

1.0

0.8

0.8 Magnitude

Magnitude

PTH

1.0

0.6 0.4 0.2

0.6 0.4 0.2

0.0

0.0

0

2

4

6

8

10

12

14

16

18

0

20

2

4

6

8

10

12

14

16

18

20

Frequency (GHz)

Frequency (GHz)

(a)

(b)

Figure 17: Differential insertion loss plots, (a) PTH, SMT VIP, and SMT VOP system lengths of 22.86 cm (9.0 in), 81.28 cm (32.0 in), and 152.4 cm (60.0 in), (b) PTH system lengths of 22.86 cm (9.0 in) through 152.4 cm (60.0 in)

Figures 16 and 17 clearly show that SMT footprints offer more improvement over PTH footprints at short system lengths. This statement can be extended to say that SMT footprints offer more signal integrity benefit when the overall system loss is low. As a result, wider traces and lower loss dielectric materials will also make the difference between PTH and SMT footprints more apparent. Note that there is little performance difference between the SMT VIP and SMT VOP systems for throughput alone. This result is consistent with footprint-connector-footprint data, which showed little impedance difference between the various SMT footprints. If using SMT HM-Zd footprints, the most routable footprint should be chosen, which, in this case, is the SMT VIP footprint.

17

Throughput with Noise System Performance This section of the paper builds upon throughput-only data by quantifying system throughput in the presence of either near- or far-end noise. In any real system, multiple signals switch simultaneously, so the effects of noise must be considered when comparing the performance of systems using PTH and SMT footprints. Note that time-domain noise considered in this section, and reported on the bit-speed versus length charts, is total, asynchronous noise since it is calculated by adding the peak absolute values from each of eight surrounding aggressor differential pairs. By calculating total, asynchronous noise in this manner, results reflect worst-case eye closure with no consideration of probabilistic factors, such as the number of bits or time necessary to reach the peak noise value. As with throughput-only data, all results were simulated, but validation was completed for several key system lengths using the system test boards shown in Figure 13. Before presenting the bit-speed versus length charts for throughput with near end noise and throughput with far end noise, several validation points are given.

SMT VIP Model

SMT VIP Meas

0.25

Magnitude

0.20 0.15 0.10 0.05 0.00 0

2

4

6

8

10

12

14

16

18

20

Frequency (GHz)

(a)

(b)

(c)

Figure 18: Simulated versus measured validation data example – 30.48 cm (12.0 in) SMT VIP system – bottom layer, (a) Total differential synchronous NEN versus frequency, (b) Simulated eye pattern with partial asynchronous NEN at 12.5 Gbps, (c) Measured eye pattern with partial asynchronous NEN at 12.5 Gbps

Figure 18 shows the simulated versus measured throughput with NEN data for a 30.48 cm (12.0 in) system that uses SMT VIP HM-Zd footprints. Throughput correlation has already been shown, so Figure 18a shows the total, synchronous near end noise correlation versus frequency. In general, simulated versus measured data correlation is extremely good, especially below 13 GHz. Figures 18b and 18c show the simulated and measured eye patterns for a 12.5 Gbps signal with partial, asynchronous NEN included. The NEN in Figures 18b and 18c is partial, because only two differential aggressors (one in-row and one in-column) are active. Correlation was completed with partial aggression, due to current test equipment limitations (only three 12.5 Gbps generators). As can be seen at the center of the eye, simulated and measured data correlate well. Note that the expanded swing shown on the measured eye pattern rails is the direct result of overshoot in the real bit pattern generator. 18

PTH Model

PTH Meas

0.05

Magnitude

0.04 0.03 0.02 0.01 0.00 0

2

4

6

8

10

12

14

16

18

20

Frequency (GHz)

(a)

(b)

(c)

Figure 19: Simulated versus measured validation data example – 81.28 cm (32.0 in) PTH system – bottom layer, (a) Total differential synchronous FEN versus frequency, (b) Simulated eye pattern with partial asynchronous FEN at 3.125 Gbps, (c) Measured eye pattern with partial asynchronous FEN at 3.125 Gbps

Figure 19 shows the simulated versus measured throughput with FEN data for an 81.28 cm (32.0 in) system that uses PTH HM-Zd footprints. Figure 19a shows the total, synchronous far end noise correlation versus frequency. In general, simulated versus measured data correlation is extremely good. Figures 19b and 19c show the simulated and measured eye patterns for a 3.125 Gbps signal with partial, asynchronous FEN included. Again, correlation was completed with partial FEN due to test equipment limitations. Similar to previous results, eye pattern shape and overall opening correlate fairly well. In this case, the simulated eye pattern is 36.7% open with 22.5% unit interval zero-crossing jitter while the measured eye pattern is 35.2% open with 27.0% unit interval zero-crossing jitter. Again, the measured eye is slightly more closed and has slightly more jitter due to bit generator imperfections. On the following pages, Figures 20 and 21 show the bit failure speed versus overall system length charts for throughput with near end noise and throughput with far end noise. Throughput with near end noise represents systems where transmit and receive signals are mixed in one area of the connector pinfield. Throughput with far end noise represents systems where transmits are grouped together and receives are grouped together, but transmits and receives are separated from one another and remain in two separate areas of the connector pinfield. Note that Figures 20 and 21 show the original throughput-only data as dotted lines so that the degradation caused by total, asynchronous near- or far-end noise can be seen. A summary of results and source causes is included below both Figure 20 and Figure 21.

19

PTH

SMT VIP

SMT VOP

Speed (Gbps)

18 Solid Lines = Throughput w/ NEN Dotted Lines = Throughput-Only

16 14

Eye Fails XFP Mask

12 10 8 6

Eye Passes XFP Mask

4 2 15

35

55

75

95

115

135

155

Length (cm) 6

16

26

36

46

56 61

Length (in) Figure 20: Throughput with NEN eye pattern failure speed versus given system length for PTH, SMT VIP, and SMT VOP systems (Total asynchronous NEN included, no equalization)

Given typical system parameters and assuming throughput with total, asynchronous near end noise, Figure 20 quantifies the electrical performance improvement that can be expected in a system that transitions from PTH to SMT footprints. Throughput with NEN data is shown as solid lines, while previously reported throughput-only data is shown as dotted lines. The chart is meant to show the speed improvement achievable for a given system length but can also be used to extrapolate the extra distance achievable for a given bit rate. As expected, the inclusion of total, asynchronous NEN causes all systems to fail at lower bit rates than for the same systems without the presence of noise. It is interesting to note, however, that the amount of signal degradation, due to NEN, is higher than one might expect for several reasons. First, system noise causes received eye patterns to close at twice the noise percentage typically reported by the signal integrity industry (differential noise voltage divided by differential source voltage). This topic is discussed in Appendix 3. Second, NEN increases not only with faster edge rate, but also with faster bit speed for the systems simulated in this paper. This topic is addressed in Appendix 4. Because total system NEN is higher at higher bit rates and SMT systems fail at higher bit rates than PTH systems, SMT system bit failure speeds tend to be more degraded by NEN than PTH system bit failure speeds. As a result, the inclusion of NEN makes overall system performance differences between PTH and SMT footprints not as great as they appeared under the throughput-only assumption.

20

SMT VIP

PTH

SMT VOP

18 Solid Lines = Throughput w/ FEN Dotted Lines = Throughput-Only

Speed (Gbps)

16 14 12

Eye Fails XFP Mask

10 8 6

Eye Passes XFP Mask

4 2 15

35

55

75

95

115

135

155

Length (cm) 6

16

26

36

46

56 61

Length (in) Figure 21: Throughput with FEN eye pattern failure speed versus given system length for PTH, SMT VIP, and SMT VOP systems (Total asynchronous FEN included, no equalization)

Given typical system parameters and assuming throughput with total, asynchronous far end noise, Figure 21 quantifies the electrical performance improvement that can be expected in a system that transitions from PTH to SMT footprints. Throughput with FEN data is shown as solid lines, while previously reported throughput-only data is shown as dotted lines. The chart is meant to show the speed improvement achievable for a given system length but can also be used to extrapolate the extra distance achievable for a given bit rate. As expected, the inclusion of total, asynchronous FEN causes all systems to fail at lower bit rates than for the same systems without the presence of noise. As with NEN, it is clear that the amount of signal degradation due to FEN is higher than one might expect. Again, system noise causes received eye patterns to close at twice the noise percentage typically reported by the signal integrity industry. This topic is discussed in Appendix 3. Also, FEN increases not only with faster edge rate, but also with faster bit speed for the systems simulated in this paper. This effect is especially apparent at shorter system lengths and is addressed in Appendix 4. At shorter system lengths, total system FEN is higher for the faster SMT bit failure speeds than total system FEN for the slower PTH bit failure speeds. As a result, SMT system degradation, due to FEN, is higher than PTH system degradation. The result is that the inclusion of FEN makes overall system performance differences between PTH and SMT footprints at shorter lengths not as great as they appeared under the throughput-only assumption. At longer system lengths, trace loss damps away both PTH resonances and most SMT and PTH FEN. As a result, there is little difference in throughput with FEN performance between PTH and SMT systems at longer system lengths. 21

Throughput with Noise and Equalization System Performance As has been shown in the throughput-only section, advantages of SMT footprints over PTH footprints for system performance are more apparent when system loss is low (i.e., short systems, wide traces, low loss dielectrics, etc.). Taken another way, more advantage can be gained by transitioning to SMT footprints when system loss is minimized through some form of equalization. Because equalization, both simple and complex, is growing ever more prevalent in current systems, this section outlines system performance differences between SMT and PTH footprints when throughput with noise and equalization is assumed. Choosing a representative form of equalization can be difficult, because many forms of equalization exist. Popular forms of equalization can be active, passive, analog, or digital. Equalization can be implemented at the transmitter or the receiver and can range from simple high-pass analog filters to more elaborate multi-tap digital filters, such as finite impulse response (FIR) filters or decision feedback equalizers (DFEs). Ultimately, all equalization schemes attempt to multiply the system by its inverse channel response in order to achieve a flat system response versus frequency. This flat response then minimizes inter-symbol interference (ISI), which improves eye opening and jitter. Note that noise must be included in the analysis of any equalization scheme, since equalization typically amplifies noise significantly (though some schemes can avoid this). For this paper, a very simple equalization scheme was selected that makes use of the bridged-T equalizer shown in Figure 22. This bridged-T equalizer implements a simple high-pass filter that always stays impedance-matched to the system impedance. It was selected because it is relatively inexpensive, easily implemented, and reasonably effective. A bridged-T equalizer is a good start for highlighting the differences between SMT and PTH footprint systems where system loss is minimized in the response.

(a)

(b)

Figure 22: Bridged-T equalizer: Matched-impedance, passive-component, high-pass filter, (a) Schematic view, (b) Physical circuit layout

Note that the bridged-T equalizer achieves signal integrity improvement by damping the low-frequency portion of a signal. Since it is passive, an input signal must be overdriven or a receive signal must be amplified in order to achieve the desired eye opening voltage at the receive side of a system. Due to the linear nature of passive systems and the bridged-T equalizer, it does not matter whether the equalization/amplification is done at the transmitter side or receiver side of the circuit. Transmitter-side equalization is often referred to as pre-emphasis, and receiver-side equalization is often referred to as equalization. Both techniques should yield the same performance. 22

Figure 23 shows an example of how a bridged-T equalizer can be optimized and added to a system to improve signal integrity. Figure 23a shows the original channel response (blue), along with the inverse channel response (magenta), which is shifted down for convenience. As Figure 23a shows, the equalizer response (red) is optimized until its slope matches the inverse channel response as closely as possible, without exceeding the inverse channel response slope. The equalizer is then cascaded with the circuit and the overall channel with equalizer response (black) is shown. This response is then amplified up until the eye pattern rails (shown in Figure 23b) just violate the upper/lower XFP mask bounds. Figure 23a shows the final circuit response (green), and Figure 23b shows the difference between a nonequalized eye (blue) and the equalized eye (green) at 5 Gbps. It should be apparent that even simple equalization can dramatically improve the quality of a received eye pattern.

Channel (CH) Response Inverted CH Response Equalizer (EQ) Response Amplified CH + EQ Response Total CH + EQ Response

1.0

Magnitude

0.8 0.6 0.4 0.2 0.0 0

2

4

6

8

10

12

14

Frequency (GHz)

(a)

(b)

Figure 23: Example results for bridged-T equalizer, (a) Channel response, tuned equalizer response, and total channel with equalizer response, (b) Resulting eye pattern improvement at 5 Gbps

Although not immediately apparent, it should be noted that equalizer optimization, in the presence of noise, can become rather complicated. At high bit-speeds, the equalizer response must be matched to the inverse channel response to high frequencies. In order to do this, the equalizer response must start at a relatively low DC value, such as the 0.5 shown above (or lower). At a low DC value, the overall system with equalizer response can approach the noise floor of the system. With noise present in the system, it can become difficult to choose what equalizer DC value will maximize throughput without being too low, such that noise closes the eye upon amplification. As a result, optimization of the equalizer must be done by iteratively choosing equalizer DC values, matching the equalizer response to the inverse channel response, and then evaluating the opening of the system with equalizer eye pattern. The equalizer that yields the most open eye with the minimum jitter is the optimum equalizer for that system and bit speed. In this section, all equalizers were iteratively optimized for each system length and bit speed to be sure that they were optimal. Note that care must be taken when simulating equalizer components. At high frequency, physical parasitics often result in component values, and hence equalizer characteristics, that are different than predicted. Also, self-resonant frequencies (SRF) of capacitors and inductors that are used with the bridged-T equalizer must be avoided. As with other sections of the paper, all work presented here was completed via simulation; however, validation data was collected to be sure that all simulation data was accurate. An example of simulated versus measured data is shown on the following page for system throughput with noise and equalization. 23

Mod EQ Meas EQ

Mod Channel Meas Channel

Mod Channel + EQ Meas Channel + EQ

1.0

Magnitude

0.8 0.6 0.4 0.2 0.0 0

1

2

3

4

5

Frequency (GHz)

(a)

(b)

(c)

Figure 24: Validation example – 81.28 cm (32.0 in) equalized SMT VIP system – bottom layer, (a) Simulated versus measured equalizer, channel, and channel with equalizer frequency responses, (b) Simulated eye pattern with partial asynchronous FEN at 6.25 Gbps, (c) Measured eye pattern with partial asynchronous FEN at 6.25 Gbps

Figure 24 shows the simulated versus measured throughput with FEN and equalization data for an 81.28 cm (32.0 in) system that uses SMT VIP HM-Zd footprints. Figure 24a shows the system response (blues), equalizer response (greens), and system with equalizer response (reds) for both simulated and measured data. To 5 GHz, simulated versus measured data correlation is fairly good. Above 2 GHz, the measured equalizer response is slightly degraded, which causes the measured system with equalizer response to be slightly worse than the simulated system with equalizer response. Degradation in measured equalizer performance is likely due to board and component parasitics. As Figures 24b and 24c show, the simulated eye pattern is 53.9% open with 8.75% UI jitter (2.35 amplification), while the measured eye is 44.1% open with 14.3% UI jitter (2.1 amplification). Beyond the differences shown in Figure 24a, discrepancy between simulated and measured data is largely due to imperfections in the bit pattern generator used during measurement. Even so, note that the eye patterns in Figures 24b and 24c would have been 5% and 0% open, respectively, without equalization. Therefore, simulations have reasonably predicted the effect equalization will have on throughput. On the following pages, Figures 25 and 26 show the bit failure speed versus overall system length charts for throughput with near- or far-end noise and equalization. Note that Figures 25 and 26 show the original throughput-only data and the throughput with noise data as dotted lines so that one can see the improvement offered by simple equalization. 24

PTH

(SMT VOP)

SMT VIP

Speed (Gbps)

18 Solid Lines = Equalized Throughput w/ NEN Dotted Lines = Throughput w/ and w/o Noise (No EQ)

16 14

Eye Fails XFP Mask

12 10 8 6

Eye Passes XFP Mask

4 2 15

35

55

75

95

115

135

155

Length (cm) 6

16

26

36

46

56 61

Length (in) Figure 25: Equalized throughput with NEN eye pattern failure speed versus given system length for PTH and SMT VIP systems (Total asynchronous NEN included, bridged-T equalization)

Given typical system parameters and equalized throughput with total, asynchronous near end noise, Figure 25 quantifies the electrical performance improvement that can be expected in a system that transitions from PTH to SMT footprints. Equalized throughput with NEN data is shown as solid lines, while previously reported throughput-only and throughput with NEN data is shown as dotted lines. The chart is meant to show the speed improvement achievable for a given system length but can also be used to extrapolate the extra distance achievable for a given bit rate. Note that SMT VOP footprint data is not included, since SMT VOP performance is very similar to SMT VIP performance. As expected, the inclusion of optimized, passive equalization results in improved system performance for both the PTH and SMT VIP systems. In fact, at longer system lengths, equalized throughput with NEN performance is actually better than throughput-only performance. It is important to note that equalization helps SMT VIP system performance more than PTH footprint system performance. For example, equalization allows a 22.86 cm (9.0 in) system to go almost 7 Gbps faster, using SMT VIP footprints over PTH footprints. Without equalization, but still including NEN, a system can only go about 3 Gbps faster using SMT footprints over PTH footprints. Superior SMT VIP equalization is achievable because the SMT VIP system response is much smoother than the PTH system response. Even at long system lengths, NEN remains present, as described in Appendix 4. As a result, equalization is limited not only by the simplicity of the bridged-T equalizer, but also by an ever-present NEN floor. The presence of NEN inherently limits the amount of simple equalization that can be done.

25

(SMT VOP)

SMT VIP

PTH

Speed (Gbps)

18 Solid Lines = Equalized Throughput w/ FEN Dotted Lines = Throughput w/ and w/o Noise (No EQ)

16 14

Eye Fails XFP Mask

12 10 8 6

Eye Passes XFP Mask

4 2 15

35

55

75

95

115

135

155

Length (cm) 6

16

26

36

46

56 61

Length (in) Figure 26: Equalized throughput with FEN eye pattern failure speed versus given system length for PTH and SMT VIP systems (Total asynchronous FEN included, bridged-T equalization)

Given typical system parameters and equalized throughput with total, asynchronous far end noise, Figure 26 quantifies the electrical performance improvement that can be expected in a system that transitions from PTH to SMT footprints. Equalized throughput with FEN data is shown as solid lines, while previously reported throughput-only and throughput with FEN data is shown as dotted lines. The chart is meant to show the speed improvement achievable for a given system length but can also be used to extrapolate the extra distance achievable for a given bit rate. Note that SMT VOP footprint data is not included, since SMT VOP performance is very similar to SMT VIP performance. As expected, including optimized, passive equalization improves system performance for both the PTH and SMT VIP systems. At longer system lengths, equalized throughput with FEN performance is significantly better than throughput-only performance. Equalization is especially effective at long system lengths because FEN is damped away. As an example, even a 100 cm (39.37 in) SMT VIP system will function at 10 Gbps. Note that, as with NEN, equalization helps SMT VIP system performance more than PTH system performance. This section has shown that simple equalization minimizes system loss. As a result, more improvement can be expected in system performance, going from PTH footprints to SMT footprints, when equalization is employed. The benefits of SMT footprints and simple equalization are more apparent, for longer systems, when transmit signals are grouped. In this case, noise consists primarily of FEN, which tends to be damped away with longer trace lengths. Note that the conclusions here are for simple equalization. Sophisticated equalization schemes may be able to compensate for PTH resonances, in which case the performance differences between PTH and SMT footprints may not be so evident. 26

Surface-Mount Manufacturing Concerns At this point, it has been shown that a transition from PTH to SMT footprints may be required in order to achieve acceptable signal integrity in some systems. Appendix 5 also shows that SMT footprints often provide system cost savings through extra routing channels that reduce PCB layer requirements. Given the apparent advantages of SMT footprints, it is reasonable in some situations to consider switching from traditional PTH footprints to SMT footprints in high-density, multi-gigabit systems. However, before doing so, the manufacturing concerns associated with surface-mount technology must be considered. This section of the paper outlines connector, PCB, and assembly manufacturing concerns associated with SMT footprints. Connectors High-density, high-speed SMT connectors must be implemented carefully to ensure mechanical reliability. The following issues should be considered when evaluating a SMT connector: • Reliability: Because soldered SMT parts are not the traditional solution in high-density, highspeed board-to-board interconnections, long term reliability is unproven. Short term systems have yielded promising results, but few, if any, high-density SMT connectors have been in operation long. Studies on sheering and retention force are ongoing, but few have been openly published. • Coplanarity: SMT connectors must maintain coplanarity in order to reliably solder to SMT PCB footprints. To date, SMT connectors have adequately been able to hold 0.013 cm (0.005 in) to 0.025 cm (0.010 in) of coplanarity across 2.54 cm (1.0 in) linear distances, and this level of coplanarity has typically been acceptable when combined with IPC Class 2 SMT PCBs. However, as high-speed, high-density connectors grow in size, it may become difficult for connectors to meet more stringent coplanarity requirements. • Lead-Free: A strong industry emphasis on lead-free manufacturing has direct implications for SMT connectors. While PTH pressfit connectors are usually placed on PCBs after hightemperature solder reflow, SMT connectors may need to directly withstand the high solder reflow temperatures associated with lead-free solder. As a result, SMT connectors may need to be manufactured out of alternate dielectric materials, such as LCPs. Further study needs to be completed on transitioning to such materials. Printed Circuit Boards (PCBs) SMT footprints also come with a host of issues that must be considered when designing and manufacturing the system printed circuit boards. These issues are outlined below: • Coplanarity: Most high-speed applications require PCBs to be manufactured to IPC Class 2 requirements, which mandate that SMT PCBs maintain 0.75% coplanarity per linear distance. Most board shops can achieve 0.75% coplanarity with no additional cost, and many can reach 0.5% with a small additional cost. To date, 0.75% coplanarity has been sufficient. • Board Finish: Coplanarity requirements typically limit board finish options. In general, hot air solder leveling (HASL) is not recommended for SMT PCBs. Rather, one should choose a board finish such as electroless nickel/immersion gold (ENIG) or organic solder protectant (OSP). For high-density, thicker PCBs, HASL is often not a good option anyway, since it tends to have difficulty in finishing high-aspect ratio vias without closing them. • Aspect Ratio: Since SMT footprints gain electrical advantages through the use of small vias, PCB thickness limitations introduced by these vias must be considered. Most board shops incur no extra cost as long as an aspect ratio of 10:1 or below is maintained. Above 10:1, a cost increase of approximately 10% can be incurred, which can become even higher if approaching board shop aspect ratio limits, which are typically between 12:1 and 18:1. 27

•

•

Via-in-Pad Plugging: When using SMT footprints with vias located inside surface pads, vias should be plugged to prevent solder leakage through the via during solder reflow. Via plugging using Dupont’s conductive CB-100 material is fairly common in the industry and typically adds about $100 per panel. Lead-Free: A strong industry emphasis on lead-free manufacturing has direct implications for PCBs that use SMT footprints. Since lead-free solder requires higher reflow temperatures, PCBs with SMT footprints may require PCB dielectrics to have higher glass transition temperatures. Typically, dielectrics with higher glass transition temperatures cost more. On daughtercards, switching to SMT footprints introduces no new requirements, since most daughtercards already have SMT components. However, for backplanes, switching to SMT footprints requires higher dielectric transition temperatures where they were not previously required.

Assembly Most issues concerning SMT footprint manufacturing are related to the assembly of the SMT connector to the SMT PCB footprint. These issues are outlined below: • Coplanarity: To date, contract assembly manufacturers have not had coplanarity issues, provided that connectors and PCBs meet the coplanarity requirements listed above. • Pick and Place: Unlike PTH connectors, SMT connectors require pick and place equipment. For large backplanes, some assembly shops may not have the equipment necessary to pick and place SMT parts on large panel sizes. Note that pick and place machines utilize suction, so special connector covers are required if machines are to pick up heavy high-density connectors. • Solder Reflow: Delivering enough heat to large backplanes with SMT connectors can be a challenge. It is common for system prototypes to require temperature profile adjustments. • Repairability: Unlike traditional PTH pressfit connectors, SMT connectors are virtually impossible to repair in the field. Even at the assembly shop, pressfit repair is easy and preferred. SMT repair is difficult and may require special equipment and/or a microstencil. • Inspection: PTH pressfit connectors can be optically inspected during insertion and electrically inspected following assembly. SMT connectors require pre-assembly optical inspection of pads and pins as well as post-assembly X-ray inspection and electrical inspection. In general, SMT inspections are more difficult, though inspections are usually only required while defining the assembly process. • CTE Matching: SMT connectors often require matching of the connector coefficient of thermal expansion (CTE) to the PCB CTE. If this is not done, parts may not align during soldering. Worse yet, run-time system heat may cause different expansion rates to crack solder joints. To date, CTE matching has not had issues for 2.54 cm (1.0 in) parts, but it may become more of an issue as parts grow larger. • Lead-Free: A strong industry emphasis on lead-free manufacturing has direct implications for assembling SMT connectors to SMT PCBs. In general, assembly shops adapt processes to the higher reflow temperatures required by lead-free solder. To date, there is a lack of industry experience, and therefore a lack of specifications, in this area. • Generally: For backplanes, assembly shops prefer all pressfit PTH to all SMT. On daughtercards, where SMT parts already exist, some assembly shops have no preference, while others still prefer pressfit PTH. Typically, pressfit PTH connectors require more expensive fixturing and are assembled through manual processes. SMT connector assembly, on the other hand, is more automated, but more expensive due to extra processing steps required. SMT connectors require more inspection and rework is difficult.

28

Conclusions The goal of this paper was to quantify signal integrity improvements achievable when transitioning from PTH footprints to SMT footprints in multi-gigabit, high-density applications. This was accomplished using the Tyco Electronics HM-Zd connector in typical systems, where SMT footprint signal integrity improvements were shown for throughput-only, throughput with noise, and throughput with noise and equalization. Manufacturing concerns associated with SMT connectors, PCBs, and assembly were listed. Within the footprint-only and footprint-connector-footprint sections of the paper, it was demonstrated that SMT footprints offer noticeable through-the-board throughput advantages over PTH footprints, due to the fact that SMT footprints can use smaller vias. It also became apparent that, for the HM-Zd connector, there was little near- or far-end noise difference between PTH footprints and SMT footprints. Between various SMT footprints, it was shown that there was little electrical difference, meaning the most routable SMT footprint should be chosen. Data was also presented showing that SMT footprints do not eliminate the need to remove via stubs in high-speed systems. Appendix 1 and Appendix 2 demonstrate how footprint impedance relates to overall insertion loss. The system performance section of the paper included throughput-only, throughput with noise, and throughput with noise and equalization performance data. Throughput-only data quantified that electrical advantages of SMT footprints are more apparent when overall system loss is low. Throughput with noise data showed how noise lessens the signal integrity improvements of SMT footprints over PTH footprints, as the result of higher noise at faster bit speeds (Appendix 3 and Appendix 4 show how noise can close system eye patterns significantly at high bit rates). Throughput with noise and equalization data showed that signal integrity improvements of SMT footprints over PTH footprints can be more apparent when simple equalization corrects for overall system loss. Manufacturing concerns associated with SMT connectors, PCBs, and assembly showed that there are still many issues to be studied and addressed to ensure the long-term reliability of high-density SMT applications. Appendix 5 shows how SMT footprints can make use of smaller signal vias and blind vias in order to gain routing channels and route more pairs through each channel. For the chosen systems of this paper, quantification has been completed with and without noise and with and without simple equalization of the lengths and bit speeds at which a transition to SMT footprints makes sense. Note that many system permutations, such as different PCB dielectrics, different connector footprints, varying daughtercard trace lengths, and more elaborate forms of equalization were not included in this study. These and other permutations may be examined in the future. Special thanks goes to Dave Helster and Alex Sharf for gathering connector, PCB, and assembly manufacturing information as well as Mike Woodford for test board design and testing support.

29

Appendices Several appendices, referenced throughout the paper, are available upon request. These appendices address relevant technical topics in greater detail than the paper itself. The subject of each appendix is listed below: Appendix 1: The Effect of a Single Impedance Discontinuity on Insertion Loss Appendix 2: The Effect of Two Impedance Discontinuities on Insertion Loss Appendix 3: How Noise Closes Eye Patterns More than the Reported Noise Percentage Appendix 4: Understanding How Noise Increases Eye Closure with Bit Speed Appendix 5: Surface-Mount Routing Advantages: Quad-Route and Blind Vias

At the time of this publication, it was felt that the technical information provided by the appendices, though useful, was not necessary for understanding the differences between PTH and SMT footprints. To keep the document a reasonable length, the appendices have been omitted, but are available upon request through the following channels: Tyco Electronics – Circuits & Design Email: Tyco Electronics – Chad Morgan Email:

[email protected] [email protected]