Computer Architecture
ESE 345 Computer Architecture Designing a Multicycle Processor Datapath and Control
Designing a multicycle processor
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Simple Questions
How many cycles will it take to execute this code?
Label:
lw $t2, 0($t3) lw $t3, 4($t3) beq $t2, $t3, Label add $t5, $t2, $t3 sw $t5, 8($t3) ...
#assume not taken
What is going on during the 8th cycle of execution? In what cycle does the actual addition of $t2 and $t3 takes place?
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Implementing the Control for a Multicycle Processor
Value of control signals is dependent upon: what instruction is being executed which step is being performed
Use the information we’ve accumulated to specify a finite state machine specify the finite state machine graphically, or use microprogramming
Implementation can be derived from specification
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Review: Finite State Machines
Finite state machines: a set of states and next state function (determined by current state and the input) output function (determined by current state and possibly input) Next state Current state
Next-state function
Clock Inputs
Output function
Outputs
We’ll use a Moore machine for the output function output based only on current state Designing a multicycle processor
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Multicycle Processor PCSource
PCWriteCond PCWrite
ALUOp
Outputs
IorD MemRead
ALUSrcB Control ALUSrcA
MemWrite MemtoReg
Op [5–0]
RegWrite
IRWrite
0
RegDst
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Instruction [25-0] Instruction [31–26] PC
0 M u x 1
Address M em ory Mem Data Write data
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M 1 u x 2
PC [31–28] 0 M u x 1
Read register 1
Instruction [25–21]
Read data 1 Read register 2 Registers Write Read register data 2
Instruction [20–16] 0 M Instruction u x [15–11] 1
Instruction [15–0] Instruction register Instruction [15–0] Memory data register
Shift left 2
Jump address [31–0]
A
ALUOut
0
B 4
Write data
0 M u x 1
Zero ALU ALU result
1M u 2 x 3
16
Sign extend
32
Shift left 2
ALU control
Instruction [5–0]
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Graphical Specification of FSM Instruction fetch
Note:
Start
don’t care if not mentioned asserted if name only otherwise exact value Memory address computation
6 ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00
How many state bits will we need?
Memory access 3
8 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10
Memory access 5
MemRead IorD = 1
1 ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00
Jump completion
Branch completion
Execution
2
MemRead ALUSrcA = 0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCWrite PCSource = 00
0
Instruction decode/ register fetch
9 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01
PCWrite PCSource = 10
R-type completion 7
MemWrite IorD = 1
RegDst = 1 RegWrite MemtoReg = 0
Memory read completon step 4 RegDst = 10 RegWrite MemtoReg = 01
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Finite State Machine for Control Implementation: P C W rit e P C W rite C o n d Io r D M em R e ad M e m W r ite IR W rit e C o n tro l l o g ic
M e m to R e g P C S o u rce ALUO p O u tp u ts
A L U S rc B A L U S rc A R e g W r ite R egD st NS3 NS2 NS1
I n s tru c t io n re g is te r
S0
S1
S2
NS0
S3
O p0
O p1
O p2
O p3
O p4
I n p u ts
O p5
S ta te r e g is te r
o p c o d e fie ld
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PLA Implementation Op5 Op4 Op3 Op2 Op1 Op0 S3 S2 S1 S0 PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg PCSource1 PCSource0 ALUOp1 ALUOp0 ALUSrcB1 ALUSrcB0 ALUSrcA RegWrite RegDst NS3 NS2 NS1 NS0
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ROM Implementation
ROM = "Read Only Memory" values of memory locations are fixed ahead of time A ROM can be used to implement a truth table m entries in the ROM. if the address is m-bits, we can address 2 our outputs are the bits of data that the address points to.
m
n
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 1 1 0 0 0 0
0 1 1 0 0 0 1 1
1 0 0 0 0 0 1 1
1 0 0 0 0 1 0 1
m is the "height", and n is the "width" Designing a multicycle processor
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ROM Implementation
How many inputs are there? 6 bits for opcode, 4 bits for state = 10 address lines (i.e., 210 = 1024 different addresses) How many outputs are there? 16 datapath-control outputs, 4 state bits = 20 outputs
ROM is 210 x 20 = 20K bits
Rather wasteful, since for lots of the entries, the outputs are the same — i.e., opcode is often ignored
(and a rather unusual size)
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ROM vs PLA
Break up the table into two parts — 4 state bits tell you the 16 outputs, 24 x 16 bits of ROM — 10 bits tell you the 4 next state bits, 210 x 4 bits of ROM — Total: 4.3K bits of ROM
PLA is much smaller — can share product terms — only need entries that produce an active output — can take into account don't cares
Size is (#inputs ´ #product-terms) + (#outputs ´ #product-terms) For this example = (10x17)+(20x17) = 510 PLA cells
PLA cells usually about the size of a ROM cell (slightly bigger)
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Another Implementation Style Complex instructions: the "next state" is often current state + 1 P C W r i te
C o n tr o l u n it
P C W r i te C o n d Io r D M em R ead PLA or RO M
M e m W r it e IR W r ite B W r ite O u tp u ts
M e m to R e g P C S o u rc e A LU O p A L U S rc B A L U S rc A R e g W r it e R eg D st
In p u t
A d d rC tl
1
S ta te A d der
A d d r e s s s e le c t l o g ic O p [5 – 0 ]
In s tr u c t io n r e g is te r o p c o d e fie ld
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Details Op 000000 000010 000100 100011 101011
Dispatch ROM 1 Opcode name R-format jmp beq lw sw
Value 0110 1001 1000 0010 0010
Op 100011 101011
Dispatch ROM 2 Opcode name lw sw
Value 0011 0101 PLA or ROM
1 State Adder
3
Mux 2 1
AddrCtl 0 0
Dispatch ROM 2
Dispatch ROM 1 Address select logic
State number 0 1 2 3 4 5 6 7 8 9
Address-control action Use incremented state Use dispatch ROM 1 Use dispatch ROM 2 Use incremented state Replace state number by 0 Replace state number by 0 Use incremented state Replace state number by 0 Replace state number by 0 Replace state number by 0
Value of AddrCtl 3 1 2 3 0 0 3 0 0 0
Designing a multicycle processor
Instruction register opcode field
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Microprogramming Control unit
Microcode memory
Outputs
Input
PCWrite PCWriteCond IorD MemRead MemWrite IRWrite BWrite MemtoReg PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst AddrCtl
Datapath
1 Microprogram counter Adder Address select logic
Instruction register opcode field
What are the “microinstructions” ? Designing a multicycle processor
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Microprogramming sequencer datapath control control
Inputs
-Code ROM
microinstruction ()
micro-PC
Opcode
-sequencer: fetch,dispatch, sequential Dispatch ROM
Decode Decode
To DataPath
° Microprogramming is a fundamental concept • implement an instruction set by building a very simple processor and interpreting the instructions • essential for very complex instructions and when few register transfers are possible • overkill when ISA matches datapath 1-1 Designing a multicycle processor
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Microprogramming ° Microprogramming is a convenient method for implementing structured control state diagrams: • Random logic replaced by microPC sequencer and ROM • Each line of ROM called a instruction: contains sequencer control + values for control points • limited state transitions: branch to zero, next sequential, branch to instruction address from displatch ROM
° Horizontal Code: one control bit in Instruction for every control line in datapath ° Vertical Code: groups of control-lines coded together in Instruction (e.g. possible ALU dest) ° Control design reduces to Microprogramming • Part of the design process is to develop a “language” that describes control and is easy for humans to understand
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“Macroinstruction” Interpretation Main Memory
ADD SUB AND
. . . DATA
execution unit CPU
User program plus Data this can change!
one of these is mapped into one of these
AND microsequence
control memory
e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s)
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Designing a Microinstruction Set 1) Start with list of control signals 2) Group signals together that make sense (vs. random): called “fields” 3) Place fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last) 4) To minimize the width, encode operations that will never be used at the same time 5) Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals • Use computers to design computers
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Multicycle datapath (with ORI but w/o Jump) PCWr
32
5
Rt 0 Rd
busA A
Rb
Reg File Rw busW busB
1 1 Mux 0
Imm 16
Extend
ExtOp
