Lecture 10: Datapath Control; Multicycle •

Organizational – We’re still grading the exams; hopefully done on Thursday – Hand out HW #3, due a week from today – Partial solutions to HW #3 available on Thursday

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Last Time – Datapath organization

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Today – Datapath Control – Multicycle Machine – Introduction to Pipelining (if we have time)

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©2004 Morgan Kaufmann Publishers

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Datapath Review

Instruction Execution •

5 basic steps – fetch instruction (F) – decode instruction and read registers (R) – execute (X) – access memory (M) – store result (W)

I-Fetch

Decode

Execute

Memory

Write Result

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Pieces we’ll need Data

ALU

PC

Register # Registers Register # Register #

Address Data memory

Address Instruction Instruction memory

Data

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Single-cycle MIPS datapath PCSrc

M u x

Add Add

4

ALU result

Shift left 2

PC

Read register 1

Read address Instruction Instruction memory

ALUSrc Read data 1

4

ALU operation MemWrite

Read register 2 Registers Read Write data 2 register

MemtoReg

Zero

M u x

Write data

ALU ALU result

Address

Write data

RegWrite 16

M u x

Data memory

MemRead

32

Sign extend

Read data

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0 M u x

Add ALU Add result

4

Instruction [31–26] Control

PC

Instruction [25–21]

Read register 1

Instruction [20–16]

Read register 2

Read address Instruction [31–0] Instruction memory

0 M u Instruction [15–11] x 1

Write register Write data

16

Instruction [15–0]

1

Shift left 2

RegDst Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite

Read data 1 Zero Read data 2

Registers

Sign extend

ALU ALU result

0 M u x 1

Address

Read data

1 M u x 0

Data Write memory data

32 ALU control

Instruction [5–0]

Instruction RegDst ALUSrc R-format 1 0 lw 0 1 sw X 1 beq X 0

Memto- Reg Mem Mem Reg Write Read Write Branch ALUOp1 ALUp0 0 1 0 0 0 1 0 1 1 1 0 0 0 0 X 0 0 1 0 0 0 X 0 0 0 1 0 1

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Control is built with combinational logic Inputs

It’s just the logic to implement a truth table

Op5 Op4 Op3 Op2 Op1 Op0

Outputs R-format

Iw

sw

beq

RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOpO ©2004 Morgan Kaufmann Publishers

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Single Cycle Implementation PCSrc

M u x

Add Add

4

ALU result

Shift left 2

PC

Read address Instruction Instruction memory

Read register 1

ALUSrc Read data 1

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memory (200ps) ALU and adders (100ps) register file access (50ps)

MemtoReg

Zero

M u x

ALU ALU result

Address

Write data

RegWrite 16

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ALU operation MemWrite

Read register 2 Registers Read Write data 2 register Write data

Calculate cycle time assuming negligible delays except:

4

Sign extend

32

Read data

M u x

Data memory

MemRead

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Where we are headed •

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Single Cycle Problems: – what if we want to reuse hardware (e.g. ALU/Adder) rather than having two copies? One Solution: – use a “smaller” cycle time – have different instructions take different numbers of cycles – a “multicycle” datapath:

PC

Instruction register

Address

Data

Data A Register # Registers Register #

Instruction Memory or data Memory data register

ALU

ALUOut

B Register #

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Multicycle Datapath

Multicycle Approach •

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We will be reusing functional units – ALU used to compute address and to increment PC – Memory used for instruction and data Our control signals will not be determined directly by instruction – e.g., what should the ALU do for a “subtract” instruction? We’ll use a finite state machine for control

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Multicycle Approach •

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Break up the instructions into steps, each step takes a cycle – balance the amount of work to be done – restrict each cycle to use only one major functional unit At the end of a cycle – store values for use in later cycles (easiest thing to do) – introduce additional “internal” registers PC

0 M u x 1

Address Memory MemData Write data

Instruction [20–16] Instruction [15–0] Instruction register Instruction [15–0] Memory data register

0 M u x 1

Read register 1

Instruction [25–21]

0 M Instruction u x [15–11] 1

Read data 1 Read register 2 Registers Write Read register data 2

A

B 4

Write data

0 M u x 1 16

Sign extend

32

Zero ALU ALU result

ALUOut

0 1M u 2 x 3

Shift left 2

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PC

0 M u x 1

Address Memory MemData Write data

Read register 1

Instruction [25–21] Instruction [20–16] Instruction [15–0] Instruction register Instruction [15–0] Memory data register

0 M Instruction u x [15–11] 1

Read data 1

Read register 2 Registers Write Read register data 2

16

32

ALUOut

0

B 4

Sign extend

Zero ALU ALU result

Write data

0 M u x 1

0 M u x 1

A

1M u 2 x 3

Shift left 2

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Instructions from ISA perspective • •

Consider each instruction from perspective of ISA. Example: – The add instruction changes a register. – Register specified by bits 15:11 of instruction. – Instruction specified by the PC. – New value is the sum (“op”) of two registers. – Registers specified by bits 25:21 and 20:16 of the instruction Reg[Memory[PC][15:11]]