IJRRECS/October 2014/Volume-2/Issue-10/3509-3513

ISSN 2321-5461

INTERNATIONAL JOURNAL OF REVIEWS ON RECENT ELECTRONICS AND COMPUTER SCIENCE

DESIGN OF EFFICIENT PARALLEL RADIX 10 MULTIPLIER Shaik Sajit Karim1, Nadella Gopi Nadh2 1

2

M.Tech Student, Dept of EC E, Ni mra Institute of Engineering & Technol ogy, Ong ole, A.P, India

Assistant Professor, Dept of ECE, Ni mra Institute of Engineering & Technology, Ongole, A.P, Indi a

ABSTRACT: Here a new technique is proposed under which it is designed with a well efficient mechanism by the effective design of the architecture related to the decimal multiplier of the radix 10 is a major concern respectively. There is a huge demand for the implementation of the decimal unit based on the floating point strategy under which there is a lot of improvement takes place in the system under the analogous decimal multiplier plays a crucial role in its applicability is a major concern respectively. The performance of the partial products is due to the generation of the data bits in a parallel fashion under which the performance is based on the scenario of the recoding of the radix 10 multiplier following by the multiples o f the multiplicand based set of the simplification plays a major role in its analysis based perspective is a major concern respectively. Here the implementation of the partial product based reduction by the help of the algorithm based on the structure oriented tree on behalf of the addition of the carry save based strategy related to the multi operand is a major concern under the constraints of the unconventional number system of the decimal coding is a major concern respectively. These are mainly designed for the improvement of the area based constraints and further previous design latency. Under which there is an inclusive of the re coders of the optimized digit, decimal adders of the carry save phenomena by the integrated operands of the decimal code and the adders of the carry free implementation and special bit counter based design plays a crucial role in its applicability respectively. Experiments have been conducted on the present method where there is a lot of analysis takes place under which for the well accurate evaluation of the proposed method in www.ijrrecs.com

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IJRRECS/ October 2014/Volume-2/Issue-10/3509-3513

terms of the efficiency followed by the performance and outcome of the entire system in a efficient fashion respectively. KEYWORDS: Arithmetic computer decimal, Multiplication of the parallel decimal, Generation of the partial product, Addition of the carry save decimal, FPGA and XILINX respectively. [2][3]. Here for the proper maintenance of the parallelism towards the system under

1. INTRODUCTION:

which there is an accessibility of the multi

Implementation of the hardware related to

operand with respect to the design of the

the decimal units of the arithmetic strategy

circuit of the hardware is a major concern

for the accuracy based provision under the

respectively.

fields of the scientific, commercial and

implementation of the schemes of the

financial followed by the applications of the

multiplication is done on the behalf of the

internet

following

respectively.

For

the

proper

Here

sequential

the

basis

further

and

which

representation of the precision of the

includes generation of the partial product,

floating point scenario under which there is

Reduction of the partial product and

a lack of orientation in the sequential

followed by the propagating addition of the

strategy respectively [1]. Therefore the

final carry respectively.

specifications are incorporating with respect 2. METHODOLOGY:

to the arithmetic floating point basis under the stipulated standards of the IEEE 754

In this paper a new technique is

plays a crucial role by the integrity of the

presented under which it is briefly shown in

hardware followed by the software is a

the above figures in the form of the block

major concern respectively. Under the

diagram and followed by the architecture

literature of the arithmetic computer there is

and is explained in an elaborative fashion

an inclusive of the decimals of the hardware

respectively. Here in the implementation of

arithmetic followed by the BCD multi

the architecture in relation to that SD

operand adders and multipliers and the

multiplier of the radix 10 of the well

dividers is a major concern respectively

oriented d digit plays a crucial role in its

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ISSN 2321-5461

IJRRECS/ October 2014/Volume-2/Issue-10/3509-3513 analysis based perspective respectively [4].

Digital recorder implementation:

There are some of the sequential steps are used for the implementation of the system and which includes decimal codes of the partial product generation and followed by the SD encoding of the radix 10 strategy and partial product reduction in addition with carry propagate BCD respectively. Here the partial products of the d+1 data bits are generated followed by the help of the multiplier based encoding basis on behalf of the SD digits of the radix 10 strategy with the proper addition of the leading bit respectively. 5:1 mux level can be controlled by the help of the SD digit radix 10 strategy in which it includes the design based specification of the positive coding of the multiple multiplicand in a well oriented fashion respectively [5]. For getting the individual partial product in which it

For the purpose of the computation oriented multiples of the multiplicand under which the recoders of the digit are used for the operation reduction of the computation of the partial product is a major concern respectively. Here the BCD based recoder implementation on behalf of the logical digits there is a straight forwards strategy excess 6 scenario where there is an inclusive of the mapping of the certainty of the decimal

digits

is

a

major

concern

respectively. As per the analysis of the various sub sets there is a well efficient presentation of the desired properties under which by the inclusive of the codes of the non redundant decimal is a major concern and plays a crucial role in a well efficient manner respectively. 3. EXPECTED RESULTS:

includes the gates of XOR based level under which the output bits are getting inverted by

Rtl schematic

the muxes of the 5:1 until the negativity is attained under the SD digit of the radix 10 respectively. Before the codes of the partial products gets reduced the alignments of the codes plays a crucial role and is done in an effective manner on behalf of the weight based decimal point respectively. Inte rnal structure of rtl schematic www.ijrrecs.com

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IJRRECS/ October 2014/Volume-2/Issue-10/3509-3513

Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Inte rnal structure of technology

Maximum combinational path delay: 20.458ns

schematic

wave form result

Design summary

Experiments have been conducted on the present method and the simulated results of the present method are shown in the above figure and

is explained

in an

elaborative fashion respectively. Here the Timing Summary:

implementation of the present method completely overcomes the drawbacks of the

--------------Speed Grade: -5

several

previous

methods

in

a

well

acquainted manner under which there is a lot of improvement in terms of the effectiveness towards the entire outcome of the system in a well oriented fashion respectively. Here www.ijrrecs.com

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IJRRECS/ October 2014/Volume-2/Issue-10/3509-3513

ISSN 2321-5461

the design of the present method completely

implementation of the hardware is a major

studies and analyzes the problems of the

concern respectively.

several

previous

methods

in

a

well

acquainted fashion where it must completely overcome the problems of the previous

REFERENCES [1]. T. Lang and A. Nannarelli. A radix-10 combinational multiplier. In Proc. 40th Asilomar Conference on Signals, Systems,

methods in which they are responsible for the degradation of the performance is a major concern respectively. Here we finally conclude that the design of the present

and Computers, pages 313–317, Oct. 2006. [2] I.D. Castellanos and J.E. Stine, “Compressor Trees for Decimal Partial Product Reduction,” Proc. 18th ACM Great Lakes Symp. VLSI, pp. 107-110, Mar. 2008.

method is effective and efficient in terms of

[3]. B.J. Hickman, A. Krioukov, M.A. Erle, and M.J. Schulte, “A

the

IEEE Conf. Computer Design, pp. 296-303, Oct. 2007.

improvement

in

the

performance

Parallel IEEE P754 Decimal Floating-Point Multiplier,” Proc. 25th

followed by the outcome of the entire

[4]. R.D. Kenney, M.J. Schulte, and M.A. Erle, “High-Frequency

system

Decimal Multiplier,” Proc. IEEE Int’l Conf. Computer Design:

in

a

well

stipulated

fashion

VLSI in Computers and Processors, pp. 26-29, Oct. 2004.

respectively.

[5]. M. A. Erle, E. M. Schwarz, and M. J. Schulte. Decimal

4. CONCLUSION:

multiplication with efficient partial product generation. In Proc. IEEE 17th Symposium on Computer Arithmetic, pages 21–28,

In this paper a new technique is

June 2005.

presented under which for the further improvement in the performance in terms of the improvement in the speed of the system followed by the reduction of the complexity of the circuit based design oriented modules in addition to the reduction of the space based parameters that will help the system for

the

further

improvement

in

the

performance is a major concern respectively. Here for the well effective implementation of the present challenge under which there is a

parallel

multiplication

based

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