ISSN(Online): 2320-9801 ISSN (Print) : 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering (An ISO 3297: 2007 Certified Organization)

Vol. 4, Special Issue 2, April 2016

Design of High Performance Radix-4 and Radix-8 Multiplier Using Verilog HDL M.Kannan Assistant Professor, Dept. of ECE, S.Veerasamy Chettiar College of engineering & Technology, Puliangudi, India

ABSTRACT : A fast and energy efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such as important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application. Now-a-days the power consumption is the major problem for the electronic devices. So, to design the integrated circuit, to perform the low power, less occupation area and high speed simultaneously. This paper present to design the high performance parallel radix-4 and radix-8 multiplier by using modified booth algorithm. The structure for design is mxn multiplication. Where , m and n reach up to 8bits. Carry the speed of operator. This design process is done in verilog HDL and simulation by using modelsim simulator (XSE 8.1). KEYWORDS : VLSI, Verilog HDL, Area, Power Consumption. I. INTRODUCTION Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MACS) and inner product are among some of the frequently used computationIntensive Arithmetic Functions (CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform (FFT), Filtering (FIR,IIR) and in microprocessors in its arithmetic and logic unit. The demand for high speed processing has been increasing as a result expanding computer and signal processing applications. One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a `subject of interest over decades. Reducing the power consumption are very essential requirements for many applications. Minimizing power consumption for digital systems involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level of the algorithms that are being implemented. Digital multiplier are the most common the used components in any digital circuit design. They are fast, reliable and efficient components that are utilized to implement the any operation. Depending upon the arrangement of the components there are different types of multipliers available. Particular multiplier architecture is chosen based on the application. The multiplier is a fairly large block of the computing system. There are different multiplier which can be compared on the basis of speed and area consideration .The multiplier architecture can be generally classified into three categories. First is the serial multiplier which emphasizes on hardware and minimum amount of chip area. Second is parallel multiplier (array and tree) which carries out high speed mathematical operations. Third is serial-parallel multiplier which serves as a good trade-off between the times consuming serial multiplier and the area consuming parallel multipliers

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ISSN(Online): 2320-9801 ISSN (Print) : 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering (An ISO 3297: 2007 Certified Organization)

Vol. 4, Special Issue 2, April 2016

Architecture of radix 2^n multiplier: The architecture of radix 2^n multipliers is given in the figure.

Fig 1.1 : Architecture of Radix 2^n multiplier This block diagram shows the multiplication of two numbers with four digits each. These numbers are denoted as V and U while the digit size was chosen as four bits. The reason for this will become apparent in the following sections. Each circle in the figure corresponds to a radix cell which is the heart of the design. Every radix cell has four digit inputs and two digit outputs. The input digits are also fed through the corresponding cells. The dots in the figure represent latches for pipelining. Every dot consists of four latches. The ellipses represent adders which are included to calculate the higher order bits. They do not fit the regularity of the design as they are used to “terminate” the design at the boundary. The outputs are again in terms of four bit digits and are shown by W’s. The 1’s denote the clock period at which the data appear II.MODIFIED BOOTH ALGORITHM Booth multiplier: Conventional array multipliers, like the Braun multiplier and Baugh Woolley multiplier achieve comparatively good performance but they require large area of silicon, unlike the add shift algorithms, which require less hardware and exhibit poorer performance. The Booth multiplier makes the use of Booth encoding algorithm in order to reduce the number of partial products by considering two bits of the multiplier at a time, thereby achieving a speed advantage over other multiplier architectures. This algorithm is valid for both signed and unsigned number. It accepts the number in two’s compliment form, based on radix-2 computation. It can handle signed binary multiplication by using 2’s compliment representation. This increases the complexity of how signs of the operands get stored in auxiliary circuits. Non-Booth Recoding: Using the non-Booth encoding method for partial product generation, the multiplier bits are examined sequentially starting from LSB to MSB. If the multiplier bit is one, the partial product is simply the multiplicand. Otherwise, the partial product is zero. Each new partial product is shifted one bit position to the left. Each partial product can be produced by just using a row of two-input AND gates. The number of partial products generated equals the size of the multiplier bits.

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ISSN(Online): 2320-9801 ISSN (Print) : 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering (An ISO 3297: 2007 Certified Organization)

Vol. 4, Special Issue 2, April 2016

BOOTH ALGORITHM: Booth Recoding: Booth's multiplication algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. The algorithm was invented by Andrew Donald Booth in 1951 while doing research on crystallography at Birkbeck College in Bloomsbury, London. Booth used desk calculators that were faster at shifting than adding and created the algorithm to increase their speed. Booth's algorithm is of interest in the study of computer architecture. The Booth recoding, or Booth algorithm, was proposed by Andrew D. Booth in 1951[7]. This method can be used to multiply two two’s complement number without the sign bit extension. Booth recoding is a method of reducing the number of partial products to be summed. Booth observed that when strings of '1' bits occur in the multiplicand the number of partial products can be reduced by using subtraction. The operation of Booth recoding consists of two major steps [8]: the first one is to take one bit of the multiplier, and then to decide whether to add the multiplicand according to the current and previous bits of the multiplier. This encoding scheme is serial, which means that the different value of the 2-bits (current and previous bits) corresponds to the different operations Xi

Xi-1

0

0

Operations Shift only

Comments String of zeros

Yi 0

String of 0 zeros Subtract and Beginning 1 0 shift of string of 1 ones Add and End of 0 1 Shift string of 1 ones Table 1.1 : Recoding in Booth Algorithm 1

1

Shift only

The serial recoding scheme is usually applied in serial multipliers. The advantage of this method is that the partial product circuit is simple and easy to implement. Therefore, this scheme is suitable for the implementation of small multipliers. The drawback is that the method is not able to efficiently handle the sign extension and it generates a number of partial products as many as the number of bits of the multiplier, which results in many adders needed so that the area and power consumption increase. This method is not applicable for large multipliers. MODIFIED BOOTH ALGORITHM: The modified Booth encoding (MBE), or modified Booth’s algorithm (MBA), was proposed by O. L. Macsorley in 1961 [11]. The recoding method is widely used to generate the partial products for implementation of large parallel multipliers, which adopts the parallel encoding scheme. One of the solutions of realizing high speed multipliers is to enhance parallelism which helps to decrease the number of subsequent calculation stages. The original version of the Booth algorithm (Radix-2) had two drawbacks. They are: (i) The number of add subtract operations and the number of shift operations becomes variable and becomes inconvenient in designing parallel multipliers. (ii)The algorithm becomes inefficient when there are isolated 1’s. These problems are overcome by using modified Radix4 Booth algorithm .This module recodes the 16-bit multiplier using radix 4 Booth’s algorithm. Radix 4 encoding reduces the total number of multiplier digits by a factor of two, which means in this case the number of multiplier digits will reduce from 16 to 8. This algorithm groups the original multiplier into groups of three consecutive digits where the outermost digit in each group is shared with the outermost digit of the adjacent group. Each of these groups of three binary digits then corresponds to one of the numbers from the set {2, 1, 0, -1, -2}. Each recoder produces a 3-bit output where the first bit represents the number 1 Copyright @ IJIRCCE

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ISSN(Online): 2320-9801 ISSN (Print) : 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering (An ISO 3297: 2007 Certified Organization)

Vol. 4, Special Issue 2, April 2016

and 13 the second bit represents the number 2 Multiplier Bits

Y2i-1 0 0 1 0 1

Y2i 0 0 1 1 0

Recoded operation on multiplicand, Y2i+1 0 1 0 1 0

X 0X +X -X +2X -2X

Table 1.2 : Radix-4 Booth Algorithm The third and final bit indicates whether the number in the first or second bit is negative. Since there are 16 input bits, there will be a total of 8 Booth recoder modules in the overall multiplier architecture. The way the outputs are determined is shown in table 4 above III.RADIX-4 MULTIPLIER Booth algorithm is a powerful algorithm [5] for signed number multiplication, which treats both positive and negative numbers uniformly. Since a k-bit binary number can be interpreted as k/2-digit Radix-4 number, a k/3-digit Radix-8 number and so on, it can deal with more than one bit of the multiplier in each cycle by using high radix multiplication[6]. The major disadvantage of the Radix-2 algorithm was that the process required n shifts and an average of n/2 additions for an n bit multiplier. This variable number of shift and add operations is inconvenient for designing parallel multipliers. Also the Radix-2 algorithm becomes inefficient when there are isolated 1’s. The Radix-4 modified Booth algorithm overcomes all these limitations of Radix-2 algorithm. For operands equal to or greater than 16 bits, the modified Radix-4 Booth algorithm has been widely used. It is based on encoding the two’s complement multiplier in order to reduce the number of partial products to be added to n/2 For Example:

Fig 1.2: Radix-4 Modified Booth Algorithm

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International Journal of Innovative Research in Computer and Communication Engineering (An ISO 3297: 2007 Certified Organization)

Vol. 4, Special Issue 2, April 2016

RADIX-4 SYSTEM ARCHITECTURE: The Radix-4 multiplier consist of three units namely 1. Encoder 2. Decoder 3. 12-bit adder

Fig 1.3 : System Architecture Diagram for Radix-4 multiplier Encoder: An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2n (or fewer) input lines on and n output lines. In encoder the output lines generated the binary code corresponding to the input value. The fig 1.4 shows the general structure of the encoder circuit. As shown in the fig1.4 the decoder information is presented as 2n inputs producing n possible outputs

Fig 1.4 :General Structure of Encoder The encoder block generates the selector signals for each 3 bits of multiplicand. This is the logic for the encoder block: X1=a; Copyright @ IJIRCCE

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International Journal of Innovative Research in Computer and Communication Engineering (An ISO 3297: 2007 Certified Organization)

Vol. 4, Special Issue 2, April 2016

X2=b c; X3=~abc + a~b~c;

Fig 1.5: Encoder Logic Diagram Decoder: A decoder is a multiple-input, multiple-output logic circuit which converts coded inputs into coded outputs, where the input and output codes are different. The input code generally has fewer bits than the output code. Each input code word produces a different output code word, i.e., there is one-to-one mapping from input code words into output code words.

Fig 1.6 : General Structure of Decoder The decoder block generates the partial product from the selector signals that they are generated in encoder blocks. Fig 1.6 shows the schematic and the layout of 1 bit decoder block. We design the 9 bit decoder using 9 blocks of 1bit decoder that their selector signals are the same and 9 blocks of half adder is used to make the partial product in the 2’s complement form in the negative cases. Fig. shows the schematic and the layout of 9 bit decoder block

Fig 1.7: Decoder Block Diagram Copyright @ IJIRCCE

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International Journal of Innovative Research in Computer and Communication Engineering (An ISO 3297: 2007 Certified Organization)

Vol. 4, Special Issue 2, April 2016

Multiplexer: Multiplexer is a digital switch. It allows digital information from several source to be routed on to a single output line. The basic multiplexer has several data-input lines and a single output lines. The selection of a particular input line is controlled by a set of selection of lines. Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is selected. Therefore multiplexer is ‘many into one’ and it provides the digital equivalent of an analog selector switch it as a called as data selector.

Fig 1.8: Multiplier Logic Symbol 12-bit Adder: The 12-bit adder circuit consists of a four 1-bit full adder and 4-bit carry look Ahead adder

Fig 1.9 :12-bit Adder IV. RADIX-8 MULTIPLIER Radix-8 Booth Encoding multiplier uses 4-bit encoding scheme [9] to produce one third the number of partial products. Radix-8 Booth recoding applies the same algorithm as that of Radix-4, but now we take quartets of bits instead of triplets. Each quartet is codified as a signed digit. Radix-8 algorithm reduces the number of partial products to n/3, where n is the number of multiplier bits.

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International Journal of Innovative Research in Computer and Communication Engineering (An ISO 3297: 2007 Certified Organization)

Vol. 4, Special Issue 2, April 2016

Multiplier Bits

Yi+2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Yi+1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

Yi 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

Yi-1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Recoded operation Multiplicand, X 0X +X +X +2X +2X +3X +3X +4X -4X -3X -3X -2X -2X -X -X 0X

Table 1.3 :Radix-8 modified booth algorithm

Fig 1.10: Example for radix-8 booth algorithm System Architecture: The three basic unit of Radix – 8 multiplier is: 1. Encoder 2. Decoder 3. 12-bit adder

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International Journal of Innovative Research in Computer and Communication Engineering (An ISO 3297: 2007 Certified Organization)

Vol. 4, Special Issue 2, April 2016

Fig 1.10 : System Architecture of Radix-8 Multiplier Radix-8 Encoder:

Fig 1.11: Encoder Logic Symbol An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 4(or fewer) input lines on and n output lines. In encoder the output lines generated the binary code corresponding to the input value. The fig shows the general structure of the encoder circuit. As shown in the fig the decoder information is presented as 2n inputs producing n possible outputs.

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Vol. 4, Special Issue 2, April 2016

Fig 1.12 : Encoder Diagram We are using by the 4:3 encoder. They are given by the 4 inputs and will given by the 3 outputs.They are using some logic for using to design by the encoder. The logic is used for radix-8 multiplier design. V. SIMULATION RESULTS (a) Radix-4 Multiplier Output:

Fig: Radix-4 Multiplier Output (b) Radix-8 Multiplier Output:

Fig:radix-8 Multiplier Output Copyright @ IJIRCCE

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VI. CONCLUSION We designed radix-4 and radix-8 multiplier using Modified Booth Algorithm. The radix-8 Modified Booth Multiplier has high performance than the radix-4 Modified Booth Multiplier. Because, radix-8 has less number of partial product than radix-4.So, the time period was reduced in radix-8 than the radix-4 multiplier. As a result, the proposed multipliers are applicable to High Speed data Transmission. REFERENCES [1] Kelly Liew Suet Swee, Lo Hai Hiung, “ Performance Comparison Review of 32-Bit Multiplier Designs” IEEE Transaction on Intelligent and Advanced Systems(ICIAS), Vol.2, June 2012 [2] Swee, K.L.S “ Performance Comparison Review of Radix-Based Multiplier Designs” IEEE Transaction on Intelligent and Advanced Systems(ICIAS), Vol.2, June 2012. [3] RNS And A2Amudha.K, 3 Sreenath.G, “A Faster Carry Save Adder in Radix-8 Booth Encoder Multiplier”,International Journal of VLSI & Signal Processing Applications, Vol. 2,Issue2, April 2012, ISSN 2231-3133, (171-175). [4] 1Premananthan.G, 2Amudha.K, 3 Sreenath.G, “A Faster Carry Save Adder in Radix-8 Booth Encoder Multiplier”,International Journal of VLSI & Signal Processing Applications, Vol. 2,Issue2, April 2012, ISSN 2231-3133, (171-175). [5] Wang.Y, “ Iterative Radix-8 Multiplier Structure Based on a Novel Real-time CSD Recoding” IEEE Transaction on Signals, systems and computers, November 2007. [6]Rajendra Katti,“A Modified Booth Algorithm for High Radix Fixed-point Multiplication” IEEE Transaction on very large scale integration (VLSI)system,vol.2,no.1,december1994. [7]Rajendra Katti,“A Modified Booth Algorithm for High Radix integration (VLSI)system,vol.2,no.1,december1994. [8] Brian S.Cherkauerl and Eby G.Friendrnan “A Hybrid Radix-4/Radix-8 LOW Power, High Speed Multiplier Architecture for Wide Bit widths”Intel Corporation 2200 Mission College Blvd.

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