Area-Efficient & High Speed Ripple Carry based Vedic Multiplier

SSRG International Journal of Electronics and Communication Engineering (SSRG-IJECE) – EFES April 2015 Area-Efficient & High Speed Ripple Carry based...
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SSRG International Journal of Electronics and Communication Engineering (SSRG-IJECE) – EFES April 2015

Area-Efficient & High Speed Ripple Carry based Vedic Multiplier Sulakshna Thakur#1, Pardeep Kumar *2 #

M.Tech. Scholar (ECE), Swami Devi Dyal Institute of Engineering & Technology, Barwala, Haryana, India

*Assistant Professor (ECE), Swami Devi Dyal Institute of Engineering & Techonology, Barwala, Haryana, India Abstract -The speed of a processor greatly depends on its multiplier’s performance. This in turn increases the demand for high speed multipliers we have proposed a high speed & area– Efficient architecture for multiplication of two 8 bit numbers, combining the advantages of ripple carry adders and also the ancient Vedic math's methodology. The proposed design has reduced area, LUT tables and increase the speeds compared with the regular compressor based multiplier.This work evaluates the performance of the proposed designs in terms area, and speed by hand with logical effort and through Xilinx ISE 12.1(Verilog HDL) and this will be implemented in FPGA (Sparton 3E). Keywords— Ripple Carry Adder, half adder, full adder, Compressors, high speed multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics

I.

INTRODUCTION

The speed of any possessor depends on its multiplier‘s performance. This leads to increase the demand for high speed multipliers, keeping in mind low area and moderate power consumption [1]. These multipliers are mostly used in the fields of the Digital Signal Processing (DSP), Fast Fourier Transform, convolution, filtering and microprocessor applications. The mathematical techniques like Vedic mathematics used to reduce the time for the processor such that it can increases speed and also takes only few hardware elements. Vedic is a word obtained from the word ―Veda‖ and its meaning is ―store house of all knowledge‖ Vedic mathematics Consisting of the 16 sutras which it can be related to the different branches of mathematics like algebra, arithmetic geometry [2]. One of the advantages of the Vedic math‘s approach is that the calculation of all the partial products required for multiplication, are obtained well in

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advance, before the actual multiplication begin. These partial products are then added based on the Vedic math‘s algorithm to obtain the final product. This in turn leads to a very high speed approach to perform multiplication [3]. In this paper, we explore a novel method to further enhance the speed of a Vedic mathematics multiplier by replacing the existing compressor based multipliers with Ripple Carry Adder [4]. Ripple carry adder is designed using multiple full adders to add 8-bit numbers. The adder is called a ripple-carry adder, since each carry bit "ripples" to the next full adder.[4] The layout of a ripple-carry adder is simple, which allows for fast design time. Ripple adder is a combination of 4full adders in which output carry is used as input carry to the next full adder. RCA uses number of AND, OR, NOT gates. It has the advantages of high speed and less delay. [5] Section II deals with the Urdhwa Tiryakbhyam method of multiplication using Vedic math‘s sutra in detail. Section III describes the Ripple Carry Adder. Section IV deals with the novel approach of combining the Vedic math for multiplication and Ripple carry adder techniques for a high speed multiplier design. Section V and VI deal with the results and future work possible with these techniques. II.

URDHAVA TIRYAKBHYAM METHOD

Vedic Mathematics can be divided into 16 different sutras to perform mathematical calculations. Among

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these the Urdhwa Tiryakbhyam preferred algorithms for performing multiplication. The words"Urdhwa Tiryakbhyam‖ originated from Sanskrit words Urdhwa and Tiryakbhyam which mean ―vertically‖ and ―crosswise‖ respectively [6]. The main advantage of utilizing this algorithm in comparison with the existing multiplication techniques, is the fact that it utilizes only logical ―AND‖ operations, half adders and full adders to complete the multiplication operation. Also, the partial products required for multiplication are generated in parallel and prior to the actual addition thus saving a lot of processing time. Let us consider two 8 bit numbers X7-X0 and Y7-Y0, where 0 to 7 represent bits from the Least Significant Bit (LSB) to the Most Significant Bit (MSB). P0 to P15 represent each bit of the final computed product. It can be seen from equation (1) to (15), that P0 to P15 are calculated by adding partial products, which are calculated previously using the logical AND operation. The individual bits obtained from equations (1) to (15), in turn when concatenated produce the final product of multiplication which is depicted in (16).The carry bits generated during the calculation of the individual bits of the final product are from C1 to C30. The carry bits generated in (14) and (15) are discarded because they are superfluous. [7] P0 =A0 * B0 C1P1 = (A1 * B0) + (A0 * B1) C3C2P2 = (A2 * B0) + (A0 * B2) + (A1 *B1) + C1 C5C4P3 = (A3 * B0) + (A2 * B1) + (A1 * B2) + (A0 * B3) +C2

(1) (2)

(4)

C7C6P4 = (A4 * B0) + (A3 * B1) + (A2 * B2) + (A1 * B3) +(A0 * B4) +C3 + C4

(5)

C10C9C8P5 = (A5 * B0) + (A4 * B1) + (A3 * B2) + (A2 * B3) +(A1 * B4) + (A0 * B5) + C5 + C6

(6)

C13C12C11P6 = (A6 * B0) + (A5 * B1) + (A4 * B2) + (A3 * B3) + (A2 * B4) + (A1 * B5) + (A0 * B6) + C7 + C8

(7)

(A5 * B2) + (A4 * B3) + (A2 * B5) + (A1 * B6) + (A0 * B7) +C9 + C11

(8)

C19C18C17P8 = (A7 * B1) + (A6 * B2) + (A5 * B3) + (A4 * B4) + (A3 * B5) + (A2 * B6) + (A1 * B7) + C10 + C12 + C14 C22C21C20P9 = (A7 * B2) + (A6 * B3) + (A5 * B4) + (A4 * B5) + (A3 * B6) + (A2 * B7) + C13 +C15 +C17

(10)

C25C24C23P10 = (A7 * B3) +(A6 * B4) + (A5 * B5) + (A4 * B6) +(A3 * B7) + C16 + C18 + C20

(11)

C27C26P11 = (A7 * B4) + (A6 * B5) + (A5 * B6) + (A4 * B7) + C19 + C21 + C23

(12)

C29C28P12 = (A7 * B5) + (A5 * B6) + (A5 * B7) + C22 + C24 +C26

(13)

C30P13= (A7 * B6) + (A6 * B7) + C25 + C27 + C28

(14)

P14 = (A7 * B7) + C29 + C30

(15)

P15= (A7 * B7)

(16)

Fig.1 illustrates the step by step method of multiplying two 8 bit numbers using the Urdhwa Tiryakbyam Sutra. The hardware architecture of the 8x8 Urdhwa multiplier has been designed and shown in Fig.2

(3)

Fig. 1 Pictorial Illustration of Urdhwa Tiryakbhyam Sutra for multiplication of 2 eight bit numbers

C16C15C14P7 = (A7 * B0) + (A6 * B1) +

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(9)

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Fig. 3 4 bit adder

Fig. 2 Hardware architecture of Urdhva Tiryakbhyam multiplier

III.

RIPPLE CARRY ADDER

Adders are the main blocks to complete a multiplier design. The Ripple Carry Adder (RCA) has the smallest area when compared to the other adders. So it is limited to applications where the area must be minimized, while the speed is not important. The ripple carry adder is one of the simplest adders. The ripple carry adder is constructed by cascading full adders (FA) blocks in series. One full adder is responsible for the addition of two binary digits at any stage of the ripple carry. The carryout of one stage is fed directly to the carry-in of the next stage. A number of full adders may be added to the ripple carry adder or ripple carry adders of different sizes may be cascaded in order to accommodate binary vector strings of larger sizes. For an n-bit parallel adder, it requires n computational elements (FA). Fig. 3shows an example of a parallel adder .A 4-bit ripplecarry adder. It is composed of four full adders. The augends‘ bits of x are added to the addend bits of y respectfully of their binary position. Each bit addition creates a sum and a carry out. The carry out is then transmitted to the carry in of the next higher-order bit. The final result creates a sum of four bits plus a carry out (c4)[8].

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Assume you want to add two operands A and B where A= A3 A2 A1 A0 B=B3 B2 B1 B0 For example: A= 1 0 1 1 B= 1 1 0 1 A+B= 11 0 0 0 = C out S3 S2 S1 S0 From the example above it can be seen that we are adding 3 bits at a time sequentially until all bits are added. A full adder is a combinational circuit that performs the arithmetic sum of three input bits: augends Ai, addend Bi and carry in from the previous adder. Its results contain the sum Si and the carry out, to the next stage in C out C. So to design a 4-bit adder circuit we start by designing the 1 –bit full adder then connecting the four 1-bit full adders to get the 4-bit adder The binary full adder is a three input combinational circuit which satisfies the truth table below.

Fig.4 Diagram and Truth Table of Full Adder

The Boolean equations of a full adder are given by: out S = ABC + AB‘C‘ + A‘B‘C + BA‘C‘ =(AB‘+BA‘)C +AB+A‘B‘) C‘ out S = A⊕B⊕C out C = AB + AC + BC out C = AB + C (A⊕B)

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Fig. 5 Carry propagation through the circuit Fig.6 Vedic Multiplier for 8x8 bit Module using Ripple Carry adder

IV. RIPPLE CARRY BASED URDHWA TIRYAKBHYAM MULTIPLIER

The 8x8 bit Vedic multiplier module as shown in the block diagram in Fig.6 can be easily implemented by using four 4x4 bit Vedic multiplier modules as discussed in the previous section. To analyze 8x8 multiplications, say A= A7 A6 A5 A4 A3 A2 A1 A0 and B= B7 B6 B5B4 B3 B2 B1B0. The output line for the multiplication result will be of 16 bits as – S15 S14 S13 S12 S11 S10 S9 S8 S7 S6S5S4 S3 S2 S1 S0. Divide A and B into two parts, say the 8 bit multiplicand A can be decomposed into pair of 4 bits AH-AL. Similarly multiplicand B can be decomposed into BH-BL. The 16 bit product can be written as:

V. RESULTS

In order to perform a comparison, various popular multipliers – Booth‘s, modified Booth‘s, Urdhwa multiplier, the compressor based Urdhwa multiplier and also Ripple carry based Vedic multiplier were Implemented on a Xilinx Spartan 3e – XC3S100E FPGA using Verilog as the RTL language with the help of Xilinx Project Navigator 12.1. The codes were synthesized. Unoptimized speed and area parameters were compared. The Spartan 3e FPGA used for the experiments has a speed grade speed of 5. The results have been tabulated in Table 1 TABLE I COMPARISON OF AREA OCCUPIED AND SPEED OF VARIOUS MULTIPLIER ARCHITECTURES

P = A x B = (AH-AL) x (BH-BL) = AH x BH + (AH x BL + AL x BH) + AL x BL

Algorithm used

LUTs Used

Using the fundamental of Vedic multiplication, taking four bits at a time and using 4 bit multiplier block we can perform the multiplication. The outputs of 4x4 bit multipliers are added accordingly to obtain the final product. Here total three 8 bit Ripple-Carry Adders are required as shown in Fig.6

Booth algorithm Modified Booth algorithm UrdhwaTiryakbhyam Compressor based Urdhwa Tiryakbhyam Ripple carry based Vedic multiplier

An analysis on the area occupied by the new design and also the improvement in speed in comparison with other popular methods of multiplication has been presented in the next section.

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% of area occupied 2

Frequency (MHz)

Time (ns)

55

Total LUTs present 1920

32.28

30.448

213

1920

11

45.982

21.747

185

1920

9

61.869

16.163

170

1920

8

69.153

14.41

132

1920

6

91.7

10.91

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It can be clearly noted from Table I, that in terms of speed, the Ripple Carry based Vedic math‘s multiplier is almost 1.32 times faster than the existing compressor based multiplier. Another interesting thing to note is the area occupied. It can be seen that the compressor based multiplier has occupied an area 2% lesser than the Vedic maths and a 5% reduction with respect to the modified booth methodology. Reduction in number of LUTs can also be seen. VI. CONCLUSION

In this paper, we have proposed Area-Efficient & High Speed Ripple Carry Based Vedic Multiplier architecture for multiplication of two 8 bit numbers, combining the advantages of Ripple Carry based adders and also the ancient Vedic maths methodology. Upon comparison of the area occupied by the multiplier and also its speed, with two other popular multipliers, we can conclude that the Ripple Carry based Vedic maths multiplier proves to be a better option over conventional multipliers used in several expeditious and complex VLSI circuits. As a future work, the multiplier‘s performance could be tested within an ALU and also compared with several other existing multipliers.

[4] Bhavani Prasad.Y, Ganesh Chokkakula‖design of low carry and high speed modified carry Select Adder for 16 bit Vedic Multiplier ―Information Communication and Embedded Systems (ICICES), 2014 International Conference ©2014 IEEE, Page(s): 1 – 6 [5] Prakash Pawar, Varun. R, Suma M.S,"Implementation of High Speed Pipelined Vedic Multiplier," International Journal of Engineering Research & Technology (IJERT) Vol. 2 Issue 5, May - 2013 [6] Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, ―VedicMathematics: Sixteen Simple Mathematical Formulae from the Veda,‖ pp. 5-45, Motilal Banarasidas Publishers, Delhi, 2009. [7] Sushma R. Huddar, Sudhir Rao Rupanagudi, Kalpana M and Surabhi Mohan, ―Novel High Speed Vedic Mathematics Multiplier using Compressors‖, International Multi conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s), 22-23March 2013, Kottayam, ISBN: 978-1-4673-5090-7/13, pp.465-469. [8] Pushpalata Verma, K. K. Mehta” Implementation of an Efficient Multiplier Based on Vedic Mathematics Using EDA Tool” International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958, Volume-1, Issue-5, June 2012 [9] Chang-Young Han, Hyoung-Joon Park, and Lee-Sup Kim, ‗A Low-Power Array Multiplier Using Separated Multiplication Technique‘, IEEE Transactions on Circuits and Systems—II: Analog And Digital Signal Processing, VOL. 48, NO. 9, pp.866-871, 2001. [10] Koren Israel,‖Computer Arithmetic Algorithms,‖ 2nd Ed, pp. 141-149, Universities Press, 2001. [11] Hsiao, Shen-Fu, Ming-Roun Jiang, and Jia-Sien Yeh, "Design of high Speed low-power 3-2 counter and 4-2 compressor for fast multipliers,‖ IEEE Electronics Letters, vol. 34, no.4, pp. 341-343, Feb. 1998.

ACKNOWLEDGEMENT

The authors like to wish thanks‟ to Mr. Pardeep Assistant Professor at SDDIET Barwala, and Mrs. Sukhwinder Kaur HOD (ECE), for giving me valuable guidance and providing me the opportunity to carry out this work further.And also grateful to reference authors who guided me by their papers. REFERENCES [1] L. Ciminiera and A. Valenzano, "Low cost serial multipliers for high-speed Specialized processors, ―Computers and Digital Techniques, IEE Proc.E, vol. 135.5, 1988, pp. 259-265. [2] Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, ―Vedic Mathematics: Vedic Mathematics: Sixteen Simple Mathematical Formulae from the Veda” Delhi (1965) [3] Tiwari, Honey Durga, et al., "Multiplier design based on ancient Indian Vedic Mathematics,‖ Int. SoC Design Conf., 2008, vol. 2. IEEE Proc., pp. II65 - II-68.

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