High-Speed A/D Converter • Flash Converter – Comparator – Binary Encoder

• Interpolation • Folding

A/D DSP

EECS 247 Lecture 17: Flash and Folding Converters

© 2002 B. Boser 1

Flash Converter • Very fast: only 1 clock cycle per conversion

V REF

V IN

R/2

R

• High complexity: 2B-1 comparators

R Encoder

Digital Output

R

• High input capacitance

R

R/2

A/D DSP

EECS 247 Lecture 17: Flash and Folding Converters

© 2002 B. Boser 2

Comparator fs V i+

Do+ Av

Latch

V i-

• • • • • • • • A/D DSP

Do-

Clock rate fs Resolution Overload Recovery Input capacitance (and linearity!) Power dissipation Common-mode rejection Kickback noise …

EECS 247 Lecture 17: Flash and Folding Converters

© 2002 B. Boser 3

CMOS Comparator Example

A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” JSSC June 1985, pp. 775-9. A/D DSP

EECS 247 Lecture 17: Flash and Folding Converters

© 2002 B. Boser 4

Comparator with Auto-Zero

I. Mehr and L. Singer, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC July 1999, pp. 912-20. A/D DSP

EECS 247 Lecture 17: Flash and Folding Converters

© 2002 B. Boser 5

Auto-Zero Implementation

I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” JSSC March 2000, pp. 318-25. A/D DSP

EECS 247 Lecture 17: Flash and Folding Converters

© 2002 B. Boser 6

Flash Converter Errors • Comparator input: VIN

VREF R/2

R

R Encoder

R

Digital Output

– Offset – Nonlinear input capacitance – Kickback noise (disturbs reference) – Signal dependent sampling time

• Comparator output:

R

– Sparkle codes (… 111101000 …) – Metastability

R/2

A/D DSP

EECS 247 Lecture 17: Flash and Folding Converters

© 2002 B. Boser 7

Sparkle Codes Binary Output (negative) 0 0 0

Correct Output: 0110 … 1000

1 1 0 0

Actual Output: 1110

1 1

A/D DSP

EECS 247 Lecture 17: Flash and Folding Converters

© 2002 B. Boser 8

Sparkle Tolerant Encoder Binary Output (negative)

0

0

0

1

1

0

0

0

1

0

Protects against a single sparkle. Ref: C. Mangelsdorf et al, “A 400-MHz Flash Converter with Error Correction,” JSSC February 1990, pp. 997-1002. A/D DSP

EECS 247 Lecture 17: Flash and Folding Converters

© 2002 B. Boser 9

Meta Stability Binary Output (negative)

0

Different gates interpret metastable output X differently

1

Correct Output: 0111 or 1000

1

Actual Output:

0

Solutions:

0

0

X

1111

1

– Latches (high power) – Gray encoding

1

Ref: C. Portmann and T. Meng, “Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters,” JSSC August 1996, pp. 1132-40. A/D DSP

EECS 247 Lecture 17: Flash and Folding Converters

© 2002 B. Boser 10

Gray Encoding Thermometer Code

Gray

Binary

T1

T2

T3

T4

T5

T6

T7

G3

G2

G1

B3

B2

B1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

1

1

1

0

0

0

0

0

0

1

1

0

1

0

1

1

1

0

0

0

0

0

1

0

0

1

1

1

1

1

1

0

0

0

1

1

0

1

0

0

1

1

1

1

1

0

0

1

1

1

1

0

1

1

1

1

1

1

1

0

1

0

1

1

1

0

1

1

1

1

1

1

1

1

0

0

1

1

1

•

G1 = T1 T3 + T5 T7 G2 = T2 T6 G3 = T4

Each Ti affects only one Gi à Avoids disagreement of interpretation by multiple gates Protects also against sparkles Follow Gray encoder by (latch and) binary encoder

• • A/D DSP

EECS 247 Lecture 17: Flash and Folding Converters

© 2002 B. Boser 11

Reducing Complexity E.g. 10-bit “straight” flash – – – – –

Input range: 0 … 1V LSB = ∆: ~ 1mV Comparators: 1023 with offset ∆

0.6 A1 +A2

A1+A2

0.4

Sets upper bound on gain