Pipelined A/D Converter • Model • Digital Correction • Digital Calibration

A/D DSP

EECS 247 Lecture 18: Pipelined ADC

© 2002 B. Boser 1

Pipelined ADC VIN

Stage 1 B 1 Bits

Stage 2 B2 Bits

Stage K Bk Bits

Digital Correction Logic

Digital output up to (B1 + B2 + ... + Bk) Bits

Partial Digital Output

VIN

A/D DSP

coarse ADC (1 ... 6 Bit)

EECS 247 Lecture 18: Pipelined ADC

Error DAC

S/H & Gain (optional)

© 2002 B. Boser 2

Pipeline Stage Model Pipeline Stage, 3 ADC levels

Residuum Ramp

4

S/H In

Out

ADC

In

Dout Dout

DAC

residuum

Gain

Out

Sum

Digital Output

in Matlab window: points =100 (number of points/lsb in simulation)

Later Stages

Corrected Output

Vres = G (Vin − DVref ) See Matlab/Simulink L18_pipe_3_el.mdl

A/D DSP

EECS 247 Lecture 18: Pipelined ADC

© 2002 B. Boser 3

Simulation of 2-Bit Stage

A/D DSP

EECS 247 Lecture 18: Pipelined ADC

© 2002 B. Boser 4

Pipeline ADC Model Pipeline ADC, 2 bits per stage ADC level off in 1st stage

Residuum 1

Residuum Ain

Residuum 2

Error Ain

Dout

Dout

Ramp Pipeline Stage 1

in Matlab window: points =10 (number of points/lsb in simulation)

Pipeline Stage 2

4

ADC Dout

Gain Sum

See Matlab/Simulink L18_pipe_2bps_error.mdl

A/D DSP

EECS 247 Lecture 18: Pipelined ADC

© 2002 B. Boser 5

Simulation Result

A/D DSP

EECS 247 Lecture 18: Pipelined ADC

© 2002 B. Boser 6

Comparator Offset ß Problem: Residuum 1 exceeds overloads 2nd pipeline stage

First stage ADC Levels: Ideal: Error: A/D DSP

Missing Code!

-1, 0, +1 -1, 0.3, +1 EECS 247 Lecture 18: Pipelined ADC

© 2002 B. Boser 7

Digital Correction Pipeline ADC, 2 bits per stage Interstage gain = 2 for digital correction

Residuum 1

Residuum Ain

Residuum 2

Error Ain

Dout

Dout

Ramp Pipeline Stage 1

in Matlab window: points =10 (number of points/lsb in simulation)

Pipeline Stage 2

2

ADC Dout

Gain Sum

Reduced interstage gain: • No overload (due to comparator offset) • Reduced input (only 1 bit resolution per stage) A/D DSP

EECS 247 Lecture 18: Pipelined ADC

© 2002 B. Boser 8

Digital Correction ß “enlarged” residuum still within +/-2 input range of next stage

Only 1 Bit resolution from first stage (3 Bit total) à A/D DSP

EECS 247 Lecture 18: Pipelined ADC

© 2002 B. Boser 9

“1.5-bps” Stage Pipeline ADC, 1.5 bit per stage (2 comparators per stage)

Residuum 1

Residuum 2

Residuum 3 Dout

Error Error Error

Ain Dout

Ain Dout

Ain

Pipeline Stage 3 Dout

2

Pipeline Stage 2 Ramp Pipeline Stage 1

in Matlab window: points = 50 (number of points/lsb in simulation)

Gain6 4 Gain5

Sum

• A full bit of “overrange” is excessive for typical comparator offset • à use only 2 (rather than 3) comparators and G=2

• 3 DAC levels à lb(3) = 1.585 Bits • Overall resolution: • 1 bps for all stages but last • 1.585 Bit for last A/D DSP

EECS 247 Lecture 18: Pipelined ADC

© 2002 B. Boser 10

1.5-bps Pipeline

• What is the maximum offset that can be corrected? • What is the offset of each comparator in this example?

A/D DSP

EECS 247 Lecture 18: Pipelined ADC

© 2002 B. Boser 11

Interstage Gain Error First Stage Residue (Gain Error)

Converter Transfer Function (Gain Error) 1

Dout

Vres

1

0

1

1

0.5

0 Vin

0.5

0

1

1

1

Dout(ideal) - Dout

0.5

1

0

0.2

EECS 247 Lecture 18: Pipelined ADC

0 Vin

Transfer Function Error(Gain Error)

0.2

A/D DSP

0.5

1

0.5

0 Vin

0.5

1

© 2002 B. Boser 12

Digital Gain Calibration • Operation of the pipeline stage:

Vres = G (Vin − DVref )

The gain G is off from it’s correct value (e.g. 1.8 instead of 2) • Digital output from the ADC

GVin = DGVref + Vres – Gain error (GVin term) – Nonlinearity at segment boundary (DGVref term)

A/D DSP

EECS 247 Lecture 18: Pipelined ADC

© 2002 B. Boser 13

Digital Gain Calibration GVin = DGVref + Vres • • •

•

A/D DSP

The “digital” gain in the circuit at right is still 2 The actual amplifier gain in stage 1 is smaller or larger due to component mismatch E.g. GVref = 1000101101 GVref = 1000000000 Hence the overall output is incorrect, regardless of the accuracy of stage 2 EECS 247 Lecture 18: Pipelined ADC

Pipeline ADC, 2 bits per stage Interstage gain = 2 for digital correction

Residuum 1

Residuum Ain

Residuum 2

Error Ain

Dout

Dout

Ramp Pipeline Stage 1

in Matlab window: points =10 (number of points/lsb in simulation)

Pipeline Stage 2

2

ADC Dout

Gain Sum

Digital circuit gain Analog circuit gain

© 2002 B. Boser 14

Measuring GVref • •

If we knew the value of GVref, we could use use that in our digital logic, rather than G=2 How can we measure GVref?

VresA = Vres (Vin = Vx , D = 0) = GVx

VresB = Vres (Vin = Vx , D = 1) = GVx − GVref VresA − VresB = GVref • • •

A/D DSP

If we proceed from the back of the pipeline, we can use the already calibrated backend to digitize GVref! The measurement is performed once at startup, the values stored in a small RAM (one per stage for 1-bps stage resolution) The digital logic uses adders to sum up the different values of GVref from the table stored in the RAM EECS 247 Lecture 18: Pipelined ADC

© 2002 B. Boser 15

• 1-Bit per stage • Only 1 comparator per stage • G