HMXADC9246

Preliminary

Radiation Hardened 14-Bit, 125 MSPS Monolithic A/D Converter Features ■

Monolithic 14-Bit, 125 MSPS A/D Converter

■

Rad Hard: >1M Rad(Si) Total Dose

■

+1.8V V Analog Supply

■

+1.8V to 3.3V Digital I/O Supply

■

Low Power: 400 mW at 125 MSPS

■

Power Down and Standby Modes

■

No Missing Codes Guaranteed

■

Differential Nonlinearity Error: 0.5 LSB

■

Signal-to-Noise and Distortion Ratio: 69.6 dB

■

Spurious-Free Dynamic Range: –81 dB

■

Complete On-Chip S/H Amplifier

■

Flexible Analog input: 1 Vp-p to 2 Vp-p

■

Differential Input with 650 MHz bandwidth

■

On-Chip Voltage Reference

■

Parallel Data Output

■

Offset binary, Gray Code or Two’s Complement output formats

■

Data Output Clock

■

Clock duty Cycle Stabilizer

■

Serial Control Port

The HMXADC9246 is a radiation hardened monolithic, single 1.8V supply, 14-bit, 125 MSPS, analog-to-digital (ADC) converter with an on-chip, high performance sample-and-hold (SHA) amplifier.

The HMXADC9246 uses a multistage differential pipelined architecture with output error correction logic to provide 14-bit accuracy at up to 125 MSPS data rates. This implementation guarantees no missing codes over the full operating temperature range. The HMXADC9246 is fabricated on Honeywell’s 150nm Silicon-On-Insulator (SOI) CMOS radiation hardened S150 technology process with very low power consumption. The input of the HMXADC9246 allows for easy interfacing to space and military imaging, sensor, and communications systems. With a wide bandwidth truly differential SHA input structure, the user can select a variety of input ranges and offsets including single-ended applications. The HMXADC9246 features excellent

dynamic performance. The sample-andhold amplifier (SHA) is well suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and well beyond the Nyquist rate. A differential clock input controls all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in Offset Binary Output, Gray Code or Two’s Complement formats. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. The HMXADC9246 is specified over the military temperature range (-55°C to 125°C).

7

DRVDD

8

D8

9

29 AGND 28 REFT

23

24 AVDD

25 SENSE

AGND

12 21

D11

22

26 VREF

AVDD

27

11

AGND

10

20

D9 D10

CSB

PWDN DrGND

Pin Description Pin

Signal

Definition

21, 23, 29, 32, 37, 41

AGND

1 to 6, 9 to 14, 45, 46

D0 (LSB) to D13

Data Output Bits

7, 16, 47

DRGND (DRVSS)

Digital Output Ground

Analog Ground (AVSS)

8, 17, 48

DRVDD

Digital Output Driver Supply (1.8V to 3.3V)

15

OR

Out-of-Range Indicator

18

SDIO/DCS

SPI Data IO (serial port mode);Duty Cycle Stabilizer Select (external pin mode)

19

SCLK/DFS

SPI Clock (serial port mode); Data Format Select Pin (external pin mode)

20

CSB

SPI Chip Select (active low)

22, 24, 33, 40, 42

AVDD

Analog Power Supply

25

SENSE

Reference Mode Selection

26

VREF

Voltage Reference Input/Output

27

REFB

Differential Reference (-)

28

REFT

Differential Reference (+)

30

VIN+

Analog Input Pin (+)

31

VIN-

Analog Input Pin (-)

34

CML

Common-Mode Level Bias Output

35

RBIAS

External Bias Resistor Connection. A 10KΩ to AGND

36

PDWN

Power-Down Function Select

38

CLK+

Clock Input (+)

39

CLK-

Clock Input (-)

43

OEB

Output Enable (Active Low)

44

DCO

Data Clock Output

30 VIN+

Top View

19

CLK+ CLK–

HMXADC9246

18

AGND

AGND

DRGND

SDIO/DCS

REF SELECT

MODE SELECT

37

VIN-

SPI SCLK/DFS SPI SDIO/DCS SPI CSB

CLOCK DUTY CYCLE STABILIZER

38 CLK+

31

SCLK/DFS

0.5V

40 AVDD

AGND

6

17

+ –

39 CLK-

32

D7

D0 (LSB)

SENSE

AVDD

5

16

D13 (MSB)

+ –

AGND

33 AVDD

D6

DRVDD

VREF

41

4

15 DCO

43 OEB

34 CML

D5 OTR

OUTPUT BUFFERS

42

3

REFB CORRECTION LOGIC

45 D0(LSB)

35 RBIAS

D4

3

DRGND

8

44 DCO

36 PDWN

2

15

A/D

REFT

1

OR

4

D2 D3

A/D

14

8-STAGE 1 1/2-BIT PIPELINE

MDAC1

13

SHA

D12

VIN–

DRGND

AD9246 VIN+

47

48 DVDD

DRVDD

D13(MSB)

AVDD

46 D1

Pinout Definition

Block Diagram

REFB

Signal Definition DRVDD The Digital Output Power Supply (DRVDD) can operate from 1.8V to 3.3V. The DRVDD voltage defines the interface voltage level for all the digital I/O signals including Clock input, Output Enable, and all data output signals. Output Enable (OEB) This signal controls the electrical state of the digital output drivers. A low logic level will enable the outputs and a high logic level will put the output drivers into a high impedance state.

Connecting the SENSE pin to VREF switches the reference amplifier input to the SENSE pin, completing the loop and providing a 0.5V reference output. If a resistor divider is connected external to the chip as shown below, the switch sets to the SENSE pin. This puts the reference amplifier in a non-inverting mode with the VREF output defined as:

(

VREF = 0.5 1+

RBIAS RBIAS is required to create the internal bias currents. An external resistor with a value of 10kΩ shall be connected between pin 35 and analog ground. Voltage Reference Input A stable and accurate voltage reference is built into the HMXADC9246. The input range is adjustable by varying the reference voltage applied to the HMXADC9246, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the following section. Internal Reference Connection A comparator within the HMXADC9246 detects the potential at the SENSE pin and configures the reference into four possible states, as summarized in the Reference Configuration Summary table. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider, setting VREF to 1V.

R2 R1

) VIN + VIN–

ADC Core

REFT 0.1µF

VREF 0.1µF

0.1µF

+ – R2

SENSE

REFB

SELECT LOGIC

0.5V +– R1

Programmable Reference Configuration

If the SENSE pin is connected to AVDD, the reference amplifier is disabled and an external reference voltage can be applied to the VREF pin (see the External Reference Operation section). The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.

VIN + VIN–

ADC Core

REFT 0.1µF

VREF 0.1µF

0.1µF

+ – SELECT LOGIC

SENSE 0.5V +–

Internal Reference Configuration

If the internal reference of the HMXADC9246 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered.

REFB

External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal resistor divider loads the external reference with an equivalent 6KΩ load. In addition, an internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1V.

Radiation Equivalent VREF Circuit AVDD

VREF

6kΩ

CML (Common Mode Level) This signal is an analog output at a typical value of 0.55 x AVDD. It can be used as a reference for biasing external circuits to a “midrail” value. This signal should be decoupled with a 0.1uF capacitor.

Reference Configuration Summary Selected Mode

SENSE Voltage

Resulting VREF (V)

Resulting Difference Span (Vp-p)

External Reference

AVDD

N/A

2 x External Reference

Internal Reference

VREF

0.5

1.0

Programmable Reference

0.2 V to VREF

0.5 x (1+R2/R1)

2 x VREF

Internal Fixed Reference

AGND to 0.2 V

1.0

2.0

Switching Specifications (TMIN to TMAX with AVDD = +1.8V, DRVDD = +2.5V, CL = 5 pF) Parameter

Symbol

Min

Typ

Max

Units

Conversion Rate, DCS Enabled

20

125

MSPS

Conversion Rate, DCS Disabled

10

125

MSPS

Clock Period

tC

8

Clock Pulse Width High, DSC Enabled

tCH

2.4

4

5.6

ns ns

Clock Pulse Width High, DSC Disabled

tCL

3.6

4

4.4

ns

tPD tDCO

3.1

3.9

4.8

DCO Propagation Delay Setup Time

tS

2.6

3.5

ns

Hold Time

tH

3.7

4.5

ns

Data Output Parameters Data Propagation Delay

4.4

Pipeline Delay (Latency) Aperture Delay

tA

Aperture Uncertainty (Jitter)

tJ

ns ns

12

cycles

0.8

ns

0.1

ps rms

Wake-Up Time

350

µs

Out-Of-Range Recovery Time

3

cycles

Serial Port Interface tCLK tHI

40

ns

SCLK Pulse Width High

SCLK Period

16

ns

SCLK Pulse Width Low

tLO

16

ns

SDIO to SCLK Setup Time

tDS

5

ns

SDIO to SCLK Hold Time

tDH

2

ns

CSB to SCLK Setup Time

tS

5

ns

CSB to SCLK Hold Time

tH

2

ns

Analog Sampling Timing Diagram

N+2

N+1

N+3 N N+4

tA

N+8 N+5

N+6

N+7

N-7

N-6

tCLK CLK+ CLK–

tPD DATA

N - 13

N - 11

N - 12

tS

N - 10

tH

N-9

tDCO

N-8

N-5

tCLK

DCO

Output Enable Timing Diagram

OE

50Ω

D1-D12 85pF TDLZ TDHZ

TDZL TDZH

(a) Output Enable Timing Diagram (a) and Effective Load (b)

Mixed Signal Rad Hard Process The HMXADC9246 is fabricated on a space qualified SOI CMOS process. High-speed precision analog circuits are now combined with high-density logic circuits that can reliably withstand the harshest environments.

(b)

N-4

Radiation Performance

Radiation Specifications (TMIN to TMAX with AVDD = +1.8V, DRVDD = +2.5V, CL = 20 pF)

Total Ionizing Radiation Dose The HMXADC9246 will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. All electrical and timing performance parameters will remain within specifications after rebound at VDD = 1.8 V extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transistors using 10 KeV X-ray and Co60 radiation sources. Transistor gate threshold shift correlations have been made between 10 KeV X-rays applied at a dose rate of 1x105 rad(SiO2)/ min at T=25°C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. Transient Pulse Ionizing Radiation The HMXADC9246 will meet any functional or electrical specification after exposure to a radiation pulse up to the transient dose rate survivability specification, when applied under recommended operating conditions. Note that the current conducted during the pulse by the ADC inputs, outputs, and power supply may significantly exceed the normal operating levels. The application design must accommodate these effects. Soft Error Rate The HMXADC9246 is not guaranteed to operate through an SEU or dose rate event, but it will recover and continue to meet all specifications over the full temperature range after an event. Latchup and Snapback The HMXADC9246 will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. Fabrication substrate material provides oxide isolation between adjacent PMOS and NMOS transistors and eliminates any potential SCR latchup structures. Sufficient transistor body tie connections to the p- and n-channel substrates are made to ensure no source/ drain snapback occurs.

Parameters

Min

Max

Units

Total Dose Hardness

>1 x 10 6

Rad (Si)

Dose Rate Upset Hardness

>2.5 x 1012

Rad(Si)/sec

Dose Rate Survivability

>2.5 x 1012

Rad(Si)/sec

Soft Error Rate LET (1)

120

MeV cm2 /mg +VREF – 0.5 LSB

11 1111 1111 1111

01 1111 1111 1111

10 0000 0000 0000

1

Clock Input and Considerations

Jitter All high-speed high resolution A/Ds are sensitive to the quality of

For optimum performance, the HMXADC9246 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ pin and the CLK− pin via a transformer or capacitors. These pins are biased internally and require no external bias. Clock Input Options The HMXADC9246 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL or sine wave signal. Regardless of the type of signal used, the jitter of the clock source is of the most concern, as described in the jitter section. One preferred method for clocking the HMXADC9246 is using a low jitter clock source converted from single-ended to a differential signal using an RF transformer. Back-to-back Schottky diodes across the transformer secondary will limit clock excursions into the HMXADC9246 to approximately 0.8V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the HMXADC9246 while preserving the fast rise and fall times of the signal, which are critical to low jitter. Other clocking methods are available and acceptable based on the user’s requirements. Clock Duty Cycle The HMXADC9246 contains a duty cycle stabilizer (DCS) that retimes the nonsampling, or falling edge of the input clock, providing an internal clock signal with a nominal 50% duty cycle. This protects the ADC performance from variation of input clock duty cycle. Jitter in the rising edge of the input clock is still of concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than approximately 20 MHz. The loop has a time constant that needs to be considered in applications where the clock rate can change dynamically. This requires a wait time of 1.5µs to 5µs after a dynamic clock frequency change before the DCS loop is relocked to the input signal. Disabling the DCS may be appropriate in those applications.

the clock input. The degradation in SNR at a given full-scale input frequency (fIN) due to only aperture jitter (tA) can be calculated with the following equation:

SNR = 20 log10

[ 2π 1f t ] IN A

In the equation, the rms aperture jitter, tA, represents the root sum square of all the jitter sources, which include the clock input, analog input signal and A/D aperture jitter specification. Under sampling applications are particularly sensitive to jitter. Clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the HMXADC9246. Power supplies for clock drivers should be separated from the A/D output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other method), it should be retimed by the original clock at the last step. The clock input is referred to the analog supply. Its logic threshold is AVDD/2. The HMXADC9246 has a clock tolerance of 5% at 125 MHz and should be a 50% duty cycle. The input circuitry for the CLOCK pin is designed to accommodate CMOS inputs. The quality of the logic input, particularly the rising edge, is critical in realizing the best possible jitter performance of the part: the faster the rising edge, the better the jitter performance. As a result, careful selection of the logic family for the clock driver, as well as the fanout and capacitive load on the clock line, is important. Jitter-induced errors become more predominant at higher frequency, large amplitude inputs, where the input slew rate is greatest. Most of the power dissipated by the HMXADC9246 is from the analog power supplies. However, lower clock speeds will reduce digital current.

Grounding and Decoupling Analog and Digital Grounding Proper grounding is essential in any high speed, high-resolution system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. It is important to design a layout that prevents noise from coupling onto the input signal. Digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. While the HMXADC9246 features separate analog and driver ground pins, it should be treated as an analog component. The AVSS and DRVSS pins must be joined together directly under the HMXADC9246. A solid ground plane under the A/D is acceptable if the power and ground return currents are carefully managed. Alternatively, the ground plane under the A/D may contain serrations to steer currents in predictable directions where cross coupling between analog and digital would otherwise be unavoidable. Analog and Digital Driver Supply Decoupling The HMXADC9246 features separate analog and driver supply and ground pins, helping to minimize digital corruption of sensitive analog signals. In general, AVDD, the analog supply, should be decoupled to AVSS, the analog common, as close to the chip as physically possible. It is recommended to use 0.1 uF ceramic chip and 10 uF tantalum capacitors for the AVDD and DRVDD power inputs. A 0.1 uF ceramic chip capacitor is adequate on the CML pin.

Serial Port Interface (SPI) The HMXADC9246 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This provides the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that are further divided into fields, as documented in the Memory Map section. Configuration Using the SPI Three pins define the SPI interface of this ADC. The SCLK/DFS pin synchronizes the read and write data presented to the ADC. The SDIO/DCS dual purpose pin allows data to be sent and read from the internal ADC memory map registers. The CSB pin is an active low control that enables or disables the read and write cycles.

Serial Port Interface Pins Pin Name SCLK/DFS

Function SCLK (serial clock) is the serial shift clock in. SCLK synchronizes serial interface reads and writes.

SDIO/DCS

SDIO (serial data input/output) is a dual purpose pin. The typical role for this pin is an input and output, depending on the instruction being sent and the relative position in the timing frame.

CSB

CSB (chip select bar) is an active low control that gates the read and write cycles.

The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. Other modes involving the CSB are available. The CSB can be held low indefinitely to permanently enable the device (this is called streaming). The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and the length is determined by the W0 bit and the W1 bit. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output.

In addition to word length, the instruction phase determines if the serial frame is a read or a write operation, allowing the serial port to be used to both program the chip as well as read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB- or in LSB-first mode. MSB first is the default on power up and can be changed via the configuration register.

SPI Timing Diagram Specifications Name

Description

tDS tDH

Setup time between data and rising edge of SCLK Hold time between data and rising edge of SCLK

tCLK

Period of the clock

tS

Setup time between CSB and SCLK

tH tHI

Hold time between CSB and SCLK

tLO

Minimum period that SCLK should be in a logic low state

Minimum period that SCLK should be in a logic high state

Hardware Interface The SPI bus is the physical interface between the user’s programming device and the serial port of the HMXADC9246. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either PROM or PIC microcontrollers. This provides the user with the ability to use an alternate method to program the ADC. One method is described in detail in the ADI Application Note AN-812, Microcontroller-based Serial Port Interface Boot Circuit. When the SPI interface is not used, some pins serve a dual function. When strapped to AVDD or ground during device power-on, the pins are associated with a specific function.

Configuration without the SPI In applications that do not interface to the SPI control registers, the SDIO/DCS and SCLK/DFS pins serve as stand-alone CMOScompatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the output data format and duty cycle stabilizer. In this mode, the CSB chip select should be connected to AVDD, which disables the serial port interface. For more information, see the ADI Interfacing to High Speed ADCs via SPI User Manual.

Memory Map Reading the Memory Map Register File Each row in the memory map register table has eight address locations. The memory map is roughly divided into three sections: the chip configuration registers map (Address 0x00 to Address 0x02), the device index and transfer registers map (Address 0xFF), and the ADC functions map (Address 0x08 to Address 0x18). Memory Register Map Table displays the register address number in hexadecimal in the first column. The last column displays the default value for each hexadecimal address. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Hexadecimal Address 0x16, output_phase, has a hexadecimal default value of 0x00. This means Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 0 or 0000 in binary. This setting is the default output clock or DCO phase adjust option. The default value adjusts the DCO phase 90° relative to the nominal DCO edge and 180° relative to the data edge. Open Locations Locations marked as open are currently not supported for this device. When required, these locations should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x14). If the entire address location is open (Address 0x13), then the address location does not need to be written.

Quality and Radiation Hardness Assurance

Default Values Coming out of reset, critical registers are loaded with default values. The default values for the registers are shown in the Memory Register Map Table.

Honeywell maintains a high level of product integrity through process control, utilizing statistical process and six sigma

Logic Levels An explanation of two registers follows:

controls. It is part of a “Total Quality Assurance Program”,

• “Bit is set” is synonymous with “Bit is set to Logic 1” or “Writing Logic 1 for the bit.”

and a radiation hardness assurance strategy.

• “Clear a bit” is synonymous with “Bit is set to Logic 0” or “Writing Logic 0 for the bit.”

Screening Levels Honeywell offers several levels of device screening to meet your needs. “Engineering Devices” are available with limited performance and screening for prototype development and evaluation testing. Hi-Rel Class V Equivalent and Class Q+ Equivalent devices undergo additional screening per the requirements of MIL-STD-883.

the computer based process performance tracking system

SPI-Accessible Features A list of features accessible via the SPI and a brief description of what the user can do with these features follow. These features are described in detail in the Interfacing to High Speed ADCs via SPI User Manual. • Modes: Set either power-down or standby mode.

Reliability

• Clock: Access the DCS via the SPI.

Honeywell understands the stringent reliability requirements that space and defense systems requires and has extensive experience in reliability testing on programs of this nature. Reliability attributes of the SOI process were characterized by testing specially designed structures to evaluate failure mechanisms including hot carriers, electro-migration, and timedependent dielectric breakdown. The results are fed back to improve the process to ensure the highest reliability products.

• Offset: Digitally adjust the converter offset. • Test I/O: Set test modes to have known data on output bits. • Output Mode: Set up outputs; vary the strength of the output drivers.

In addition, our products are subjected to dynamic, accelerated life tests. The packages used are qualified through MIL-STD-883, TM 5005 Class S. Quality conformance testing is performed as an option on all production lots to ensure on-going reliability.

• Output Phase: Set the output clock polarity. • VREF: Set the reference voltage.

Serial Port Interface Timing tDS tS

tHI

tCLK

tDH

tH

tLO

CSB

SCLK

SDIO

DON’T CARE

DON’T CARE

DON’T CARE

RW

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Memory Register Map Table Addr. (Hex)

Parameter Name

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit1

Default Bit 0 (LSB)

Default Value (Hex)

Notes/ Comments

Chip Configuration Registers 00

LSB first

Soft reset 1

Soft reset

LSB first

0 = Off

chip_port_config

0

0 = Off

0 = Off

1

0 = Off

0 = Off

0

0x18

be mirrored. See the

The nibbles should

(Default)

(Default)

(Default)

(Default)

(Default)

Interfacing to High

1 = On

1 = On

1 = On

1 = On

1 = On

Speed ADCs via SPI User Manual.

01

chip_id

8-bit Chip ID Bits 7:0

Read

Default is unique

(HMXADC9246 = 0x00), (default)

only

chip ID, different for each device.

02

chip_grade

Open

Open

Open

Open

Child ID

Open

Open

Open

0 = 125

Read

Child ID used to

only

differentiate speed

MSPS

grades.

Device Index and Transfer Registers FF

device_update

Open

Open

Open

Open

Open

Open

Open

SW transfer

0x00

Synchronously transfers data from the master shift register to the slave.

Global ADC Functions 08

modes

Open

Open

PDWN

Open

Open

Internal power-down mode

0x00

000 – normal (power-up, Default)

generic modes of chip

(Default)

001 – full power-down

operation. See the

1 – standby

010 – standly

Power Dissipation and

011 – normal (power-up)

Standby Mode section

Note: External PDWN pin

and the SPI-Accessible

overrides this setting. 09

clock

Open

Open

Determines various

0 – full

Open

Open

Open

Open

Open

Features section. Duty cycle stabilizer

0x01

See the Clock Duty Cycle section and the

0 – disabled

SPI-Accessible

1 – enabled

Features section.

(Default)

Memory Register Map Table Addr. (Hex)

Parameter Name

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit1

Bit 0 (LSB)

Default Value (Hex)

Default Notes/ Comments

Flexible ADC Functions 10

offset

Digital Offest Adjust

Offset in LSBs

0111111

+31

inherent in the

011110

+30

converter. See the

011101

+29

0x00

Adjustable for offset

SPI-Accessible

...

Features section.

000010

+2

000001

+1

000000

0 (Default)

111111

1

111110

-2

111101

-3

... 100001

-31

100000 0D

test_io

-32

PN23

PN9

Global Output Test Options

0=

0=

000 – off (Default)

to High Speed ADCs

normal

normal

001 – midscale short

via SPI User Manual.

(Default)

(Default)

010 – +FS short

1=

1=

011 – -FS short

reset

reset

100 – checker board output

0x00

See the Interfacing

101 – PN 23 sequence 110 – PN 9 111 – one/zero word toggle 14

output_mode

Output Driver

Open

Output

Open

Output

Data Format Select

Configuration

Disable

Data

00 – offset binary

outputs and the

00 for DRVDD = 2.5 V

1–

Invert

(Default)

format of the data.

to 3.3 V (Default)

disabled

1=

01 – twos

10 for DRVDD = 1.8 V

0–

invert

complement

Open

Open

enabled1 16

output_phase

Output Clock Open

Open

Open

0x00

Configures the

10 – Gray Code Open

Open

0x00

See the SPI-

Polarity

Accessible Features

1 = inverted

section.

0 = normal (Default) 18

VREF

Internal Reference

Open

Open

Open

Open

Open

Open

0xC0

See the SPI-

Resistor Division

Accessible Features

00 – VREF = 1.25 V

section.

01 – VREF = 1.5 V 10 – VREF = 1.75 V 11 – VREF = 2.00 V (Default) 1 External output enable (OEB) pin must be high.

Package Outline Dimensions The HMXADC9246 is packaged in a 48 lead ceramic quad flat pack.

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Ordering Information (1)

H

MX

ADC

Source H = Honeywell

Process M = Mixed Signal X = SOI

Part Type

9246

N Package Designation N = 48 CQFP

Part Number

Z

H Total Dose Hardness H = 1x106 rad (Si) N = No Level Guaranteed

Screen Level Z = Class S \QML V Equivalent (3) Y = Class B \QML Q + Equivalent (3) E = Eng. Model (2)

(1) Orders may be faxed to 763-954-2051. Please contact our Customer Service Representative at 1-763-954-2474 for further information. (2) Engineering Device Description: Parameters are tested -55°C to 125°C, 24 hour burn-in, no radiation guaranteed. (3) This is an equivalent screening flow but not QML qualified.

QCI Testing (1) Classification

QCI Testing

QML Q+ and QML Q+ Equivalent

No lot specific testing performed. (2)

QML V and QML V Equivalent

Lot specific testing required in accordance with MIL-PRF-38535 Appendix B.

(1) QCI groups, subgroups and sample sizes are defined in MIL-PRF38535 and the Honeywell QM Plan. Quarterly testing is done in accordance with the Honeywell QM Plan. (2) If customer requires lot specific testing, the purchase order must indicate specific tests and sample sizes.

This product and related technical data is subject to the U.S. Department of State International Traffic in Arms Regulations (ITAR) 22 CFR 120-130 and may not be exported, as defined by the ITAR, without the appropriate prior authorization from the Directorate of Defense Trade Controls, United States Department of State. Diversion contrary to U.S. export laws and regulations is prohibited. This datasheet includes only basic marketing information on the function of the product and therefore is not considered technical data as defined in 22CFR 120.10. Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Find out more To learn more about Honeywell’s radiation hardened integrated circuit products and technologies, visit www.honeywell.com/microelectronics. Honeywell Aerospace Honeywell 1944 E. Sky Harbor Circle Phoenix, AZ 85034 Telephone: 1.800.601.3099 International: 602.365.3099 www.honeywell.com

N61-0996-000-000 June 2010 © 2010 Honeywell International Inc.