RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

Low Power CMOS Analog Multipliers

Supervisor:

Dr. C. Chen

Student:

Zheng Li

Department of Electrical and Computer Engineering University of Windsor

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

1. Application of Analog Multipliers Analog multiplier is an important subcircuit for many applications such as adaptive filters, frequency doublers, and modulators. It performs linear product of two continuous signals x and y, yielding an output z = Kxy, where K is a constant with suitable dimension[1]. Z=Kxy

Z=Kxy

Signal x

Signal x

Signal y

Signal y

Fig 1 The Application of Analog Multiplier

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

2. Performance Metrics of Analog Multipliers The linearity, supply voltage, power dissipation and noise are the main metrics of performance [3]. We try to design some specific structures or topologies for the analog multiplier that have low power dissipation while at the same time keeping good linearity, low supply voltage and low noise. Noise

Linearity

Power dissipation Input/output impedance Speed

Gain Supply Voltage Voltage swings

Fig 2 The Metrics of Analog Multiplier

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

3. Basic Idea of Our Low Power Design Use total current to represents the power consumption x 1 I D  K(VGS VTH )2 (1 VDS ) 2 1 I D  K[(VGS  VTH )VDS  VDS2 ] 2

[3]Where K = oCox W/L and

x

y

y Fig. 3. Power consumption and input range for (a) series structure and (b) parallel structure

VTH are the transconductance parameter and the threshold voltage of the device, respectively, and  represents the channel-length modulation effect for long channel devices. By biasing the transistors to operate in the triode region, one can reduce the drain current while keeping a relatively large input range.

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

4. Design Flow of Our structures Theoretically Computation and Analysis Simulation in the Schematic Level and Verification Layout Layout Verification ( DRC, LVS and Extraction) Simulation in the Layout Level and Verification Fabrication and Testing

(not finished)

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

5. Our First Multiplier structure VDD=1.5V Vbias=1V

Vo1

i1

i2

i3

i4

X+x

Vo2 X+x

X-x Y+y

Y-y

Fig. 4. First Multiplier Structure

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

6. Theoretical Analysis of First structure For the transistors working in the triode region, we have the equation for small signal model as id  Kvgs vDS , therefore, we have: i1  KvDS1 ( x  y )

vDS 1  vo1  Y  y

i2  KvDS 2 (x  y)

vDS 2  vo 2  Y  y

i3  KvDS 3 ( x  y )

vDS3  vo1 Y  y

i4  KvDS4(x  y)

vDS 4  vo 2  Y  y

By this equations, we have (i1  i3 )  (i2  i4 )  4Kxy The bias conditions is

vo  X  x  VTH 0  Y  y  X  x  VTH

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

7. Linearity Analysis of First structure

Fig. 5.(a) DC Response for signal x (with body effect)

Fig. 5.(b) DC Response for signal y (with body effect)

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

7. Linearity Analysis of First structure Linearity Error [%]

1 0.5 0 0.2

0.3

0.4

2x [V]

Fig. 6.(a) Linearity Error of signal x with 2y=0.4V (with and without body effect) Linearity Error [%]

3 2 1 0 0.2

0.3

0.4

2y [V]

Fig. 6.(b) Linearity Error of signal y with 2x=0.4V (with and without body effect)

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

8. Power Consumption of First Structure Power consumption can be estimated by the total supply current if the supply voltage is constant. Because we have Itotal  i1  i2  i3  i4 1 i1  i3  2 Kl ( X  Y  VTH )(Vo1  Y )  2 Kl ( x  y ) y  Ku (Vb  Vo1  VTH )2 2 1 i2  i4  2 Kl ( X  Y  VTH )(Vo 2  Y )  2 Kl ( x  y) y  Ku (Vb  Vo 2  VTH ) 2 2 2 Therefore Itotal  2 Kl ( X  Y  VTH )(Vo1  Vo 2  2Y )  4 Kl y

We could decrease the power consumption by decreasing the (X-Y), K l and signal y.

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

8. Power Consumption of First Structure I total

I total 40u

30u

30u 20u 20u 10u 0

10u 0.7

0.9

1.1

1.3

X-Y [V]

Fig. 7.(a) Total Current Versus X-Y

Fig. 7.(c) Total Currents for different signal distribution

0

1

2

3

Kl

4

Fig. 7.(b) Total Current VersusK

l

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

9. Noise Analysis of First Structure The total output noise of Fig. 5 is given by[4] 1 in2;o  4in2;lin  2in2; sat  16 KT ( g ds.l  g m ,u )df 3

gds.l  Kl ( X  Vo  VTH )

and

where

gm,u  2 Kl Ku ( X  Y  VTH )(Vo  Y )

[2] Hence the input noise is vn2;i 

in2;o 16 Kl2



kT 2 Ku [( X  Vo  VTH )  ( X  Y  VTH )(Vo  Y )] Kl 3 Kl

That implies that Ku/K l and (X-Y) should be decreased to improve the noise performance.

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

9. Noise Analysis of First Structure input-noise [aV2/Hz]

0.25

0.33

0.5

1

Fig 8(a) The input-referred noise voltage of Fig. 2

Ku/K l versus Ku/K l

input-noise [aV2/Hz]

0.7

0.9

1.1

1.3

1.5

(X-Y) V

Fig 8(b) The input-referred noise voltage of Fig. 2 versus X-Y

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

10. Layout of First Multiplier structure

Fig. 9 Layout of our first multiplier structure

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

10. Layout of First Multiplier structure When we do the layout of the structures, we consider to: •

Decrease the distance among the transistors as long as we could pass the DRC.

•

Try to decrease the length of the metal or polysilicon to decrease the parasite resistors and capacitors involved.

•

For the differential structure, try to make involved parasite resistors and capacitors symmetric.

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

11. Extracted Structure

Fig. 10 Extracted First Multiplier Structure

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

12. Comparison before and after layout

Fig. 11 (a) The comparison of total current before and after layout THD[%]

100K

Fig. 11 (b) The comparison of AC response before and after layout THD[%]

1M

100M

1G

Frequency

Fig. 11 (c) The comparison of THD for signal 2x=0.4V before and after layout with frequency

100K

1M

100M

1G

Frequency

Fig. 11 (d) The comparison of THD for signal 2y=0.4V before and after layout with frequency

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

13. Our Second Multiplier structure VDD=1.5V

X+x

iP1

iP 2 Vo1

iP 3

iP 4

X-x

Vo2

Y+y

Y-y

Ground Fig. 12. Second Multiplier Structure

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

14. Theoretical Analysis of Second structure For the PMOS transistors, we have: 1 iP1  KP (VDD  X  x  VTHP )2[1 (VDD VP1)] 2

iP 2 

1 K P (VDD  X  x  VTHP )2 [1   (VDD  VP 2 )] 2

1 iP3  KP (VDD  X  x  VTHP )2 [1   (VDD  VP3 )] 2

iP 4 

1 K P (VDD  X  x  VTHP )2 [1   (VDD  VP 4 )] 2

For the transistors N1-N4, we have: 1 i1  KN[(Y  y VP1 VTHN )(VO1 VP1)  (VO1 VP1)2 ] 2

1 i2  KN [(Y  y VO1 VTHN)(VP2 VO1 )  (VP2 VO1 )2 ] 2

1 i3  KN[(Y  y VP3 VTHN )(VO2 VP3)  (VO2 VP3)2 ] 2

1 i4  KN [(Y  y  VO2  VTHN)(VP4  VO2 )  (VP4  VO2 )2 ] 2

And also, we realized that: iP1  i1  iM 1

iP 2  i2  iM 2

iP 3  i3  iM 3

iP 4  i4  iM 4

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

14. Theoretical Analysis of Second structure The transistors M1-M4 can be considered as the resistors with resistance approximately equal to R  K (V 1  V ) ON

M

Solving the equations above with i1  i2 gives the following approximate result: V O 1  VO 2 

DD

THN

i3  i4

KN KM xy KP

which is a multiplication of two input signals, x and y The bias conditions is VP  VTHP  X  x  VDD  VTHP

For P1-P4

Y  y  VO  VTHN

For N1-N4

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

15. Linearity Analysis of Second structure

Fig. 13.(a) DC Response for signal x (with body effect)

Fig. 13.(b) DC Response for signal y (with body effect)

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

15. Linearity Analysis of Second structure Linearity Error [%]

1.5 1 0.5 0

0.2

0.3

0.4

2x [V]

Fig. 14.(a) Linearity Error of signal x with 2y=0.4V (with and without body effect) Linearity Error [%]

0.6 0.4 0.2 0.1 0

0.2

0.3

0.4

2y [V]

Fig. 14.(b) Linearity Error of signal y with 2x=0.4V (with and without body effect)

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

16. Power Consumption of Second Structure Power consumption can be estimated by total current: Itotal  iP1  iP 2  iP3  iP 4

Therefore

1 1 Itotal  KP(VDD X xVTHP )2[1(VDD VP1)] KP(VDD X xVTHP )2[1(VDD VP2)] 2 2 1 1 2  KP(VDD X xVTHP ) [1(VDD VP3)] KP(VDD X xVTHP )2[1(VDD VP4)] 2 2

Approximately, we have I total  2 K P [(VDD  X  VTHP ) 2  x 2 ] We see that the power dissipation has nothing to do with the signal y and DC bias Y for transistors N1-N4.

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

16. Power Consumption of Second Structure I total [uA]

I total [uA] when a=W/L=0.35/0.7u 80

30

60

20

40

10

20

0

0 0.4

0.45

0.5

0.55

0.6

X [V]

Fig. 15.(a) Total Current Versus X

I total[uA]

a

2a

3a

4a

Size of

KP

Fig. 15.(b) Total Current VersusK P

I total [uA] when X=0.5V and Y=1.5V, 2y=0.4V

20

20 10

0

10

0 1.5

1.45

1.4

1.35

Y [V]

Fig. 15.(c) Total Current Versus Y

0

0.1

0.2

0.3

0.4

Fig. 15.(d) Total Current Versus 2y

2y [V]

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

17. Noise Analysis of Second Structure The total output noise of Fig. 11 is given by i 8i 4i 2 n;o

2 n;lin

2 n;sat

32 16kTgds1df 16kTgds2df  kTgmdf 3

where

gds1  KN (Y VO VTHN )

gds2 KM(VDD VP VTHN) gm  KP (VDD  X  VTHP )

Then, the total input noise would be 2 n ;o

v

 8v

2 n ;lin

 4v

2 n ;sat

K P2 K P2 32 K P4  16kT 2 df  16kT 2 df  kT 2 2 df 3 KM KN KM KN

This suggests that KM , KN should be increased and KP should be decreased to improve the noise performance

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

17. Noise Analysis of Second Structure input-noise [aV2/Hz] KP

180 160 140 120 100 80 60

KM

40 20 0

KN 1

2

3

4

3 1.05

4 1.10

5

Fig 16(a) The input-referred noise voltage of Fig. 2 versus KP, KM and KN input-noise 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 1

[aV2/Hz] 8 7 6 5 4 3 2 1 0 9 1 0.95

2 1.00

5

YX (V)

Fig 16(b) The input-referred noise voltage of Fig. 2 versus Y-X

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

18. Layout of Second Multiplier structure

Fig. 17 Layout of our second multiplier structure

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

19. Extracted Structure

Fig. 18 Extracted Second Multiplier Structure

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

20. Comparison before and after layout

Fig. 19 (a) The comparison of total current before and after layout THD[%]

100K

Fig. 19 (b) The comparison of AC response before and after layout THD[%]

1M

100M

1G

Frequency

100K

1M

100M

1G

Frequency

Fig. 19 (c) The comparison of THD for signal Fig. 19 (d) The comparison of THD for signal 2x=0.4V before and after layout with frequency 2y=0.4V before and after layout with frequency

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

21. Most recommended structure by [3]

Vbias=1V

VDD=1.5V

Vo1

Vo2

X+x

X-x Y-y

Y+y Ground Fig. 20 The most recommended multiplier structure by[2]

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

22. Comparison of Three Structures Our First Structure

Our Second Structure

Most Recommended by[2]

Power Consumption

22.65u

27.15u

68.31u

Estimated

12u*12u

27u*16u

0.8%

1.5%

3.3%

2.6%

0.48%

0.9%

0.43%

0.4%

0.4%

Area Linearity Error of x Linearity Error of y THD of x

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

22. Comparison of Three Structures Our First Structure

Our Second Structure

Most Recommended by[2]

THD of y

0.51%

0.8%

1.1%

Noise

76a

128a

109a

Band width

2G

80M

80M

Number of Transistors

6

12

10

Technology

CMOS 0.35

CMOS 0.35

CMOS 0.35

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

Conclusion •

By Biasing the transistors in the linear region and decrease the drainsource voltage, we could get low current while at the same time, keeping a relatively wider input range. This is the basic idea of our low power design.

•

We try to use transistors as few as possible if we could satisfy the other performance metrics in order to get less area fabrication.

•

Body effect is an important second-order effect which we have to consider for good linearity.

•

In the layout level, for the differential structure, try to make involved parasite resistors and capacitors symmetric.

•

Post-layout simulation is important for performance verification.

•

Our two structures have less power consumption compared with the most recommended structure in [2] while keeping other performance good.

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

Reference [1] K. Bult and H. Wallinga, “A four-quadrant analog multiplier,” IEEE Journal of Solid-State Circuits, vol. Sc-21, no.3, pp. 430-435, June 1986. [2] G. Han and E. Sanchez-Sinencio, “CMOS transconductance multipliers: A tutorial,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 45, no. 12, pp. 1550-1563, December 1998. [3] B. Razavi, “Design of analog CMOS integrated circuits,” New York: McGraw-Hill, 2001. [4] K.R. Laker and W. M. C. Sansen, “Design of Analog Integrated Circuits and Systems,” New York: McGraw-Hill, 1994.

And another about 70 papers in the Literature survey. The papers I have submitted to the conferences: • A Low Power and Lower Noise CMOS Analog Multiplier • A Low Power CMOS Analog Multiplier

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS – UNIVERSITY OF WINDSOR

Thanks a lot!