MOSFET Fundamentals

MOSFET


MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor  




Time lines     




MOS specifically refers to the metal-SiO2-Si system MIS refers to more general metal-insulator-semiconductor systems 1960: invented by D. Kahng and M. Atalla at Bell Labs. 1963: CMOS, employs both NMOS and PMOS concept 1971: Intel4004, 2300 MOSFETs on chip Current: Millions gates on chip Probably the most successful man-kind technology

It is a huge field of technology and enormous business sector  

involves a lot of science and technology, and sometimes (critically) ‘black-magic’ and ‘art’ We can only ‘scratch the surface’ but hopefully give you a good foundation for you to explore more.

Basic operation principle

Formation of inversion layer

Modes of Operation






Cut-off Linear Saturation

Threshold Voltage VT:


Threshold Voltage is the Gate voltage that creates a sufficiently conductive inversion layer. 

Conventionally VT is defined as the Gate voltage that creates a inversion layer with the same (inversed) carrier concentration as the substrate.

 φ −φ ns = N a exp s sT  Vt

  

Depletion layer width

1/ 2

 2ε sε 0φs   xd =   eN a 


Maximum xdT depletion width:

 4ε sε 0 φ Fp =  eN a 

1/ 2

   

φs denotes the difference between the intrinsic Fermi level in bulk region and at the oxide junction.  

It is how much the band edges bend And is the voltage difference between bulk region and the position at the oxide junction

Depletion layer width

 2ε ε φ xd =  s 0 s  eN d


1/ 2

  

Maximum depletion width:

xdT

 4ε sε 0 φ Fn =   eN d

1/ 2

   

φs denotes the difference between the intrinsic Fermi level in bulk region and at the oxide junction.  

It is how much the band edges bend. And is the voltage difference between bulk region and the position at the oxide junction

Example


Consider a oxide to p type silicon junction at T=300K. The impurity doping concentration is Na=3x1016 cm-3. Calculate the maximum space charge width in the silicon, given that the dielectric constant of the silicon εs = 11.7. Maximum depletion width:

φ Fp

xdT

   

 Na   3 × 1016   = −0.0256 ln  = −0.376 V = −Vt ln 10   1.5 ×10   ni  −14

xdT

 4ε sε 0 φ Fp =  eN a 

1/ 2

1/ 2

 4 × 11.7 × 8.85 × 10 F/cm × 0.376 V   =  −19 16 -3 1.6 × 10 Q × 3 × 10 cm  

= 0.18 µm

Metal-Semiconductor Work Function Difference

φms




Eg   = φm − E Fs = φm −  χ + − φF  2e  

Defines different technology system 

Metal-SiO2-Si, polysilicon-SiO2-Si sytem, or other MIS systems

Example:


Calculate the metal-semiconductor difference for an Al-SiO2-Si system if the silicon is p type and doped to a concentration of Na=1016 cm-3 at T=300K. Modified workfunction of Al to SiO2 is 3.20V, modified electron affinity of Si to SiO2 is 3.25V.

φm′ = 3.2 V φms

χ m′ = 3.25 V

E g = 1.12 eV

Eg Eg     = φm − E Fs = φm −  χ + − φ F  = φm′ −  χ ′ + − φF  = −0.61 V + φF 2e 2e     Need to find out φFp for Na=1e16 cm-3

φ Fp

 Na   = −Vt ln  ni 

For T=300K, ni=1.5e10 cm-3 (from appendix B)

φ Fp

 1016   = −0.347 V = −0.0259 ln 10   1.5 × 10 

φms = −0.61 − 0.347 = −0.957 V

Metal-Semiconductor Work Function Difference


n+ polysilicon gate

φms

Eg Eg      Eg  = φm −  χ + − φ F  = χ −  χ + − φ F  = − − φ F  2e 2e      2e 

Metal-Semiconductor Work Function Difference


p+ polysilicon gate

φms

Eg Eg   Eg     Eg  −  χ + = φm −  χ + − φ F  =  χ + − φF  = + φF 2e 2e e       2e

Metal-Semiconductor Work Function Difference







Most of time, one can look up φms from a chart like this. Note φms can be either positive or negative

Oxide Charges


Voltage can build up across an insulator without induce any current 




Positive and negative charges are separated and build up

Q’ss denotes an equivalent trapped charge per unit area inside the oxide layer, result a non-zero potential difference Vox=-Q’ss/Cox across the oxide layer give Cox is the oxide unit area capacitance COX =

ε OX ε 0 tOX

MOS Capacitor: zero bias VG=0 VOX 0 + φs 0 = −φms





VG dictates the separation of the Fermi levels of metal and semiconductor if VG=0 then EF metal = EFs and the band bending plus the oxide build up voltage has to negate the metal-semiconductor workfunction difference

MOS Capacitor: under bias VG VG = VOX + φs − (VOX 0 + φs 0 ) = VOX + φs + φms





VG dictates the separation of the Fermi levels of metal and semiconductor For non-zero VG, band bending plus the oxide build up voltage has to make up the difference

Flat-band voltage


Flat-band voltage is the gate voltage under which the band bending is zero. since

VG = VOX + φs − (VOX 0 + φs 0 ) = VOX + φs + φms

Set the band bending φs=0, then VG=VFB

VFB = VOX + φms

Qss′ = φms − COX

Example


The silicon impurity doping concentration in an Al-SiO2-Si MOS structure is Na=3x1016 cm-3. For an oxide thickness of tox=20 nm and an oxide charge of Q’ss=8x1010 cm-2, calculate the flat-band voltage, given the dielectric constant of SiO2 εox=3.9 and T=300K.

For Al-SiO2-Si: φ Fp

φms = −0.61 V + φF

 Na   3 × 1016   = −0.0259 × ln  = 0.376 V = −Vt ln 10  × n 1 . 5 10    i 

φms = −0.61 V − 0.376 V = -0.986 V Unit area capacitance

VOX

COX =

ε OX ε 0 tOX

Qss′ Qss′ tOX 1.6 ×10-19 Q × 8 × 1010 cm -2 × 20 × 10-7 cm =− =− =− = −0.074 V ε OX ε 0 COX 3.9 × 8.85 × 10 −14 F/cm

VFB = VOX + φms = −0.074 − 0.986 = −1.06 V

Threshold voltage





Threshold voltage is more or less arbitrary chosen as the Gate voltage that creates a inversion layer with the same (inversed) carrier concentration as the substrate. Effectively this is the gate voltage that allows significant current flow from Source to Drain. For inversion point:

φsT = 2 φFp VTN = VoxT + φsT + φms = VoxT + 2 φFp + φms VoxT =

′ QmT t = ox (eN a xdT − Qss′ ) Cox ε oxε 0

Example


Consider an n+ polysilicon gate and a p-type silicon substrate doped to Na=5x1016 cm-3. Assume Q’ss=1011 cm-2. Determine the oxide thickness such that VTN=0.4V.

VTN = VoxT + φs + φms = VoxT + 2 φ Fp + φms

φ Fp

VoxT =

tox

ε oxε 0

(eN a xdT − Qss′ )

 Na   5 ×1016   = −0.0259 × ln  = −0.389 V = −Vt ln 10   1.5 × 10   ni 

 Eg  For n+ polysilicon gate φms = − − φ Fp   2  = −(0.56 + 0.389 ) = −0.949 V   VoxT = VTN − 2 φFp − φms = 0.4 − 2 × 0.389 + 0.949 = 0.57 V For VTN=0.4 V xdT

 4ε sε 0 φ Fp =  eN a 

1/ 2

   

−14

1/ 2

 4 × 11.7 × 8.85 × 10 F/cm × 0.389 V   =  −19 16 -3 1.6 × 10 Q × 5 × 10 cm  

= 0.142 µm

Example: (continued)


Consider an n+ polysilicon gate and a p-type silicon substrate doped to Na=5x1016 cm-3. Assume Q’ss=1011 cm-2. Determine the oxide thickness such that VTN=0.4V.

VTN = VoxT + φs + φms = VoxT + 2 φ Fp + φms For VTN=0.4 V

ε oxε 0VoxT

VoxT = 0.57 V

VoxT =

tox

ε oxε 0

(eN a xdT − Qss′ )

xdT = 0.142 µm

3.9 × 8.85 ×10 −14 F/cm × 0.57 V tox = = = 20 nm -19 16 -3 -4 11 -2 ′ eN a xdT − Qss 1.6 × 10 Q × 5 × 10 cm × 0.142 ×10 cm − 10 cm

(

Note: if reading from chart (Fig.6.21) φms~=-1.1 V

)

Example


Consider an Al-SiO2-Si MOS with a lightly doped p-type silicon substrate of Na=1014 cm-3. Assume Q’ss=1010 cm-2. oxide thickness of 50nm, determine the threshold voltage.

VTN = VoxT + φs + φms = VoxT + 2 φ Fp + φms

φ Fp

 4ε sε 0 φ Fp =  eN a 

VoxT

ε oxε 0

(eN a xdT − Qss′ )

 Na   1014   = −0.0259 × ln  = −0.228 V = −Vt ln 10   1.5 × 10   ni 

Find φms from chart (Fig. 6.21)

xdT

VoxT =

tox

1/ 2

   

φms = −0.82 V −14

1/ 2

 4 × 11.7 × 8.85 × 10 F/cm × 0.228 V   =  −19 14 -3 1.6 × 10 Q × 10 cm  

20 × 10 −7 cm (eN a xdT − Qss′ ) = −14 3.9 × 8.85 × 10 F/cm

= 2.43µm

Example (continued)


Consider an Al-SiO2-Si MOS with a lightly doped p-type silicon substrate of Na=1014 cm-3. Assume Q’ss=1010 cm-2. oxide thickness of 50nm, determine the threshold voltage.

VTN = VoxT + φs + φms = VoxT + 2 φ Fp + φms

φ Fp = −0.228 V VoxT

φms = −0.82 V

VoxT =

tox

ε oxε 0

(eN a xdT − Qss′ )

xdT = 2.43µm

20 × 10 −7 cm × 1.6 × 10 −19 Q 14 -3 −4 10 -2 10 cm 2 . 43 10 cm 10 cm = × × − = 0.133 V −14 3.9 × 8.85 ×10 F/cm

(

)

VTN = VoxT + 2 φFp + φms = 0.133 + 2 × 0.228 − 0.82 = −0.35 V

Threshold Voltage: n-channel MOSFET






Al-SiO2-Si n-channel (p-type body) Oxide layer thickness 50 nm For higher doping levels, VTN is positive For lower doping levels, VTN is negative Oxide charge significantly influences threshold voltage

Threshold Voltage: p-channel MOSFET





Al-SiO2-Si p-channel (n-type body) Oxide layer thickness 50 nm VTP is always negative Oxide charge significantly influences threshold voltage

Enhancement Mode v.s. Depletion Mode


For n-channel MOSFET (p-type body) 

Positive VTN means Enhancement Mode





Negative VTN means Depletion Mode






Attracts n carriers to the channel A gate voltage must be applied to create the inversion layer which enhance the flow of the current Repels n carriers from the channel A negative gate voltage need to be applied to create the inversion layer which depletes the flow of the current

For p-channel MOSFET (n-type body) 

Negative VTP means Enhancement Mode




Attracts p carriers to the channel

Positive VTP means Depletion Mode


Repels p carriers from the channel

Enhancement Mode v.s. Depletion Mode: n-channel

Enhancement-mode

Depletion-mode

Enhancement Mode v.s. Depletion Mode: p-channel

Enhancement-mode

Depletion-mode

Project: Due May 1st, 2008


Design a computer application (Excel spreadsheet, matlab code, Visual Basic script, etc.) to help determine p-type body doping concentration Na for a required threshold voltage VTN for an n-channel Al-SiO2-Si MOSFET. Use your program to design an n-MOSFET with threshold voltage of 10V, assume Q’ss=1x1011 cm-2 and the oxide layer thickness is 100 nm.

MOS capacitor operation scenarios


Accumulation  




Depletion   




No space charge build up Same as oxide parallel plate capacitors Space charge build up Oxide capacitance in series with depletion region capacitance Maximum build up reached at VG=VT.

Inversion   

Beyond VT, an inversion layer forms At low frequencies, behave again like an oxide parallel plate capacitor At high frequencies, however, the carrier concentration in the inversion layer can not change instantaneously, only space charge can respond

MOS capacitor operation scenarios

C ′(acc ) = COX =


ε OX ε 0 tOX

Accumulation  

No space charge build up Same as oxide parallel plate capacitors

MOS capacitor operation scenarios

C ′(depl ) =

′ COX C SD = ′ COX + C SD

tOX

ε OX ε 0  ε OX +   εs

  xd 

Depletion   

Space charge build up Oxide capacitance in series with depletion region capacitance Maximum build up reached at VG=VT.

MOS capacitor operation scenarios

Low frequency: C ′(inv ) = COX =




ε OX ε 0 tOX

Inversion: Low frequency response  

Beyond VT, an inversion layer forms At low frequencies, behave again like an oxide parallel plate capacitor

MOS capacitor operation scenarios

High frequency: C ′(inv ) = C ′(delp ) xd = xdT =

tOX


Inversion: High frequency 

ε OX ε 0  ε OX   xdT +   εs 

At high frequencies, however, the carrier concentration in the inversion layer can not change instantaneously, only space charge can respond

MOS capacitor Ideal C-V Characteristics COX =

ε OX ε 0 tOX xdT

 4ε sε 0 φFp =  eN a 

′ = Cmin tOX

′ = C FB tOX

ε OX ε 0 ε  ε ε V +  OX  s 0 t  ε s  eN a




1/ 2

   

ε OX ε 0 ε  +  OX  xdT  εs 

Flat-band capacitance corresponding to the bandbending of kT/2.

Example:


Consider an Al-SiO2-Si MOS capacitor with a p-type silicon substrate at T=300K doped to Na=1016 cm-3. The oxide thickness is 55 nm. Find Cox, C’min, and C’FB. COX =

φFp

xdT

ε OX ε 0

3.9 × 8.85 ×10 −14 Fcm -1 = = 6.28 × 10 −8 Fcm -2 -7 55 ×10 cm

tOX

 1016  Na  = −0.347 V = −Vt ln = −0.0259 × ln 10  1 . 5 10 ni ×  

 4ε sε 0 φ Fp =  eN a 

1/ 2

   

1/ 2

 4 ×11.7 × 8.85 ×10 −14 Fcm -1 × 0.347 V   =  16 -3 −19 1 . 6 10 Q 10 cm × ×  

ε OX ε 0 3.9 × 8.85 ×10 Fcm = 2.23 ×10 −8 Fcm - 2 =  3.9  ε  −7 −5 3 ×10 cm +  OX  xdT 55 ×10 cm +   11.7   εs  −14

′ = Cmin tOX

′ = C FB tOX

= 3 × 10 −5 cm

-1

′ Cmin = 0.355 COX ′ C FB = 0.8 COX

3.9 × 8.85 × 10 −14 Fcm -1 ε OX ε 0 = 5.03 × 10 −8 Fcm -2 = ε  ε ε V 3.9  11.7 × 8.85 × 10 −14 Fcm -1 × 0.0259V +  OX  s 0 t 55 × 10 −7 cm +   1.6 × 10 −19 Q × 1016 cm -3  11.7   ε s  eN a

Oxide Charge Effects