MIPS ISA and Single Cycle Datapath

Computer Science 104

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Outline of Today’s Lecture   Homework   The

#5

MIPS Instruction Set

  Datapath

and timing for Reg-Reg Operations

  Datapath

for Logical Operations with Immediate

  Datapath

for Load and Store Operations

  Datapath

for Branch and Jump Operations

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The MIPS Instruction Formats °  All MIPS instructions are 32 bits long. The three instruction formats: 31

•  R-type •  I-type •  J-type

26 op 6 bits

31

21 rs 5 bits

26 op 6 bits

31

16 rt 5 bits

21 rs 5 bits

11

6

rd 5 bits

0

shamt 5 bits

funct 6 bits

16

0 immediate

rt 5 bits

16 bits

26

0

op 6 bits

target address 26 bits

°  The different fields are: •  •  •  •  •  • 

op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction

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The MIPS Subset (We can’t implement them all!) 31

°  ADD and subtract •  add rd, rs, rt •  sub rd, rs, rt

31

°  OR Immediate: •  ori rt, rs, imm16

26 op 6 bits 26 op 6 bits

21 rs 5 bits 21 rs 5 bits

16 rt 5 bits

11 rd 5 bits

16 rt 5 bits

6 shamt 5 bits

0 funct 6 bits 0

immediate 16 bits

°  LOAD and STORE •  lw rt, rs, imm16 •  sw rt, rs, imm16 °  BRANCH: •  beq rs, rt, imm16 °  JUMP: •  j target cps 104 4

31

26 op 6 bits

0 target address 26 bits

An Abstract View of the Implementation

Clk

PC Instruction Address Ideal Instruction Memory

Instruction Rd Rs 5 5

Rt 5

Imm 16 A

Clk

32

32

ALU

Rw Ra Rb 32 32-bit Registers

32

B

32

Data Address

Ideal Data Memory

Data In Clk

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Clocking Methodology Clk Setup

Hold

Setup

Hold

. . .

. . .

Don’t Care

. . .

  All

. . .

storage elements are clocked by the same clock edge

  Cycle

Time >= CLK-to-Q + Longest Delay Path + Setup + Clock Skew

  Longest

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delay path = critical path

DataOut

An Abstract View of the Critical Path °  Register file and ideal memory: •  The CLK input is a factor ONLY during write operation •  During read operation, behave as combinational logic: -  Address valid => Output valid after “access time.” Clk

PC Instruction Address Ideal Instruction Memory

Rd Rs 5 5

Rt 5

Rw Ra Rb 32 32-bit Registers

Imm 16 32 32

ALU

32

Instruction

Clk

Data Address Data In

Ideal Data Memory

Clk

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Overview of the Instruction Fetch Unit °  The common RTL operations •  Fetch the Instruction: mem[PC] •  Update the program counter: -  Sequential Code: PC