MIPS ISA as an Example
Design a MIPS Processor •
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Instruction set overview of MIPS processors Single cycle MIPS processor – Datapath design – Controller design Multiple cycle MIPS Processor – Datapath design – Controller design •
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Registers
Instruction categories: – Load/Store – Computational – Jump and Branch – Floating Point – Memory Management – Special
$r0 - $r31
PC
3 Instruction Formats: all 32 bits wide
finite state machine; sequencer; microcode.
R type
Design a Multiple cycle MIPS Processor with Verilog at Behavioral/Structural Level (Project 5)
OP
$rs
$rt
I type
OP
$rs
$rt
Jump
OP
$rd
sa
funct
immediate
jump target
1
2
MIPS Arithmetic Instructions
R-Format Instructions 6
5
5
5
5
6
opcode
rs
rt
rd
shamt
funct
• MIPS assembly language arithmetic statement add$r10, $r11, $r12 sub$r10, $r11, $r12 • Each arithmetic instruction performs only one operation • Each arithmetic instruction fits in 32 bits and specifies exactly three operands destination ← source1 op source2 • Those operands are all contained in the datapath’s register file ($r10,$r11,$r12) – indicated by $ • Operand order is fixed (destination first)
– opcode: partially specifies what the instruction is (Note: 0 for all R-Format instructions) – funct: combined with opcode to specify the instruction – rs (Source Register): specify register containing first operand – rt (Target Register): specify register containing second operand – rd (Destination Register): specify register which will receive result of computation
3
4
1
MIPS Memory Access Instructions
MIPS Data Transfer Instructions
• MIPS has two basic data transfer instructions for accessing memory lw $t0, 4($s3) #load word from memory sw $t0, 8($s3) #store word to memory • The data is loaded into (lw) or stored from (sw) a register in the register file – a 5-bit address • The memory address – a 32-bit address – is formed by adding the contents of the base address register to the offset value – A 16-bit field meaning access is limited to memory locations within a region of ±213 or 8,192 words (±215 or 32,768 bytes) of the address in the base register – Note that the offset can be positive or negative
Instruction sw $t3,500($t4) sh $t3,502($t2) sb $t2,41($t3) lw $t1, 30($t2) lh $t1, 40($t3) lhu $t1, 40($t3) lb $t1, 40($t3) lbu $t1, 40($t3) lui $t1, 40
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6
Specifying Branch Destinations
MIPS Control Flow Instructions • MIPS conditional branch instructions: bne $s0, $s1, Lbl #go to Lbl if $s0≠$s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1 – Ex:
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if (i==j) h = i + j; bne $s0, $s1, Lbl1 add $s3, $s0, $s1 ...
Lbl1:
rs
rt
Use a register (like in lw and sw) added to the 16-bit offset – which register? Instruction Address Register (the PC) • its use is automatically implied by instruction • PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction – limits the branch distance to -215 to +215-1 instructions from the (instruction after the) branch instruction from the low order 16 bits of the branch instruction 16 offset sign-extend 00 branch dst 32 32 Add address 32 PC 32 Add 32 ? 4 32 32
• Instruction Format (I format): op
Comment Store word Store half Store byte Load word Load halfword Load halfword unsigned Load byte Load byte unsigned Load Upper Immediate (16 bits shifted left by 16)
16 bit offset
• How is the branch destination address specified? 7
8
2
Other Control Flow Instructions
MIPS Immediate Instructions •
• MIPS also has an unconditional branch instruction or jump instruction:
addi slti
j label //go to label • Instruction Format (J Format): op
Small constants are used often in typical code
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$sp, $sp, 4 $t0, $s2, 15
//$sp = $sp + 4 //$t0 = 1 if $s2