LC-3 Input and Output Summer 2008
I/O: Connecting to Outside World
So far, we’ve learned how to: compute with values in registers load data from memory to registers store data from registers to memory use the TRAP calls to deal with I/O
How do the TRAP calls work?
CMPE12 – Summer 2008 – Slides by ADB
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I/O devices types
I/O devices are characterized by Behavior Data rate
Behavior: input, output, storage Input: keyboard, motion detector, network interface Output: monitor, printer, network interface Storage: disk, CD-ROM
Data rate: how fast can data be transferred? Keyboard: 100 bytes/sec Disk: 30 MB/s Network: 1 Mb/s - 1 Gb/s
CMPE12 – Summer 2008 – Slides by ADB
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I/O Controller
Control/Status Registers
Data Registers
CPU tells device what to do -- write to control register CPU checks whether task is done -- read status register CPU transfers data to/from device
Device electronics
Performs actual operation
pixels to screen, bits to/from disk, characters from keyboard
Control/Status
CPU
Output Data
CMPE12 – Summer 2008 – Slides by ADB
Graphics Controller
Electronics
display
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Programming Interface
How are device registers identified?
How is timing of transfer managed?
Memory-mapped vs. I/O-mapped (special instructions) Asynchronous vs. synchronous
Who controls transfer?
CPU (polling) vs. device (interrupts)
CMPE12 – Summer 2008 – Slides by ADB
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I/O-mapped I/O
Specific opcode(s) for I/O (e.g. IN and OUT in x86) Two separate addressing spaces
CMPE12 – Summer 2008 – Slides by ADB
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Memory-Mapped I/O
Assign a memory address to each device register Use same memory data movement instructions (load/store) for control and data transfer The hardware will figure out that the instruction refers to a device and not to the memory
CMPE12 – Summer 2008 – Slides by ADB
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Transfer Timing
I/O events generally happen much slower than CPU cycles Synchronous Data supplied at a fixed, predictable rate CPU reads/writes every X cycles
Asynchronous Data rate less predictable CPU must synchronize with device, so that it doesn’t miss data or write too quickly
CMPE12 – Summer 2008 – Slides by ADB
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Transfer Control
Who determines when the next data transfer occurs? Polling CPU keeps checking status register until new data arrives OR device ready for next data “Are we there yet? Are we there yet?”
Interrupts Device sends a special signal to CPU when new data arrives OR device ready for next data CPU can be performing other tasks instead of polling device. “Wake me up when we get there.”
CMPE12 – Summer 2008 – Slides by ADB
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LC-3: Memory-mapped IO (Table A.3 in text) Location
I/O Register
xFE00
Keyboard Status Reg (KBSR)
Bit [15] is one when keyboard has received a new character.
xFE02
Keyboard Data Reg (KBDR)
Bits [7:0] contain the last character typed on keyboard.
xFE04
Display Status Register (DSR)
Bit [15] is one when device ready to display another char on screen.
xFE06
Display Data Register (DDR)
Character written to bits [7:0] will be displayed on screen.
CMPE12 – Summer 2008 – Slides by ADB
Function
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Input from the keyboard
When a character is typed:
Its ASCII code is placed in bits [7:0] of KBDR (bits [15:8] are always zero) The “ready bit” (KBSR[15]) is set to one
Keyboard is disabled -- any typed characters will be ignored
When KBDR is read:
KBSR[15] is set to zero, that is
Keyboard is enabled
15
8 7
keyboard data
0
KBDR 1514
0
ready bit
KBSR
CMPE12 – Summer 2008 – Slides by ADB
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Basic polling routine: GETC POLL NO
Polling
new char?
LDI R0, KBSRPtr BRzp POLL LDI R0, KBDRPtr ...
YES
read character
KBSRPtr .FILL xFE00 KBDRPtr .FILL xFE02
(look it up – it’s GETC, at x0400)
CMPE12 – Summer 2008 – Slides by ADB
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Hardware implementation of memorymapped input
Address Control Logic determines whether MDR is loaded from Memory or from KBSR/KBDR.
CMPE12 – Summer 2008 – Slides by ADB
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Output to Monitor
When Monitor is ready to display another character:
The “ready bit” (DSR[15]) is set to one
When data is written to Display Data Register: DSR[15] is set to zero Character in DDR[7:0] is displayed Any other character data written to DDR is ignored while DSR[15] is zero
15
8 7
output data
0
DDR 1514
ready bit CMPE12 – Summer 2008 – Slides by ADB
0
DSR 14
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Basic polling routine: PUTC POLL NO
Polling
screen ready?
LDI R1, DSRPtr BRzp POLL STI R0, DDRPtr ...
YES
write character
DSRPtr .FILL xFE04 DDRPtr .FILL xFE06
CMPE12 – Summer 2008 – Slides by ADB
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Hardware implementation of memorymapped output
Sets LD.DDR or selects DSR as input. CMPE12 – Summer 2008 – Slides by ADB
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Keyboard Echo Routine
Usually, input character is also printed to screen. POLL1
POLL2
LDI BRzp LDI LDI BRzp STI
R0, KBSRPtr POLL1 R0, KBDRPtr R1, DSRPtr POLL2 R0, DDRPtr
... KBSRPtr KBDRPtr DSRPtr DDRPtr
.FILL .FILL .FILL .FILL
NO
YES
read character
NO
xFE00 xFE02 xFE04 xFE06
CMPE12 – Summer 2008 – Slides by ADB
new char?
screen ready? YES
write character
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Interrupt-Driven I/O
Polling consumes a lot of cycles, especially for rare events – these cycles can be used for computation. Example: Process previous input while collecting current input. In a more efficient approach, an external device can: (1) (2) (3)
Force currently executing program to stop; Have the processor satisfy the device’s needs; and Resume the stopped program as if nothing happened.
CMPE12 – Summer 2008 – Slides by ADB
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Interrupt-Driven I/O
To implement an interrupt mechanism, we need three things A way for the I/O device to signal the CPU that an interesting event has occurred A way for the CPU to test whether the interrupt signal is set A way for the CPU to test whether its priority is higher than the current program’s
CMPE12 – Summer 2008 – Slides by ADB
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Interrupt generation
Software sets "interrupt enable" (IE) bit in device register (interrupt mask) When ready bit is set and IE bit is set, interrupt is signaled. interrupt enable bit 1514 13
0
KBSR ready bit
CMPE12 – Summer 2008 – Slides by ADB
interrupt signal to processor
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Testing for the interrupt signal
CPU looks at signal between STORE and FETCH phases If not set, continue with next instruction If set, transfer control to interrupt service routine
FF NO YES
Transfer Transfer to to ISR ISR
interrupt signal?
D D EA EA OP OP EX EX S S
CMPE12 – Summer 2008 – Slides by ADB
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Priority
Every instruction executes at a stated level of urgency LC-3 has 8 priority levels, from PL0 (lowest) to PL7 It’s OK for PL6 device to interrupt PL0 program, but not the other way around Example:
Payroll
program runs at PL0. Nuclear power correction program runs at PL6.
Priority encoder selects highest-priority device, compares to current processor priority level, and generates interrupt signal if appropriate
CMPE12 – Summer 2008 – Slides by ADB
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Priority encoding for interrupt
CMPE12 – Summer 2008 – Slides by ADB
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Full implementation of LC-3 memorymapped I/O
Because of interrupt enable bits, status registers (KBSR/DSR) must be writable, as well as readable.
CMPE12 – Summer 2008 – Slides by ADB
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Ok, the interrupt interrupted
How am I (the program) going to resume execution after the interrupt service routine is done? Where do I save my stuff? We need a stack
CMPE12 – Summer 2008 – Slides by ADB
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Recommended exercises
Good review questions: 8.3, 8.6, 8.9, 8.10, 8.14 Interesting for interrupt enable: 8.15 (but the code requires… adjustments to actually work in the simulator)
CMPE12 – Summer 2008 – Slides by ADB
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