Department of Electrical and Computer Engineering

CMOS Comparator Design Extra Slides Vishal Saxena, Boise State University ([email protected])

Vishal Saxena

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Comparator Design Considerations 

Comparator =    



Preamp (optional) + Reference Subtraction (optional for single-bit case) + Regenerative Latch +Static Latch to hold outputs (optional)

Design Considerations      

Accuracy (dynamic and static offset, noise, resolution) Settling time (tracking BW, regeneration speed) Sensitivity/resolution (gain) Metastability (ability to make correct decisions) Overdrive recovery (memory) Power consumption

Vishal Saxena

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An Example CMOS Comparator Vos orginiates from: VDD

M3 M4

M5

•

Preamp input pair mismatch (Vth,W/L)

•

PMOS loads and current mirror

•

Latch offset

•

Charge-Injection

M6 Φ

Vos M1 M2

Vo

+

Vi

V oM9

M7

M8

VSS

Preamp

Latch

Vishal Saxena

clock-feedthru imbalance of the reset switch (M9) •

Clock routing

•

Parasitics

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Latch Regeneration VDD

Φ M5

Vo

+

M6 Φ Vo M9

CL M7

PA tracking Latch Latch reseting regenrating

VDD

-

Vo+ CL

M8

Vo VoVSS

VSS

•

Exponential regeneration due to positive feedback of M7 and M8

Vishal Saxena

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Regeneration Speed – Linear Model

Vo+

Vo+

Vo-

CL

CL M7



CL

-1 gmVo-

M8

    Vo   Vo     V   g  V m o /sCL  o

Vo-

1  Vo   1     0     1 gm /sCL  Vo 

Δs  gm /sCL  1  0  sp  gm /CL , singleRHP pole

Vo t  0  Vo t  0 expt  gm /CL 

Vishal Saxena

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Reg. Speed – Linear Model

Vo+

Vo-

CL

CL M7

Vo(t=0)

M8

Vo

Vo(t=0)

t/(CL/gm)

1V

100mV

2.3

1V

10mV

4.6

1V

1mV

6.9

1V

100μV

9.2

Vishal Saxena

t

t

Vo = 1V

CL  Vo t    ln  gm  Vo t  0

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Reg. Speed – Linear Model Reg. Speed – Linear Model Vm+

M3 M4 Vm+

M5

V mM1 M2

x

Vo

+

Vi

Vm-

M6 Φ=1

Vo-

gm5Vm+



Vo+

M9 M7

A V1 

gm1 gm3

R9 2

R9 2

Vo-

X

M8

A V2 

gm5Vm-

-1 gm7

-1 gm7

gm5R9 R9 1 ,  to be amplifier. 2  gm7R9 2 gm7

Vo 0  Vi 0 A V  Vi 0 A V1A V2 Vo t   Vi 0 A V1A V2  expt  gm /CL  Vishal Saxena

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Comparator Metastability Reg. Speed T/2 – Linear Model

Vo t   Vi 0 A V1A V2  expt  gm /CL 

Φ

Curve

AV1AV2

Vi(t=0)



10

10 mV



10

1 mV



10

100 μV



10

10 μV

1 2 3 4 Vo+ Vo

-

Comparator fails to produce valid logic outputs within T/2 when input falls into a region that is sufficiently close to the comparator threshold

Vishal Saxena

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Comparator Metastability Reg. Speed – Linear Model Do

Δ

Assuming that the input is uniformly distributed over VFS, then

j+1

Δ BER  1LSB

Vi

j

Vo t   Vi 0 A V1A V2  expt  gm /CL  Vos

•

Cascade preamp stages (typical flash comparator has 2-3 pre-amp stages)

•

Use pipelined multi-stage latches; pre-amp can be pipelined too

Vishal Saxena

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Charge-Injection and Clock-Feedthrough in Latch

Reg. Speed – Linear Model M5 Vo+

Cgs

Cgd

Vo-

M9

CL M7

•

Φ

Φ

M6

CL

CM jump

M8

Vo+ Vo-

Charge injection (CI) and clock-feedthrough (CF) introduce CM jump

in Vo+ and Vo•

Dynamic latches are more susceptible to CI and CF errors

Vishal Saxena

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Dynamic Offset of a Latch Reg. Speed – Linear Model Dynamic offset derives from:

Φ

Vo

+

Vo-

•

Imbalanced CI and CF

•

Imbalanced load capacitance

•

Mismatch b/t M7 and M8

•

Mismatch b/t M5 and M6

•

Clock routing

0.5V CM jump    50mV offset 10% imbalance 

Dynamic offset is usually the dominant offset error in latches

Vishal Saxena

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Typical CMOS Comparator

Reg. Speed – Linear Model VDD

M3 M4

M5

M1 M2

Vo

+

Vi

Input-referred latch offset gets divided by the gain of PA

•

Preamp introduces its own offset (mostly static due to Vth, W, and L mismatches)

•

PA also reduces kickback noise

M6 Φ

Vos

•

V oM9

M7

M8

VSS

Preamp

Latch

Kickback noise disturbs reference voltages, must settle before next sample

Vishal Saxena

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Comparator Offset

Reg. Speed – Linear Model VDD

M3 M4

M5

Differential pair mismatch:

M6

2

 W Δ   1 2 2 2 L Vos   ΔVth   Vov  W  4    L  gm5R9 g A V1  m1 A V2  2  gm7R9 gm3

Φ

Vos M1 M2

Vo+

Vi

V oM9

M7

M8

VSS

Preamp

Total input-referred comparator offset:

Latch

Vos,34  Vos,56 2

Vos  Vos,12  2

2

Vishal Saxena

A

2

2 V1

2



Vos,78 A

2 V1

A V2

2



Vos,dyn 2

2

A V1 A V2

2

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Recall: Matching Properties

Reg. Speed – Linear Model Suppose parameter P of two rectangular devices has a mismatch error of ΔP. The variance of parameter ΔP b/t the two devices is 2

A 2 σ ΔP   P  SP D2 , WL 2

1st term dominates for small devices

where, W and L are the effective width and length, D is the distance

A Vth2 Threshold : σ  Vth  = + S Vth2D2 WL σ 2 β  A β2 Current factor :   Sβ 2D2 2 β WL 2

Ref: M. J. M. Pelgrom, et al., “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433-1439, issue 5, 1989. Vishal Saxena

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Recall: Device Sizing for Mismatch

Reg. Speed – Linear Model R R 1

W

X

2

X

X

X

X

L

R1  RS 

L with std σR1 W

X

…

X

X

10 identical resistors

 L  R2  RS 10    10R1 with std σR2 , W 10

σR2   σR j 2  10σR12  σR2  10σR1 2

j1

σR2 10σR1 σR 1  σR1  1 1        R2 10R1 R 10  R1  A WL

Vishal Saxena

“Spatial averaging”

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Pre-amp Design 

A fully-differential gain-stage   



Avoid or use simple CMFB Pre-amp gain reduces input referred offset due to the latch Autozeroing techniques for offset storage and reduction

Pre-amp open-loop gain vs tracking bandwidth trade-off 

Multiple stages of pre-amp limit bandwidth •

Optimum value of stages 2-4

N stages:    A0 A0  AN  ω       1 ω / ω 2  1  j  ω / ω0   0  N

A N  ω  ω3dB  

Vishal Saxena

A 0N 2

1 N

, ω3dB  ω0 2  1

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N

   

Pre-amp (PA) Autozeroing Φ2' Φ1

C

M3

Vo+

Vos

Vi A

Vi+

Vo-

Φ2'

Vo Φ2

M4

M5

M6

M1

M2

Vi-

 Finite preamp gain : VOS , preamp VOS ,in  A  For the overall comparator :

 2V

OS ,in



 2V

OS , pre

2

A

pre



 2V

OS ,latch

2

A

pre

Vishal Saxena

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Pre-amp Design: Pull-up load  NMOS diode pull  up : AV  

Pull-up Vo+ Vi+

VoM1

M2

gm1  gmL

W L 1 W L L

 PMOS diode pull  up :

Vi-

AV  

gm1 μ W L 1  n gmL μp W L L

 Resistorpull  up : A V  gm1  RL •

NMOS pull-up suffers from body effect, affecting gain accuracy

•

PMOS pull-up is free from body effect, but subject to P/N mismatch

•

Gain accuracy is the worst for resistive pull-up as resistors (poly, diffusion, well, etc.) don’t track transistors; but it is fast!

Vishal Saxena

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Pre-amp Design: More Gain M3

Ip

Ip

M4

Vo +

Vo-

AV   Vi+

M1

M2

Vi-

gm1 μ  I 2  W L 1  n gm3 μp  I 2  Ip  W L 3

I

•

Ip diverts current away from PMOS diodes (M3 & M4), reducing (W/L)3

•

Higher gain without CMFB

•

Needs biasing for Ip

•

M3 & M4 may cut off for large Vin, resulting in a slow recovery

Vishal Saxena

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Faster Settling Pre-amp M3 M5

M6 M4

Vo +

1 gm3

Vo-

gm1Vid

Vid

Vi+

M1

M2

-1 gm5

ro3

ro5

ro1

Vod

ViDM gain : A V

M7

dm

 1  gm1    gm3

  1  g r //ro1//ro3 //ro5    m1 o1 //   3  gm5  

•

NMOS diff-pair loaded with PMOS diodes and a PMOS cross-coupled latch

•

High DM gain, low CM gain, good CMRR

•

Simple, no CMFB required

•

(W/L)34 > (W/L)56 needs to be ensured for stability

•

Ref: K. Bult and A. Buchwald, “An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2,” JSSC, vol. 32, pp. 1887-1895, issue 12, 1997.

Vishal Saxena

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Pre-amp Example M3

M4 RL

Vo

RL

+

VoX

Vi+

M1

M2

Vi-

M5

•

NMOS diff. pair loaded with PMOS diodes and resistors

•

High DM gain, low CM gain, good CMRR

•

Simple, no CMFB required

•

Gain not well-defined

•

Ref: B.-S. Song et al., “A 1 V 6 b 50 MHz current-interpolating CMOS ADC,” in Symp. VLSI Circuits, 1999, pp. 79-80. Vishal Saxena

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Pre-amp Example

•

NMOS diff. pair loaded with PMOS Current mirror • Simple CMFB circuit

•

Gain is well-defined

Ref: V. Srinivas, S. Pavan, A. Lachhwani, and N. Sasidhar, “A Distortion Compensating Flash Analog-to-Digital Conversion Technique," IEEE JSSC, vol. 41, no. 9, pp. 1959-1969, Sep. 2006. Vishal Saxena

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Latch Design •

Regenerative latches for faster settling • See lecture notes

•

At least one cross-coupled regenerative core • Local positive feedback • Numerous methods for applying the input initial signal to regenerate upon

• Latches can have large static and dynamic offsets •

Large Regenerative gain for resolving small inputs • Metastability (wrong or incomplete decisions) when latch can’t make decision

• Pre-amp can be used for amplifying the inputs (slower tracking BW) •

One size doesn’t fit all applications • Speed vs power consumption trade-off

Vishal Saxena

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Static Latch

Vi+

M3

M4 M2

M1

• Active pull-up and pull-down → full CMOS logic levels Vi-

• Q+ and Q- are not well defined in reset mode (Φ = 1)

Φ

Q+

Q-

M7 M5

• Very fast!

• Large short-circuit current in reset mode • Zero DC current after full regeneration

M6

• Supply is very noisy

Vishal Saxena

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Semi-Dynamic Latch • Diode divider disabled in reset mode → less short-circuit current Φ

Vi+

• Pull-up not as fast

M8

M3

M4 M2

M1

Vi-

• Zero DC current after full regeneration

Φ

Q+

Q-

M7

M5

• Q+ and Q- are still not well defined in reset mode (Φ = 1)

• Supply still very noisy

M6

Vishal Saxena

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Dynamic Latch • Zero DC current in reset mode Φ

M7

M5

M6

Q+

M1

M9

M3

• Q+ and Q- are both reset to “0” • Full logic level after regeneration

QΦ

Vi+

Φ

M8

• Slow

Φ

M10

M4

M2

Vi-

Vishal Saxena

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Dynamic Latch 2

Φ

M7

M5

M6

Φ

M8

+

-

Q

Q Φ

M9 M3

Vi+

• Slow

M4

M1

M2

• Q+ and Q- are both reset to “0”

• Full logic level after regeneration

Φ

M10

• Zero DC current in reset mode

Vi-

Ref: T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,” JSSC, vol. 30, pp. 166-172, issue 3, 1995. Vishal Saxena

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Current-Steering/CML Latch Φ

RL

Vi+

M1 Φ

RL

M2

Q+

Q-

M7

Vi-

M3

M4 Φ

M5

M8

• Current mode logic (CML) latch • Constant current → supply very quite • Higher gain in tracking mode

M6

• Cannot produce full logic levels

• Fast • Popular for high-speed designs • Trip point of the inverters

Vishal Saxena

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PA Autozeroing Example

I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” IEEE JSSC March 2000, pp. 318-25.

Vishal Saxena

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Reference Subtraction

S. Pavan, N. Krishnapura, R. Pandarinathan, P. Sankar, "A Power Optimized Continuous-time Delta-Sigma Modulator for Audio Applications," IEEE JSSC, vol. 43, no. 2, pp. 351-360, Feb. 2008.

Vishal Saxena

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Autozeroing and Reference Subtraction

Pre-amp V. Srinivas, S. Pavan, A. Lachhwani, and N. Sasidhar, “A Distortion Compensating Flash Analog-to-Digital Conversion Technique," IEEE JSSC, vol. 41, no. 9, pp. 1959-1969, Sep. 2006. Vishal Saxena

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CML based Comparator

CML-Latch V. Singh, N. Krishnapura, S. Pavan, B. Vigraham, D. Behera, and N. Nigania, “A 16MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay," IEEE JSSC, vol. 47, no. 8, Aug. 2012. Vishal Saxena

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Comparators for Pipelined ADCs 

Pipelined ADCs employ at least 0.5 bit/stage redundancy 



Should consume negligible power in a good design •



Can tolerate large offsets and large noise with appropriate redundancy

50-100 mW or less per comparator

Lots of implementation options  

Resistive/capacitive reference generation Different pre-amp/latch topologies

Vishal Saxena

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Comparators for Pipelined ADCs

Vishal Saxena

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Comparator Example

A 6-b 1.3-Gsample/s A/D Converter in 0.35-m CMOS IEEE JSSC, vol. 36, no. 12, Dec 2001.

Vishal Saxena

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Latch Example

A 0.9-V 60-W 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range IEEE JSSC, vol. 43, no. 2, Feb. 2008

Vishal Saxena

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Comparator Example

A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded ΔΣ Modulator, IEEE JSSC, vol. 43, no. 4, Apr 2008

Vishal Saxena

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Comparator Example

I. Galdi, 40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW, IEEE JSSC, vol. 39, no. 8, pp. 1341–1346, Aug. 2004.

Vishal Saxena

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Comparator Example

Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," IEEE JSSC, vol. 39, pp. 2139 - 2151, December 2004.

Vishal Saxena

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Comparator Example

B. Min, P. Kim, F. W. Bowman, D. M. Boisvert, and A. J. Aude, "A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC," IEEE JSSC, vol. 38, pp. 2031 - 2039, Dec. 2003.

Vishal Saxena

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Comparator Example

J. Lin and B. Haroun, "An embedded 0.8 V/480 µW 6B/22 MHz flash ADC in 0.13 µm digital CMOS Process using a nonlinear double interpolation technique," IEEE JSSC, vol. 37, pp. 1610 - 1617, Dec. 2002.

Vishal Saxena

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Comparator Example

S . Limotyrakis, S. D. Kulchycki, D. Su, and B. A. Wooley, "A 150MS/s 8b 71mW time-interleaved ADC in 0.18µm CMOS," proc. IEEE ISSCC, pp. 258 - 259, Feb 2004.

Vishal Saxena

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Exercise 

Compare the latches with respect to     

Static power dissipation Dynamic and static Offsets Kickback noise at the input Number of clock phases Maximum achievable clock speed

Vishal Saxena

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References 1. 2. 3. 4.

Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters,” 2nd Ed., Springer, 2005. N. Krishnapura, Analog IC Design, IIT Madras, 2008. Y. Chiu, Data Converters Lecture Slides, UT Dallas 2012. B. Boser, Analog-Digital Interface Circuits Lecture Slides, UC Berkeley 2011.

Vishal Saxena

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