Features • • • • •

28-bit Prescaler Programmable Time-out Period Fully Synchronous Protected Turn-off Sequence Up to 100% Fault Coverage with Scan Test

Description The AVR® embedded RISC microcontroller core is a low-power, CMOS 8-bit microprocessor based on the AVR RISC architecture. With this core, Atmel supplies a Watchdog Timer.

Watchdog Timer

The Watchdog Timer generates a timeout signal if it has not been reset after a certain number of clock cycles. This can be used to exit from endless loops. The Watchdog Timer is a fully synchronous peripheral.

Embedded RISC Microcontroller Core Peripheral

Figure 1. Watchdog Timer Pin Configuration cp2 ireset runmod AVR Control

dbus_in[7:0]

dbus_out[7:0]

AVR Control

out_en

cs cs_adr[5:0] adr[5:0] iore

Watchdog Timer

iowe

wdtmout Watchdog

Scan Test

wdri

wdcnt[28:0]

test_se test_si

test_so

Watchdog

Scan Test

Rev. 1344A–02/00

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Table 1. Pin Description Pin Name

Function

I/O

Comments AVR Control

cp2

CPU Clock

Input

Any register in the watchdog will update its content only on the rising edge of cp2.

ireset

Synchronous Reset

Input

When high, ireset will reset internal registers by reading the value on dbus_in which is forced to zero by the AVR core.

runmod

Run Control

Input

When low, runmod stops all the internal functions (count) of the watchdog. Only the interface register continues to function normally.

dbus_out[7:0]

Data Bus Output

dbus_in[7:0]

Data Bus Input

Input

out_en

Output Enable

Output

When high, out_en indicates that the watchdog is requiring the control of the data bus.

cs

Chip Select

Input

When adr[5:0] = cs_adr[5:0] and cs is high, the Watchdog Timer is addressed and iore and iowe are active.

cs_adr[5:0]

Chip Select Address

Input

Watchdog Timer base address. When cs is high and adr[5:0] = cs_adr[5:0], the Watchdog Timer is addressed and iore and iowe are active. cs_adr is NOT dynamic and therefore MUST be established at power-up.

adr[5:0]

I/O Address

Input

Valid only when accompanied by a strobe on iore or iowe

iore

I/O Read Strobe

Input

Used to read the content of the I/O location addressed by adr.

iowe

I/O Write Strobe

Input

Used to update the content of the I/O location addressed by adr.

Output

Valid only when accompanied by a strobe on out_en, otherwise held at zero. Data bus input.

Watchdog Timer wdri

Watchdog Reset Input

wdtmout

Watchdog Time-out

Output

Input

Depending on WDTCR[3:0], wdtmout will indicate the time-out of the watchdog.

Watchdog reset instruction input. When high, wdri resets the watchdog.

wdcnt[28:0]

Watchdog Counter

Output

State of internal watchdog timer. Test Scan

test_se

Scan Enable Output

Input

Test scan enable (active high).

test_si

Scan Chain 1 Input

Input

Scan chain input.

test_so

Scan Chain 1 Output

Output

Scan chain output.

Figure 2. Watchdog Timer

WDE

wdtmout

2

Watchdog Timer

fCP2/262144K

fCP2/65536K

fCP2/131072K

fCP2/8192K

fCP2/32768K

From Watchdog Timer Control Register WDTCR WDP0 WDP1 WDP2 WDP3

fCP2/16384K

fCP2/4096K

fCP2/2048K

fCP2/512K

fCP2/1024K

fCP2/256K

fCP2/64K

fCP2/128K

fCP2/16K

wdri

fCP2/32K

cp2

Watchdog Timer Functional Description The Watchdog Timer is clocked by the system clock cp2. By controlling the watchdog timer prescaler, the watchdog timeout interval can be adjusted from 16K to 262,144K x TCP2. The WDR - Watchdog Reset - instruction resets the watchdog timer. Fifteen different multiples of the clock cycle period can be selected to determine the timeout period. If the timeout period expires without another watchdog reset, the wdtmout pin is held high during half the watchdog timeout period, or until wdri is asserted. This assertion must reset the AVR core. To prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is disabled. Refer to the description of the Watchdog Timer Control Register for details.

Watchdog Timer Chip Select (CS) The watchdog timer has the ability to be remapped inside the AVR I/O address range. To access the internal I/O location of the watchdog timer, the following conditions must be true: • adr[5:0] = cs_adr[5:0] • cs = 1 Under these conditions, iore and iowe are used to access internal I/Os to read or to write. The cs_adr bus input is NOT dynamic and therefore must be set at power-up. Instead of cs_adr, cs may be used dynamically to decode, for example, multiple I/O pages. The binary value of cs_adr[5:0] is the Base Address (BaseAdr) for Watchdog Timer addressing. It locates the Watchdog Timer Control Register WDTCR.

THE WATCHDOG TIMER CONTROL REGISTER - WDTCR Bit

7

6

5

4

3

2

1

0

BaseAdr

-

-

WDTTOE

WDE

WDP3

WDP2

WDP1

WDP0

Read/Write

R

R

R/W

R/W

R/W

R/W

R/W

R/W

Initial value

0

0

0

0

0

0

0

0

Bits 7..6 - Res : Reserved bits:

These bits are reserved bits and will always read as zero. Bit 5 - WDTOE : Watchdog Turn-off Enable:

This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog Timer will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for the watchdog disable procedure. Bit 4 - WDE : Watchdog Enable:

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the watchdog timer function is disabled. WDE can only be cleared if the WDTOE bit is set (one). To disable an enabled watchdog timer, the following procedure must be followed:

WDTCR

1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is already set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical zero to WDE. This disables the watchdog. Bits 3..0 - WDP3, WDP2, WDP1, WDP0 : Watchdog Timer Prescaler 3, 2, 1 and 0:

The WDP3, WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding timeout periods are shown in Table 2. The WDP3, WDP2, WDP1 and WDP0 bits must be set before enabling the Watchdog Timer.

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Table 2. Watchdog Timer Prescale Select WDP3

WDP2

WDP1

WDP0

Timeout Period

0

0

0

0

16K x TCP2

0

0

0

1

32K x TCP2

0

0

1

0

64K x TCP2

0

0

1

1

128K x TCP2

0

1

0

0

256K x TCP2

0

1

0

1

512K x TCP2

0

1

1

0

1024K x TCP2

0

1

1

1

2048K x TCP2

1

0

0

0

4096K x TCP2

1

0

0

1

8192K x TCP2

1

0

1

0

16384K x TCP2

1

0

1

1

32768K x TCP2

1

1

0

0

65536K x TCP2

1

1

0

1

131072K x TCP2

1

1

1

0

262144K x TCP2

1

1

1

1

Reserved

Scan Test Configuration The AVR Watchdog Timer peripheral has been designed with a full scan methodology which results in a 100% maximum fault coverage. The coverage is maximum if all non-scan inputs can be controlled and all non-scan outputs can be observed. In order to acheive this, the ATPG vectors must be generated on the entire circuit (top level) which includes the AVR Watchdog Timer. The scan test pins can then be connected for serial or parallel scan.

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Watchdog Timer

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